Thermally tunable anti-ambipolar heterojunction devices

Abstract

Two-dimensional materials and their van der Waals heterostructures have emerged as a research focal point for constructing various innovative electronic devices due to their distinct photonic and electronic properties. Among them, anti-ambipolar devices, characterized by their unique nonlinear electrical behavior, have garnered attention as novel multifunctional components, positioning them as potential contenders for building multi-state logic devices. Utilizing the properties of few-layer As_0.4P_0.6 and PdSe₂, we have constructed an anti-ambipolar heterojunction device. At 300 K, the device exhibits a peak voltage (V_peak) of −3 V and a peak-to-valley ratio (PVR) close to 8 × 10³, and the PVR can be modulated by bias voltage. Furthermore, by characterizing the anti-ambipolar attributes at different temperatures ranging from 80 K to 330 K, we have elucidated the thermally tunable feature of the device. At 330 K, a certain PVR (∼10³) and a large V_peak (∼−16 V) are obtained, while a PVR exceeding 10⁸ has been achieved at 80 K. This temperature-related sensitivity empowers the device with significant potential and thermal tunability in various applications.

---

1. Introduction

In recent years, two-dimensional (2D) materials and their van der Waals heterojunctions (vdWHs) have shown great potential to gradually replace conventional semiconductors as building blocks for multifunctional devices due to their unique optical, electronic, and magnetic properties, and their dangling bond-free surface.^1–8 Various device types based on heterojunctions have been demonstrated, such as tunneling field-effect transistors,^5,9,10 memory devices,^11,12 photodetectors,^13,14 p–n junction diodes,^15,16 rectification devices,^17–19etc. Among them, the anti-ambipolar property device, which was initially realized by a gate-tunable carbon-nanotube/monolayer-layer MoS₂ p–n heterojunction,²⁰ has attracted a great deal of attention. The anti-ambipolar property exhibits a nonlinear feature, which results in a significant decrease in electrical current with an increase in the gate voltage.^21,22 Recently, this property has also been observed in numerous vdW p–n heterojunctions, such as p-WSe₂/n-SnS₂,²³ p-WSe₂/n-WS₂,²⁴ p-WSe₂/n-MoS₂,²⁵etc. Considering that the anti-ambipolar property behaves similarly to a negative differential resistance (NDR), it also shows promise for applications in logic circuit design.²⁶ Even more exciting, in these anti-ambipolar devices, the peak-to-valley ratio (PVR), serving as a crucial parameter for evaluating device performance, can reach as high as 10³–10⁵ at room temperature,²³ significantly surpassing existing NDR devices.^27,28 These advantages make anti-ambipolar devices potential candidates for constructing three-channel devices for signal processing and information storage, and make them more promising for practical applications in multi-valued logic circuits compared to NDR devices.^25,29,30

However, to date, the comprehension of the mechanism behind anti-ambipolar behaviors remains the main requirement for in-depth and extended investigation,²¹ and although recent studies have begun to explore the temperature-dependent anti-ambipolar characteristics,^31,32 there remains a lack of comprehensive research on ambipolar behavior across a wide temperature range. Specifically, the influence of temperature on the PVR from 77 K to 330 K has not been thoroughly investigated. Additionally, the design and fabrication of appropriate anti-ambipolar field-effect transistor (FET) devices using vdWHs pose a huge challenge, thereby impeding the advancement of logic devices founded on this distinctive characteristic.^21,33–35 Recently, arsenic phosphorus (As_0.4P_0.6), a material synthesized from ultrapure gray arsenic and red phosphorus,^36–38 has attracted more attention. As_0.4P_0.6 with high carrier mobility and a narrow bandgap of about 0.36 eV typically exhibits p-type behavior. This is a suitable material for building devices, inspired by black phosphorus (BP)-based FETs.^39,40 Also, palladium diselenide (PdSe₂) is an emerging air-stable n-type dominant 2D material, with high room temperature mobility and a widely tunable bandgap (0.03–1.3 eV).^41–43 Considering band alignment and material properties, As_0.4P_0.6 and PdSe₂ are suitable materials for constructing p–n heterojunctions and probable anti-ambipolar devices.

In this study, we have presented an anti-ambipolar device built upon the vdWH composed of As_0.4P_0.6 and PdSe₂. Our research demonstrates the realization of high-performance thermally tunable anti-ambipolar devices, where the drain is implemented using As_0.4P_0.6, the source employs PdSe₂, and the heterojunction area serves as the channel. At room temperature, a PVR of ∼8 × 10³ and a peak voltage (V_peak) of −3 V can be attained. In particular, we uncover the thermally tunable sensitivity of the anti-ambipolar device, which can be used to finely tune the PVR and V_peak of the device via the temperature. At low temperature, we achieved a PVR exceeding 10⁸. Furthermore, as the temperature reached 330 K, the anti-ambipolar characteristics were suppressed to a certain degree. Our work presents a heterojunction device fabricated using the previously unreported combination of As_0.4P_0.6 and PdSe₂, aiming to contribute to the field of anti-ambipolar devices. We believe that the distinctive behavior observed in the PdSe₂/As_0.4P_0.6 heterojunction, particularly its thermally tunable anti-ambipolar characteristics, offers valuable insights and potential applications in multifunctional device design.

2. Experimental

2.1. Fabrication and characterization of the anti-ambipolar heterojunction device

The few-layer PdSe₂ and As_0.4P_0.6 were achieved by mechanical exfoliation from their bulk counterpart using tap (NITTO 224S) and clean polydimethylsiloxane (PDMS). A Si substrate covered by a SiO₂ layer (285 nm) was cleaned in turn with acetone, isopropanol, and deionized water for 10 min. The few-layer As_0.4P_0.6 and PdSe₂ were transferred onto the PDMS and then onto the SiO₂/Si substrate in turn. After that, the SiO₂–Si substrate with As_0.4P_0.6 and PdSe₂ was spin-coated with PMMA 950K (3000 rpm, 60 s) and placed on a hot plate at 180 °C for 2 min. The electrode pattern was defined using standard electron beam lithography (Vistec EBPG 5000plus ES), and Cr (5 nm)–Au (60 nm) electrodes were deposited using electron beam evaporation (BOC-500).

2.2. Characterization analyses

An optical microscopic image of the device was obtained using an optical microscope (Olympus, LEXT-OLS4000), the electron microscopic image of the device was characterized using a transmission electron microscope (TEM, Tecnai G2 F20 U-TWIN), and the thickness of the sample was characterized using an atom force microscope (AFM, Bruker Multimode 8HR). The material quality was characterized using a Raman spectroscope (Renishaw InVia plus, 514 nm excitation laser). All the electrical measurements were conducted on a manual probe station (Lakeshore, TTP4) equipped with a vacuum pump, a temperature control system, and a semiconductor characterization system (Keithley 4200A-SCS).

3. Results and discussion

A schematic of the three-dimensional view of the PdSe₂/As_0.4P_0.6 vdWH device is shown in Fig. 1a. The few layers of PdSe₂ and As_0.4P_0.6 were acquired by mechanical exfoliation from bulk materials, and then stacked through an all dry transfer method (details are given in the Experimental section and Fig. S1, ESI†). As shown in the blue dashed frame in Fig. 1, crystalline PdSe₂ has a pentagonal structure, and As_0.4P_0.6 belongs to the typical orthogonal crystal phase. To further confirm their lattice structure, the exfoliated PdSe₂ and As_0.4P_0.6 flakes were transferred onto Cu grids for TEM measurements, respectively. As_0.4P_0.6 on a Cu grid is shown in Fig. S2a (ESI†), and the high-resolution TEM image of As_0.4P_0.6 (Fig. S2b, ESI†) clearly shows the pentagonal structure of the As_0.4P_0.6 with the (001) planes (lattice constant of 4.4 Å) and (100) planes (lattice constant of 3.5 Å). The high-quality single-crystal nature of As_0.4P_0.6 is further confirmed by the corresponding selected area electron diffraction (Fig. S2c, ESI†). The low-magnification TEM image of the PdSe₂ is presented in Fig. S1d (ESI†), and the high-resolution TEM and SAED images (Fig. S2e and f, ESI†) show that the lattice spacings are 2.92 Å and 2.82 Å, which are attributed to the (020) and (200) planes of the PdSe₂, indicating that the PdSe₂ is a single crystal with an orthogonal crystal structure.

Fig. 1 Characterizations of the heterojunction device. (a) Three-dimensional schematic representation of the device, where the enlarged region within the blue dashed box highlights the heterojunction area. The lower layer is As_0.4P_0.6, while the upper layer is PdSe₂. (b) The OM image of the device, the white dashed box represents the presence of PdSe₂, while the red dashed box highlights As_0.4P_0.6, scale bar: 20 μm. (c) The Raman spectra of As_0.4P_0.6, PdSe₂, and the heterojunction, respectively. The Raman peaks within the heterojunction exhibit characteristic peak positions including both materials. (d) Localized AFM images of the heterojunction. (e) The thickness of As_0.4P_0.6 with the measurement curve taken along the white dashed line on As_0.4P_0.6 in (d). (f) The thickness of PdSe₂ with the measurement curve along the white dashed line on PdSe₂ in (d).

An optical microscope (OM) image of the fabricated device is shown in Fig. 1b; the white dashed frame outlines the PdSe₂ and the red dashed frame outlines the As_0.4P_0.6. Raman characterizations of PdSe₂, As_0.4P_0.6, and the heterojunction area (PdSe₂ as the top layer) are shown in Fig. 1c. The A¹_g–B¹_1g, A²_g, B²_1g, and A³_g modes of the PdSe₂ are positioned at 143, 206, 222, and 256 cm⁻¹, respectively. Furthermore, the three peaks of As_0.6P_0.4 at 253, 349, and 430 cm⁻¹ correspond to the A¹_g, B_2g, and A²_g modes, respectively. The characteristic peaks of both PdSe₂ and As_0.4P_0.6 can be seen in the Raman spectra of the heterojunction, indicating that As_0.4P_0.6 and PdSe₂ remain unchanged after the formation of the heterojunction. Fig. 1d shows an AFM image of the heterojunction, measured along the white dashed lines in Fig. 1d, respectively. Thicknesses of 8.38 nm and 4.03 nm were obtained for the few-layers of As_0.4P_0.6 and PdSe₂, respectively, as shown in Fig. 1e and f.

Utilizing heavily doped silicon as the back gate, individual characterization of the transfer curves for PdSe₂ and As_0.4P_0.6 was conducted, as depicted distinctly in Fig. 2a, prior to measuring the electrical properties of the heterojunction. The transfer characteristics obtained reveal that the current through As_0.4P_0.6 augments concomitantly with increasing negative gate voltages, indicative of its p-type behavior. On the other hand, the current of PdSe₂ exhibits an inclination to increase in response to both positive and negative gate voltages, with a minimum current manifesting at a gate voltage of −30 V, which corresponds to the OFF state and unequivocally signifies a preponderance of n-type dominant ambipolar behavior. The output characteristics of PdSe₂ and As_0.4P_0.6 under diverse bias voltages are respectively illustrated in Fig. S3 and S4 (ESI†), evincing an absence of pronounced rectification. This suggests that the contact potential barrier between the electrode and the material is minimal, ensuring that the electrical tests can accurately reflect the intrinsic properties of the materials. Based on the p–n behavior exhibited by the two materials, the As_0.4P_0.6 side is designated as the drain electrode, while the PdSe₂ side serves as the source electrode.

Fig. 2 Characterization of the transfer properties of the heterojunction device. (a) The transfer characteristics curves of As_0.4P_0.6 (in blue) and PdSe₂ (in red) under a forward bias voltage of 1 V. (b) The transfer characteristics curves of the heterojunction under various forward biases (from 0.2 V to 2 V, step 0.2 V). (c) The three-dimensional transfer characteristics curves of the heterojunction under various forward biases. (d) The dependence of PVR on forward biases.

Fig. 2b shows the transfer characteristics of the device under several forward biases, manifesting pronounced anti-ambipolar properties. When the gate voltage is below −30 V, the device is primarily in the OFF state. With increasing gate voltage, the current gradually increases under a constant bias. When the gate voltage is over the V_peak (∼−3 V), the current exhibits a decreasing trend that is similar to negative differential conductance. It is observed that as the bias voltage increases from 0.2 V to 2 V, the magnitude of the current decline also increases, showing increasingly prominent anti-ambipolar properties. The mapping plot of this phenomenon is clearly illustrated in Fig. 2c. To further investigate the current variation within the gate voltage range of −30 to 20 V, the PVR is calculated by taking the ratio of the maximum and minimum currents. The resulting PVR curve demonstrates a monotonically increasing trend, and the PVR can reach a maximum of approximately 8 × 10³ at a bias voltage of 1.8 V, showing the high performance of the anti-ambipolar characteristic at room temperature.

The transfer curve, demonstrating an analogous negative differential transconductance phenomenon, has engendered our focal interest. Fig. 3a illustrates the transfer curve at V_ds = 0.5 V. The transfer curve can be divided into four regions. In region I, the back gate voltage is less than −40 V, and the PdSe₂ channel is depleted, which results in the minimum drain current and indicates that the device is fully turned off. In region II, the back gate voltage is about −40 to −10 V, the bias current starts to be dominated by the PdSe₂ channel, and the holes in As_0.4P_0.6 and the electrons in PdSe₂ are gradually accumulated and participate in the current transport, leading to the ON-state in the entire p–n junction. In region III, the back gate voltage is about −10 to 15 V, and it is partially pinched off due to the depletion of electron carriers in the As_0.4P_0.6 channel being much faster than the increase in the PdSe₂ channel, causing the decrease in overall channel current. On the other hand, the whole device cannot be completely turned off because of the small band gap (0.326 eV) of As_0.4P_0.6 and the strong capacitance screening effect, which is similar to that in BP.⁴⁴ This phenomenon leads to the device having two OFF-states, and the ON/OFF ratios are about 10⁴ and 10², respectively. In region IV, the back gate voltage is over 15 V, the PdSe₂ channel regains dominance and the current in both channels starts to increase. In conclusion, the transfer curve can be modulated by the gate voltage.

Fig. 3 Energy band and thermally tunable transfer properties of the heterojunction device. (a) The transfer characteristic curve at a forward bias voltage of 0.5 V, which can be divided into four regions. (b) The corresponding energy band bending of the four regions in the transfer characteristic curve in (a). (c) The transfer characteristic curve of the heterojunction under a forward bias voltage of 2 V for temperatures ranging from 80 K to 300 K. (d) The transfer characteristic curve of the heterojunction under a forward bias voltage of 2 V for temperatures ranging from 310 K to 330 K. (e) At a temperature of 140 K, the bias current mapping plot of the heterojunction is presented on a semi-logarithmic scale as a function of bias voltage and gate voltage. (f) At a temperature of 330 K, the bias current mapping plot of the heterojunction is presented on a semi-logarithmic scale as a function of bias voltage and gate voltage.

The energy band diagrams of this heterojunction under gate voltage are shown in Fig. 3b. The band diagram of PdSe₂/As_0.4P_0.6/SiO₂/Si before contact is shown in Fig. S5 (ESI†), showing a type-II band alignment between As_0.4P_0.6 and PdSe₂. The energy positions of the valence and conduction band are referred from previous reports.^36,45,46 The gate voltage can provide the unique behavior by controlling the bending of the energy band in the channel region. When the forward gate voltage is less than −40 V and the bias is forward, both As_0.4P_0.6 and PdSe₂ are p-type, with their Fermi levels close to the valence band, the barrier formed at the interface between As_0.4P_0.6 and PdSe₂ hinders the hole transport, resulting in the device being in an almost completely OFF state. As the gate voltage is increased, PdSe₂ transitions to n-type, and the Fermi levels are close to the conduction band. The energy band of PdSe₂ bends upwards and the energy band of As_0.4P_0.6 is pulled downwards, reducing the barrier between the two materials. Under forward bias, electrons transfer from PdSe₂ to As_0.4P_0.6, while holes transfer from As_0.4P_0.6 to PdSe₂, resulting in an increase in current. However, when the gate voltage exceeds −10 V, although the energy bands of As_0.4P_0.6 continue to pull downwards, further reducing the barrier and allowing electrons to transfer from PdSe₂ to As_0.4P_0.6, the holes in As_0.4P_0.6 are rapidly depleted as the gate voltage increases. This significant reduction in hole transfer from As_0.4P_0.6 to PdSe₂ results in a decrease in current. When the gate voltage increases to exceed 15 V, as the energy bands of As_0.4P_0.6 continue to be pulled downwards, a type-I heterojunction is formed, allowing a substantial number of electrons to transfer from PdSe₂ to As_0.4P_0.6, leading to an increase in current. With increasing gate voltage, the current of the device initially increases and reaches a peak at V_g = −10 V and then decreases, demonstrating obvious anti-ambipolar behavior. Here the band alignment between As_0.4P_0.6 and PdSe₂ has a shift with a change in gate voltage and thereby regulates the transport of electrons and holes within the heterojunction, which is crucial to the anti-ambipolar behavior.

To further understand the transport of the PdSe₂/As_0.4P_0.6 heterojunction device, the electrical transport was also investigated at different temperatures and different directional drain biases. Fig. 3c shows the I_ds–V_ds curves on a semilog coordinate at low temperatures when a 2 V forward bias is applied. It can be noted from the curves that the gate voltage control of the band bending is still present at low temperatures and that the gate voltage of the device in the OFF state increases as the temperature decreases. The two OFF-state voltages of the anti-ambipolar increase from −40 V and 20 V at 300 K to −35 V and 45 V at 140 K, respectively. At temperatures below 100 K, there will be no PdSe₂ channel-dominated electron transport, and the current will not increase again after the gate voltage has increased to the threshold, as the thermionic emission is completely suppressed. Considering the different electrical transport behavior after complete suppression of thermionic emission,⁴⁷ the devices were warmed up to further investigate the effect of thermionic emission on the devices. As shown in Fig. 3d, when the temperature of the device rises to 330 K, it is obvious that the current change resulting from the gate voltage modulation of the band bending disappears. It is thought that as the gate voltage pulls the valence band of the As_0.4P_0.6 near the PdSe₂ conduction band, the drain current is maintained rather than falling rapidly due to the strong hot electron emission, which suppresses the ambipolar characteristics.

Fig. 3e shows mapping of the I_ds at 140 K for the device as functions of V_g and V_ds. This mapping diagram clearly illustrates that the band bending can be regulated by gate voltage at 140 K to produce two OFF-states at V_g < −40 V and 40 V < V_g < 60 V, and can return to an open state again at higher gate voltages, making this anti-ambipolar characteristic well-suited for the fabrication of logic devices such as inverters. In Fig. 3f, I_ds mapping at 330 K, shows the disappearance of the second OFF-state and the reduction in the range of the first OFF-state as the device warms up, indicating that at 330 K the device is only in the OFF-state when the gate voltage is about 40 V, demonstrating flexibility in the construction of multifunctional devices.

To gain a more profound comprehension of the anti-ambipolar characteristics of the device, the study of the device at different temperatures is further investigated, as shown in Fig. 4a. At V_g = 2 V, the anti-ambipolar properties exhibit pronounced temperature dependence, notably manifested in the discernible shift of V_peak. At 300 K, the V_peak stands at −3 V. As temperature decreases, the V_peak experiences a slight augmentation, reaching 20 V at 80 K. Conversely, with rising temperature, the V_peak undergoes a declining trend, eventually reaching −16 V at 330 K. This phenomenon shows potential for the construction of multifunctional logic devices. However, at temperatures exceeding 300 K, the peak current (I_peak) depicted in the transfer curve registers a decrease compared to the low-temperature regime. Considering the varying OFF-state currents at different temperatures, further characterization of the PVR across different temperature conditions is presented in Fig. 4b. Notably, as the temperature descends to 80 K, an exceptionally high PVR surpassing 10⁸ is attained. This signifies an unprecedentedly high PVR value, emphasizing the outstanding performance of the device. Even at temperatures around 330 K, the PVR remains consistently above 10³, reflecting the ability of the anti-ambipolar device to maintain excellent performance at higher temperatures.²¹ At low temperatures, thermally excited carriers are suppressed, resulting in an extremely high PVR. As the temperature increases, thermal excitation leads to more carriers being excited from the valence band to the conduction band, increasing the carrier concentration. Consequently, more electrons and holes participate in conduction, which may increase the device's current. Additionally, the carrier mobility increases with rising temperature, further enhancing the device's conductivity. These factors may contribute to a reduction in PVR. As for V_peak, the increased carrier concentration and mobility at higher temperatures reduce the voltage required to reach the peak value. V_peak and PVR, as two critical parameters for evaluating anti-ambipolar devices, exhibit robust performance across a wide temperature range. Notably, the changes in V_peak and PVR with temperature are inversely related, enabling precise control of the device's V_peak and PVR by adjusting the temperature. This allows for flexible modulation of the anti-ambipolar behavior. These characteristics indicate that it is possible to modulate the PVR and V_peakvia temperature adjustments, and thus achieve a degree of thermal tunability of the anti-ambipolar behavior, which offers new avenues for the design of multifunctional logic circuits.

Fig. 4 Thermally tunable anti-ambipolar and gate-dependent output properties of the heterojunction device. (a) The transfer characteristic curve under a forward bias of 2 V at different temperatures (from 80 K–330 K). (b) The relationship curve between multiple forward biases and their corresponding PVR. (c) The output characteristic curve at room temperature under different gate voltage (from −40 to 60 V). (d) The corresponding rectification ratios (RF ratio = I_2V/I_−2V) under different gate voltages (from −40 to 60 V).

When the gate voltage is −40 V, the device is in the OFF state and exhibits reverse rectification. As the gate voltage increases, the reverse rectification effect gradually decreases, as shown in Fig. 4c. At a gate voltage of −20 V, the device changes from reverse to forward rectification. When the gate voltage is at 10–20 V, gate voltage regulation of the band bending reduces the forward bias current from 10⁻⁶ A to 10⁻⁷ A. With a further increase in gate voltage, the reverse current gradually increases due to the dominance of the current generated by hot electron emission, and the device again shows a tendency toward reverse rectification. Fig. 4c shows the relationship between the corresponding rectification ratios and the gate voltage, which implements the conversion between reverse and forward rectifications.

4. Conclusions

We have successfully constructed a high-performance thermally tunable anti-ambipolar device by using an As_0.4P_0.6/PdSe₂ heterojunction. At room temperature, the device exhibits an anti-ambipolar characteristic with a PVR of around 8 × 10³ and a V_peak of −3 V, exhibiting outstanding anti-ambipolar properties. Furthermore, our anti-ambipolar heterojunction device demonstrates temperature-dependent behavior, maintaining a high PVR while achieving a low V_peak of −20 V at high temperature. At lower temperature, an exceptionally high PVR of 10⁸ is achieved, demonstrating exceptional performance. These findings underscore the outstanding performance of our device, with immense potential in applications for constructing multifunctional circuits like multi-valued logic circuits and analog circuitry.

Author contributions

Qian Liu, Xinzheng Zhang, and Cong Wang conceived and directed the study. Shengyao Chen, Jiyou Jin, and Wenxiang Wang carried out the investigations. Shengyao Chen, Jiyou Jin, Shu Wang, Xiaoshan Du, Feng Wang, Lijun Ma, and Junqi Wang discussed and optimized the parameters of the devices. Shengyao Chen, Jiyou Jin, Wenxiang Wang, Qian Liu, Xinzheng Zhang, and Cong Wang wrote the manuscript. All authors discussed the results, commented on the paper, and approved the final manuscript.

Data availability

The authors confirm that the data supporting the findings of this study are available within the article and its ESI.† Further data and information can be obtained from the corresponding authors.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was supported by the National Natural Science Foundation of China (No. 51971070, 10974037, 62205011, and 12074201), the National Key Research and Development Program of China (No. 2016YFA0200403), the Eu-FP7 Project (No. 247644), the CAS Strategy Pilot Program (No. XDA 09020300), the Fundamental Research Funds for the Central Universities (No. buctrc202122) and the Open Research Project of Special Display and Imaging Technology Innovation Center of Anhui Province (No. 2022AJ05001).

Notes and references

1. K. S. Novoselov, A. Mishchenko, A. Carvalho and A. H. Castro Neto, 2D materials and van der Waals heterostructures, Science, 2016, 353, aac9439.
2. R. Cheng, F. Wang, L. Yin, Z. Wang, Y. Wen, T. A. Shifa and J. He, High-performance, multifunctional devices based on asymmetric van der Waals heterostructures, Nat. Electron., 2018, 1, 356–361.
3. Y. Liu, Y. Huang and X. Duan, van der Waals integration before and beyond two-dimensional materials, Nature, 2019, 567, 323–333.
4. A. K. Geim and I. V. Grigorieva, van der Waals heterostructures, Nature, 2013, 499, 419–425.
5. L. Britnell, R. V. Gorbachev, R. Jalil, B. D. Belle, F. Schedin, A. Mishchenko, T. Georgiou, M. I. Katsnelson, L. Eaves, S. V. Morozov, N. M. R. Peres, J. Leist, A. K. Geim, K. S. Novoselov and L. A. Ponomarenko, Field-Effect Tunneling Transistor Based on Vertical Graphene Heterostructures, Science, 2012, 335, 947–950.
6. C. Wang, R.-C. Xiao, H. Liu, Z. Zhang, S. Lai, C. Zhu, H. Cai, N. Wang, S. Chen, Y. Deng, Z. Liu, S. A. Yang and W.-B. Gao, Room-temperature third-order nonlinear Hall effect in Weyl semimetal TaIrTe₄, Natl. Sci. Rev., 2022, 9, nwac020.
7. W. J. Yu, Z. Li, H. Zhou, Y. Chen, Y. Wang, Y. Huang and X. Duan, Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters, Nat. Mater., 2013, 12, 246–252.
8. M. Huang, S. Li, Z. Zhang, X. Xiong, X. Li and Y. Wu, Multifunctional high-performance van der Waals heterostructures, Nat. Nanotechnol., 2017, 12, 1148–1154.
9. S. Jiang, L. Li, Z. Wang, J. Shan and K. F. Mak, Spin tunnel field-effect transistors based on two-dimensional van der Waals heterostructures, Nat. Electron., 2019, 2, 159–163.
10. T. Georgiou, R. Jalil, B. D. Belle, L. Britnell, R. V. Gorbachev, S. V. Morozov, Y.-J. Kim, A. Gholinia, S. J. Haigh, O. Makarovsky, L. Eaves, L. A. Ponomarenko, A. K. Geim, K. S. Novoselov and A. Mishchenko, Vertical field-effect transistor based on graphene–WS₂ heterostructures for flexible and transparent electronics, Nat. Nanotechnol., 2013, 8, 100–103.
11. X. Sun, C. Zhu, J. Yi, L. Xiang, C. Ma, H. Liu, B. Zheng, Y. Liu, W. You, W. Zhang, D. Liang, Q. Shuai, X. Zhu, H. Duan, L. Liao, Y. Liu, D. Li and A. Pan, Reconfigurable logic-in-memory architectures based on a two-dimensional van der Waals heterostructure device, Nat. Electron., 2022, 5, 752–760.
12. W. Huang, F. Wang, L. Yin, R. Cheng, Z. Wang, M. G. Sendeku, J. Wang, N. Li, Y. Yao and J. He, Gate-Coupling-Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in van der Waals Ferroelectric Heterojunctions, Adv. Mater., 2020, 32, 1908040.
13. R. Tian, X. Gan, C. Li, X. Chen, S. Hu, L. Gu, D. Van Thourhout, A. Castellanos-Gomez, Z. Sun and J. Zhao, Chip-integrated van der Waals PN heterojunction photodetector with low dark current and high responsivity, Light: Sci. Appl., 2022, 11, 101.
14. H. Wang, Z. Li, D. Li and P. Chen, L. Pi, X. Zhou and T. Zhai, van der Waals Integration Based on Two-Dimensional Materials for High-Performance Infrared Photodetectors, Adv. Funct. Mater., 2021, 31, 2103106.
15. C.-H. Lee, G.-H. Lee, A. M. van der Zande, W. Chen, Y. Li, M. Han, X. Cui, G. Arefe, C. Nuckolls, T. F. Heinz, J. Guo, J. Hone and P. Kim, Atomically thin p–n junctions with van der Waals heterointerfaces, Nat. Nanotechnol., 2014, 9, 676–681.
16. J. Y. Lim, M. Kim, Y. Jeong, K. R. Ko, S. Yu, H. G. Shin, J. Y. Moon, Y. J. Choi, Y. Yi, T. Kim and S. Im, van der Waals junction field effect transistors with both n- and p-channel transition metal dichalcogenides, npj 2D Mater. Appl., 2018, 2, 37.
17. X. Zhang, B. Liu, L. Gao, H. Yu, X. Liu, J. Du, J. Xiao, Y. Liu, L. Gu, Q. Liao, Z. Kang, Z. Zhang and Y. Zhang, Near-ideal van der Waals rectifiers based on all-two-dimensional Schottky junctions, Nat. Commun., 2021, 12, 1522.
18. S. Kim, H. Du, T. Kim, S. Shin, H.-k Song, H. Kim, D. Kang, C.-W. Lee and S. Seo, Gate-switchable rectification in isotype van der Waals heterostructure of multilayer MoTe₂/SnS₂ with large band offsets, npj 2D Mater. Appl., 2020, 4, 15.
19. D. S. Schulman, A. J. Arnold and S. Das, Contact engineering for 2D materials and devices, Chem. Soc. Rev., 2018, 47, 3037–3058.
20. D. Jariwala, V. K. Sangwan, C.-C. Wu, P. L. Prabhumirashi, M. L. Geier, T. J. Marks, L. J. Lauhon and M. C. Hersam, Gate-tunable carbon nanotube–MoS₂ heterojunction p-n diode, Proc. Natl. Acad. Sci., 2013, 110, 18076–18080.
21. Y. Wakayama and R. Hayakawa, Antiambipolar Transistor: A Newcomer for Future Flexible Electronics, Adv. Funct. Mater., 2020, 30, 1903724.
22. L. Wu, W. Gao, Y. Sun, M. Yang, Z. Zheng, W. Fan, K. Shu, Z. Dan, N. Zhang, N. Huo and J. Li, Polarity-Switchable and Self-Driven Photo-Response Based on Vertically Stacked Type-III GeSe/SnS₂ Heterojunction, Adv. Mater. Interfaces, 2022, 9, 2102099.
23. Y. Wang, W.-X. Zhou, L. Huang, C. Xia, L.-M. Tang, H.-X. Deng, Y. Li, K.-Q. Chen, J. Li and Z. Wei, Light induced double ‘on’ state anti-ambipolar behavior and self-driven photoswitching in p-WSe₂/n-SnS₂ heterostructures, 2D Mater., 2017, 4, 025097.
24. N. Huo, J. Yang, L. Huang, Z. Wei, S.-S. Li, S.-H. Wei and J. Li, Tunable Polarity Behavior and Self-Driven Photoswitching in p-WSe₂/n-WS₂ Heterojunctions, Small, 2015, 11, 5430–5438.
25. Y. Li, Y. Wang, L. Huang, X. Wang, X. Li, H.-X. Deng, Z. Wei and J. Li, Anti-Ambipolar Field-Effect Transistors Based On Few-Layer 2D Transition Metal Dichalcogenides, ACS Appl. Mater. Interfaces, 2016, 8, 15574–15581.
26. J. Shim, S. Oh, D.-H. Kang, S.-H. Jo, M. H. Ali, W.-Y. Choi, K. Heo, J. Jeon, S. Lee, M. Kim, Y. J. Song and J.-H. Park, Phosphorene/rhenium disulfide heterojunction-based negative differential resistance device for multi-valued logic, Nat. Commun., 2016, 7, 13413.
27. T. P. E. Broekaert, W. Lee and C. G. Fonstad, Pseudomorphic In_0.53Ga_0.47As/AlAs/InAs resonant tunneling diodes with peak-to-valley current ratios of 30 at room temperature, Appl. Phys. Lett., 1988, 53, 1545–1547.
28. K. Kobashi, R. Hayakawa, T. Chikyow and Y. Wakayama, Negative Differential Resistance Transistor with Organic p-n Heterojunction, Adv. Electron. Mater., 2017, 3, 1700106.
29. D. Jariwala, V. K. Sangwan, J.-W. T. Seo, W. Xu, J. Smith, C. H. Kim, L. J. Lauhon, T. J. Marks and M. C. Hersam, Large-Area, Low-Voltage, Antiambipolar Heterojunctions from Solution-Processed Semiconductors, Nano Lett., 2015, 15, 416–421.
30. Y. Meng, W. Wang, W. Wang, B. Li, Y. Zhang and J. Ho, Anti-Ambipolar Heterojunctions: Materials, Devices, and Circuits, Adv. Mater., 2024, 36, 2306290.
31. Y. Lv, C.-Y. Wu, Y. Zhao, G. Wu, M. Abid, J. Cho, M. Choi, C. Ó. Coileáin, K.-M. Hung, C.-R. Chang, Y.-R. Wu and H.-C. Wu, Robust Anti-Ambipolar Behavior and Gate-Tunable Rectifying Effect in van der Waals p–n Junctions, ACS Appl. Electron. Mater., 2022, 4, 5487–5497.
32. R. J. Mathew, K.-H. Cheng, C. R. P. Inbaraj, R. Sankar, X. P. A. Gao and Y.-T. Chen, An Anti-Ambipolar Cryo-Phototransistor, Adv. Electron. Mater., 2023, 9, 2300095.
33. D. Jariwala, V. K. Sangwan, L. J. Lauhon, T. J. Marks and M. C. Hersam, Emerging Device Applications for Semiconducting Two-Dimensional Transition Metal Dichalcogenides, ACS Nano, 2014, 8, 1102–1120.
34. R. Hu, E. Wu, Y. Xie and J. Liu, Multifunctional anti-ambipolar p-n junction based on MoTe₂/MoS₂ heterostructure, Appl. Phys. Lett., 2019, 115, 073104.
35. Z. Wang, X. He, X.-X. Zhang and H. N. Alshareef, Hybrid van der Waals p–n Heterojunctions based on SnO and 2D MoS₂, Adv. Mater., 2016, 28, 9133–9141.
36. S. Li, J. Zhang, L. Zhu, K. Zhang, W. Gao, J. Li and N. Huo, Reconfigurable and Broadband Polarimetric Photodetector, Adv. Funct. Mater., 2023, 33, 2210268.
37. B. Liu, M. Köpf, A. N. Abbas, X. Wang, Q. Guo, Y. Jia, F. Xia, R. Weihrich, F. Bachhuber, F. Pielnhofer, H. Wang, R. Dhall, S. B. Cronin, M. Ge, X. Fang, T. Nilges and C. Zhou, Black Arsenic–Phosphorus: Layered Anisotropic Infrared Semiconductors with Highly Tunable Compositions and Properties, Adv. Mater., 2015, 27, 4423–4429.
38. L. Wu, T. Fan, S. Wei, Y. Xu, Y. Zhang, D. Ma, Y. Shu, Y. Xiang, J. Liu, J. Li, K. Panajotov, Y. Qin and H. Zhang, All-optical logic devices based on black arsenic–phosphorus with strong nonlinear optical response and high stability, Opto-Electron. Adv., 2022, 5, 200046.
39. M. Xie, S. Zhang, B. Cai, Y. Huang, Y. Zou, B. Guo, Y. Gu and H. Zeng, A promising two-dimensional solar cell donor: Black arsenic–phosphorus monolayer with 1.54 eV direct bandgap and mobility exceeding 14 000 cm² V⁻¹ s⁻¹, Nano Energy, 2016, 28, 433–439.
40. N. Izquierdo, J. C. Myers, P. Golani, A. De Los Santos, N. C. A. Seaton, S. J. Koester and S. A. Campbell, Growth of black arsenic phosphorus thin films and its application for field-effect transistors, Nanotechnology, 2021, 32, 325601.
41. H. Wang, Z. Li, D. Li, X. Xu, P. Chen, L. Pi, X. Zhou and T. Zhai, Junction Field-Effect Transistors Based on PdSe₂/MoS₂ Heterostructures for Photodetectors Showing High Responsivity and Detectivity, Adv. Funct. Mater., 2021, 31, 2106105.
42. M. Long, Y. Wang, P. Wang, X. Zhou, H. Xia, C. Luo, S. Huang, G. Zhang, H. Yan, Z. Fan, X. Wu, X. Chen, W. Lu and W. Hu, Palladium Diselenide Long-Wavelength Infrared Photodetector with High Sensitivity and Stability, ACS Nano, 2019, 13, 2511–2519.
43. W. Ahmad, J. Liu, J. Jiang, Q. Hao, D. Wu, Y. Ke, H. Gan, V. Laxmi, Z. Ouyang, F. Ouyang, Z. Wang, F. Liu, D. Qi and W. Zhang, Strong Interlayer Transition in Few-Layer InSe/PdSe₂ van der Waals Heterostructure for Near-Infrared Photodetection, Adv. Funct. Mater., 2021, 31, 2104143.
44. S. Das, W. Zhang, M. Demarteau, A. Hoffmann, M. Dubey and A. Roelofs, Tunable Transport Gap in Phosphorene, Nano Lett., 2014, 14, 5733–5739.
45. Z. Wang, N. Ali, T. D. Ngo, H. Shin, S. Lee and W. J. Yoo, Achieving Ultrahigh Electron Mobility in PdSe₂ Field-Effect Transistors via Semimetal Antimony as Contacts, Adv. Funct. Mater., 2023, 33, 2301651.
46. X. Zhao, Q. Zhao, B. Zhao, X. Dai, S. Wei and Y. Ma, Electronic and optical properties of PdSe₂ from monolayer to trilayer, Superlattices Microstruct., 2020, 142, 106514.
47. A. Allain, J. Kang, K. Banerjee and A. Kis, Electrical contacts to two-dimensional semiconductors, Nat. Mater., 2015, 14, 1195–1205.

---

Footnotes

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d4cp02937b

‡ These authors contributed equality to this work.

---