Oxide and 2D TMD semiconductors for 3D DRAM cell transistors

Abstract

As the downscaling of conventional dynamic random-access memory (DRAM) has reached its limits, 3D DRAM has been proposed as a next-generation DRAM cell architecture. However, incorporating silicon into 3D DRAM technology faces various challenges in securing cost-effective high cell transistor performance. Therefore, many researchers are exploring the application of next-generation semiconductor materials, such as transition oxide semiconductors (OSs) and metal dichalcogenides (TMDs), to address these challenges and to realize 3D DRAM. This study provides an overview of the proposed structures for 3D DRAM, compares the characteristics of OSs and TMDs, and discusses the feasibility of employing the OSs and TMDs as the channel material for 3D DRAM. Furthermore, we review recent progress in 3D DRAM using the OSs, discussing their potential to overcome challenges in silicon-based approaches.

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Jae Seok Hur

Jae Seok Hur received a BS degree from Kyunghee University, South Korea, majoring in Information Displays in 2016. Subsequently, he received a MS degree from Hanyang University, South Korea, majoring in Information Display Engineering in 2019. Currently, he is studying toward a PhD degree at the Department of Electronic Engineering at Hanyang University. His research interests include n-type oxide semiconductor materials and devices based on atomic layer deposition, as well as emerging thin-film transistor technologies and their applications.

Sungsoo Lee

Sungsoo Lee received a BS degree in Advanced Materials Science from Sungkyunkwan University in 2022. He is currently working toward an M.S. degree at the Department of Electrical and Computer Engineering at Sungkyunkwan University. His current research interests focus on DRAM cell transistors based on 2D vdW materials and oxide semiconductor materials.

Jiwon Moon

Jiwon Moon received a BS degree in Electronic Engineering from Kyunghee University, Seoul, South Korea, in 2018. She is currently working toward an Integrated MS and PhD degree at the Department of Electrical and Computer Engineering at Sungkyunkwan University. Her research focuses on next-generation devices utilizing 2D TMD semiconductors, 3D DRAM cell transistors, and their applications.

Hang-Gyo Jung

Hang-gyo Jung received his BS degree in Physics and MS degree in Electrical and Electronic Engineering from Konkuk University in Seoul, South Korea. Currently, he is pursuing his PhD at Sungkyunkwan University in Suwon, South Korea. His research interests lie in the simulation of next-generation semiconductor devices, compact modeling, and design-technology co-optimization (DTCO).

Jongwook Jeon

Jongwook Jeon received a BS degree in Electrical Engineering from Sungkyunkwan University, in 2004, and the PhD degree in Electrical Engineering from Seoul National University, Seoul, South Korea, in 2009. He was a Senior Engineer and a Principal Engineer with the Samsung Research and Development Center, South Korea, from 2009 to 2017. From 2017 to 2023, he was an assistant and associate professor at Konkuk University, Seoul, South Korea. Since 2023, he has been an associate professor in the Department of Electrical and Computer Engineering at Sungkyunkwan University, Suwon, South Korea, focusing on design-technology co-optimization (DTCO) for next-generation semiconductor technology.

Seong Hun Yoon

Seong Hun Yoon received a BS and MS degree from the Department of Electronic Engineering at Hanyang University, South Korea, in 2021 and 2023, respectively. He is currently working toward a PhD degree at the Department of Display Science and Engineering at Hanyang University. His research interests include semiconductor/insulating oxide materials and devices based on atomic layer deposition for emerging display/memory applications.

Jin-Hong Park

Jin-Hong Park holds the title of Distinguished Professor (SKKU Fellow) at Sungkyunkwan University (SKKU) in South Korea, where he is affiliated with the Department of Electrical and Computer Engineering, Department of Semiconductor Convergence Engineering, Sungkyunkwan Advanced Institute of Nanotechnology (SAINT). Prof. Park earned his MS and PhD degrees in electrical engineering from Stanford University in the United States in 2009. He furthered his academic and research career as a postdoctoral researcher at the IBM Thomas J. Watson Research Center from 2009 to 2010. Following his postdoctoral work, Prof. Park served as an Assistant Professor at Kyung Hee University from 2010 to 2011. He subsequently joined Sungkyunkwan University (SKKU) and has worked as an Assistant, Associate, and Full Professor. Prof. Park also contributes to the field of nanoscale research as an Editorial Board Member of Nanoscale Horizons, The Royal Society of Chemistry. His research interests primarily include developing advanced low-power devices utilizing 2D van der Waals (vdW) materials, such as gate-all-around FETs, multivalued logic devices, and neuromorphic devices. Additionally, he focuses on the fabrication technologies related to 2D vdW materials and oxide–semiconductor materials.

Jae Kyeong Jeong

Jae Kyeong Jeong received his BS, MS, and PhD degrees in Material Science and Engineering from Seoul National University, Seoul, Korea, in 1997, 1999, and 2002, respectively. In 2003, he served as a post-doctoral researcher at the University of Illinois at Urbana–Champaign in the United States. He then joined Samsung Display Corp. as a senior engineer in 2004, focusing on research related to the design and characterization of LTPS and IGZO TFTs for AMOLED display. Notably, as a project leader at Samsung Display, he led groundbreaking research in oxide TFTs, culminating in the unveiling of the world's largest 12.1′′ Oxide TFT-driven AMOLED display in 2008. In 2009, he transitioned to academia, joining Inha University at an assistant professor. Since 2015, he has served as a Professor in the Department of Electronic Engineering at Hanyang University, Seoul, Republic of Korea. His research has expanded to encompass novel devices such as oxide TFTs, flexible electronics, CMOS TFTs, and memory technologies. With over 198 SCI journal papers and 120 international patents, he holds an H-index of 63 and over 25 000 citations according to Google Scholar. He became a member of the National Academy of Engineering of Korea (NAEK) in 2021 and currently serves on the editorial boards of Scientific Reports. Throughout his career, Jeong has received numerous awards, including the Merck Grand Award (2023) and the Distinguished Paper Award from SID (2008).

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A. Introduction

In the era of big data, there has been a rapid increase in the volume of data handled by computers. The worldwide data generated in 2022 is projected to reach approximately 101 zettabytes, an annual growth rate of roughly 20%.¹ The processing bottlenecks arising from this substantial increase in data volume are a primary challenge, and it is crucial to enhance the performance of dynamic random access memory (DRAM), a key component serving as the primary memory in contemporary computers.

Enhancements in DRAM performance have been achieved through reductions in feature size and structural modifications. However, as feature sizes decreased beyond the 10 nm process node, leakage current has become the foremost challenge.² The reduction in gate length leads to increased gate-induced drain leakage (GIDL), junction leakage, and channel leakage current, making it difficult to meet the desired refresh time targets.³ Scaling cell geometry has also encountered limitations. The current mass production employs the 6F² architecture, while endeavors are underway to implement the 4F² architecture through the introduction of vertical channel array transistors (VCAT). The 4F² architecture, featuring one DRAM cell at each intersection of the word and bit lines, represents the most compact cell architecture achievable in a 2D structure. Scaling beyond 4F² requires breakthroughs. Currently, active research is addressing physical limitations and seeking to diminish feature size through the incorporation of alternative channel materials. These materials must exhibit immunity to the short-channel effect while experiencing minimal degradation in ultra-thin body structures. Notable candidates include OSs and TMDs.^4–7 The adoption of such materials facilitates the facile reduction of feature size, leading to significant improvements in DRAM performance, including operation speed and power consumption. In terms of cell geometry scaling, efforts are underway to introduce a vertically stacked DRAM, commonly referred to as “3D DRAM,” with a goal of higher integration compared to the 4F² cell architecture. Numerous structures have been proposed, inducing ongoing discussions regarding the most suitable configuration. The novel channel materials present a promising pathway for development of 3D DRAM. Silicon technology faces challenges in implementing ultra-thin body structures, scaling feature size, minimizing GIDL, and reducing processing temperature, making it difficult to realize stacked 3D DRAM with dozens of layers. Numerous research efforts are currently in progress to tackle these physical obstacles through the utilization of advanced channel materials. Representative examples include oxide semiconductors (OSs) and transition metal dichalcogenides (TMDs). Their inherent characteristics, facilitating reduced process temperatures, enhanced scalability, and decreased leakage currents compared to silicon, position them as prospective channel options for 3D DRAM cell transistors.^8,9

This review is organized as follows. In Part B, we provide a comprehensive overview of the evolution of DRAM cell structures. We compare the structures of 3D DRAM presented in patents and papers, along with their characteristics, from a process perspective. In Part C, we compare the features of OSs and TMDs from the perspective presented in Part B and discuss which materials may exhibit better performance when applied as channel material for the 3D DRAM cell array transistor. In Part D, we compare the critical issues that need addressing for the implementation of OSs and TMDs in 3D DRAM. We also review recent preliminary work related to OS-based DRAM cells.

B. Overview of DRAM cell structure

1. Evolution of DRAM cell structure

Transistors for 8F², 6F², and 4F² cells. In the initial phases of dynamic random-access memory (DRAM) development, a planar channel array transistor (PCAT) was employed, and the cell array adopted an 8F² geometry. However, the planar structure, susceptible to the short channel effect (SCE), encountered difficulties in scaling down. To address the SCE issues and to enable further scaling, a recess channel array transistor (RCAT) with a recessed channel was introduced, entering into the 88 nm node.¹⁰ After resolving the SCE, effort was made to decrease chip size by altering the cell architecture. Transitioning from the 8F² to a 6F²-based cell architecture posed challenges related to interconnect lines. Issues such as increased leakage current due to gate-induced drain leakage (GIDL) and higher parasitic capacitance between the word line and bit line were observed. The mentioned challenges were effectively addressed through the introduction of a buried channel array transistor (BCAT), facilitating the implementation of the 6F²-based cell architecture. This transition successfully led to a reduction in DRAM chip size.¹¹ Presently ongoing research aims to achieve a 4F²-based cell architecture, recognized as the most compact design within the realm of 2D cell array architecture.^2,12,13

Beyond 4F²:3D DRAM cell structure. Continued research has explored cell architectures with the potential to scale beyond the 4F²-based design. In this regard, vertically stacked DRAM, “3D DRAM,” has emerged as a promising candidate because the 4F²-based architecture represents the pinnacle of compactness in 2D cell design architecture. Several architectures for 3D DRAM cell transistors have been proposed. Samsung and Hynix suggested structures in which a horizontal capacitor is linked to gate-all-around and double gate transistors,^14,15 while Micron presented a structure where a vertical capacitor is connected to a channel-all-around transistor (Fig. 1a–c).¹⁶

Fig. 1 Schematic diagrams of 3D DRAM proposed by (a) Samsung, (b) Hynix, and (c) Micron.^14–16 Schematic diagrams of 3D DRAM with (d) vertical and (e) horizontal word lines.¹⁷

Compared to the horizontal capacitor, the vertical capacitor occupies a lower chip footprint (Fig. 1a). However, the process difficulty is high due to the formation of a high aspect ratio structure. The horizontal capacitor mitigates the process complexity, not requiring the formation of a vertical structure (Fig. 1b and c). However, enough layers should be stacked to compensate for the increased area of the larger chip footprint. To further increase integration density, the structure with the horizontal capacitor requires improvement in stacking technology, while the structure with the vertical capacitor requires enhancements in scaling techniques in the lateral direction. In cases where the horizontal capacitor and transistors are interconnected, two structures can be implemented depending on the orientation of the word line and bit line (Fig. 1d and e). In the scenario where the word line assumes a vertical orientation (as depicted in Fig. 1d), the lateral spacing between cells becomes wider, resulting in a larger footprint. However, this structure is predicted to have a lower height due to the reduced distance between layers. Conversely, when the word line takes a horizontal alignment (as depicted in Fig. 1e), the lateral spacing between cells decreases, reducing the overall cell area. However, this structure has a larger space between layers, resulting in a higher structure. Furthermore, the fabrication of horizontal word lines between cells adds complexity to the fabrication process flow.^17,18

Issues in utilizing new channel materials. The challenges arising from the reduction in feature size and the development of a 3D structure through stacking include the floating body effect, high leakage current, and high growth temperature.¹⁹ Efforts are underway to overcome these challenges, particularly in implementing 3D DRAM with channel materials other than silicon. When utilizing alternative semiconductor materials for the DRAM cell array transistor, the crucial parameters for assessing electrical performance are the on-current and off-current. The on-current directly influences the operational speed of DRAM, facilitating faster capacitor charging to reduce the width of the write pulse. On the other hand, the off-current, representing the leakage current of the cell array transistor, is linked to the power consumption of DRAM. A high off-current results in the leakage of charge from the capacitor even when the word line is inactive. To prevent complete loss of charge, periodic refresh operations become necessary. A higher off-current necessitates more frequent refresh operations, contributing significantly to DRAM power consumption. Extending the refresh period significantly reduces overall DRAM power consumption.

Furthermore, the deposition method and process temperature become crucial considerations when incorporating new channel semiconductor materials for the 3D DRAM cell array transistor. Physical vapor deposition (PVD) methods like sputtering exhibit inadequate step coverage and low uniformity, rendering them unsuitable for the 3D DRAM process. On the other hand, chemical vapor deposition (CVD) methods offer superior step coverage compared to PVD. However, achieving a high-quality thin film requires high temperatures in CVD, presenting a challenge in monolithic process integration schemes. The high process temperatures can lead to thermal budget issues, causing variations in the characteristics of upper and lower devices. Atomic layer deposition (ALD) stands out among CVD techniques due to its exceptional step coverage and uniformity, allowing the deposition of extremely thin and high-quality film. Nonetheless, the drawback of ALD is the necessity for the development of precursors tailored to the target materials.

Recently, OSs such as IGZO and TMDs like MoS₂ have been proposed as next-generation semiconductor channel materials. OSs exhibit low off-current characteristics and are easy to mass-produce, allowing wide use in the display field. TMDs, with a thickness of sub-1 nm and high mobility characteristics, are also considered promising materials for next-generation semiconductor channel materials. In part C, we will compare the features of OSs and TMDs from the perspective presented in part B and discuss the performances predicted when they are applied to 3D DRAM cell array transistors.

C. Emerging channel materials and their device characteristics

1. Oxide semiconductors and TMD semiconductors

Oxide semiconductors. OSs including amorphous indium–gallium–zinc oxide (a-IGZO) have seen increased application since their debut in active matrix organic light-emitting diode (AMOLED) televisions as backplane electronics by LG Display in 2013.^12,20 This successful implementation into a commercial product is attributed to their intriguing features such as reasonable high mobility in comparison to amorphous Si (a-Si), extremely low off-current, high transparency, and excellent uniformity. The electrical and physical properties of OSs exhibit significant dependence on the composition ratio of metal cations and oxygen. Unlike Si semiconductors, the OS system allows effective control of carrier concentration and electron effective mass without heavy reliance on doping processes. Researchers have explored diverse compositional tuning to extend the application of OSs beyond a-IGZO, aiming to maximize mobility and to improve reliability.^21,22 Beyond IGZO, a variety of OSs with different combinations, including binary oxides (In₂O₃, ZnO),^23,24 ternary oxides (IGO, IZO),^25–27 and further combinations like IZTO²⁸ and IGZTO,²⁹ has been researched. It is noteworthy that the majority of research and development in the field of OS thin-film transistors (TFTs) has been directed towards their application in flat-panel displays, where the physical channel length tends to be longer, exceeding 1 μm. In contrast, the use of scaled high-performance transistors at nm-scale for memory chips faces challenges such as sufficient drive current and mitigation of SCEs.

TMD semiconductors. Research on two-dimensional materials started with the successful exfoliation of graphene using tape in 2008.³⁰ TMDs are actively studied as promising next-generation semiconductor materials due to their excellent electrical properties. TMDs are compounds with the chemical formula MX₂, consisting of one transition metal atom bonded to two chalcogen atoms. Various TMDs can be formed by combining different transition metal and chalcogen atoms. WSe₂, MoS₂, and WS₂ are the most extensively studied due to their superior stability and electrical properties.³¹ TMDs have various lattice structures and are thermally stable when adopting the 1T and 2H structures. The 1T structure exhibits metallic properties, and the 2H structure shows semiconductor properties.³² The constituent atoms of TMDs form a hexagonal structure through strong covalent bonding within the same layer. However, each layer is interconnected by weak van der Waals bonds, resulting in a layered structure. Due to this unique structure, TMDs theoretically have no dangling bonds and exhibit excellent electrical properties even at sub-nanometer thickness, demonstrating strong immunity against the short channel effects.³³ Thus, TMDs are promising candidates for next-generation channel materials.

2. Transistor on/off characteristics

(1) Achieving high ON-current (Table 1). As mentioned, advancements in the design of the access transistor in DRAM focus on minimizing off-current, increasing V_TH, and achieving a low subthreshold slope (SS). OSs, celebrated for their favourable attributes such as low off-current and SS values even in small and slim configurations, exhibit promising potential. However, the enhancement of on-current and precise control of V_TH continue to be critical challenges. To position OSs as the channel layer in the access transistor of 3D DRAM cells, it is essential to guarantee the necessary on-current for operational efficiency. This necessity stems from the comparatively lower mobility of OSs compared to crystalline silicon or TMD. Ongoing efforts to address this limitation involve the composition^34,35 and non-stoichiometry fine-tuning^25,28,36 and thickness scaling,^37,38 as evidenced by the average values presented in the referenced studies (see Table 1). Among various approaches, indium-rich substances such as In₂O₃ or Sn-doped indium oxide (ITO) emerged as frontrunners in enhancing the on-current of OS FETs, ensuring 20 mA μm⁻¹ in a GAA-structured In₂O₃ nano-ribbon transistor.³⁹ This impressive feat underscores the potential of indium-rich oxides wherein the ultra-high physical thickness is a key factor to maintain the superior on/off characteristics (Fig. 2a and b).^23,38 However, challenges persist due to the critical trade-off of negative-shifted V_TH at these highly degenerated OSs, particularly the formidable hurdle of mitigating the degradation of PBTS/NBTS reliability. Gate efficiency of OSs FETs can be improved through high-κ materials, yielding devices that manifest outstanding SS characteristics approaching ∼60 mV per decade.^40–42 This noteworthy achievement underscores the potential to obtain superior interface characteristics both in a conventional planar structure and in the realm of 3D integrated devices, all of which were achieved without substantial compromise or degradation.^27,39

Table 1 Physical and electrical properties affecting transistor ON characteristics

Property		Channel materials
		c-Si	2D TMDs	Oxide semiconductors
Contact related	Contact resistance	20–50 Ω μm	>1000 Ω μm	500–2000 Ω μm
	Barrier height (EF pinning)	∼500 meV	∼200 meV	300–1000 meV (SBH)
	Doping concentration	10^21–10^22 cm^−3	10^12–10^13 cm^−2 (10^19–10^20 cm^−3 at d = 100 nm)	10^16–10^18 cm^−3
	M–S gap	Negligible	0.3–0.5 nm	Negligible
Channel conductivity	Effective DOS	3 × 10^19 cm^−3	∼10^22 cm^−3	5 × 10^18 cm^−3
	Mobility	∼125 cm^2 V^−1 s^−1	20–50 cm^2 V^−1 s^−1	20–100 cm^2 V^−1 s^−1
	D it (with high-κ)	∼10^10 cm^−2 eV^−1	∼10^13 cm^−2 eV^−1	∼10^12 cm^−2 eV^−1

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Table 2 Physical and electrical properties affecting transistor OFF characteristics

Property		Channel materials
		c-Si	2D TMDs	Oxide semiconductors
GIDL	Bandgap	1.12 eV	1.6 eV	>3.0 eV
	D it (with high-κ)	∼10^10 cm^−2 eV^−1	∼10^13 cm^−2 eV^−1	∼10^12 cm^−2 eV^−1
Subthreshold leakage
	Thickness	∼6 nm	<1 nm	10–50 nm
Junction leakage	Barrier height	PN junction (Eg – 500–1000) meV	Schottky junction (Eg – 1400) meV	Schottky junction (Eg – 300–1000) meV

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Fig. 2 (a) DFT-calculated band structure at In₂O₃ film thicknesses of 0.7, 1.0, 1.2, and 1.5 nm and bulk along the Γ to X-direction, the red and black lines indicate the bands from In₂O₃ and Al₂O₃, respectively.³⁸ (b) I_D–V_GS characteristics of In₂O₃ transistors with channel thickness of 0.7 nm.³⁸ (c) I_DS–V_GS curves and extracted g_m–V_GS curves for a-IGZO TFTs with and without an ITO interlayer between M/S contact and (d) schematic band diagrams of SBH lowering with ITO interlayer.⁴⁴ (e) Carrier injection characteristics in degenerately doped semiconductors and TMDs.⁵³ (f) Band diagram of the metal–TMD interface with a van der Waals gap.⁵⁵ (g) D_it distribution-extracted technology computer-aided design (TCAD) simulation at the MoS₂–insulator interface.⁵⁸ (h) Transfer characteristics as a function of D_it.⁵⁹

Nevertheless, most OS FETs exhibit contact-limited behavior attributed to a notably high specific contact resistivity. Evidently, the diminishing contact area within nanoscale DRAM cells imposes a substantial constraint on the on-current, a phenomenon underscored in literature.⁴³ In display backplane technologies where contact areas typically span a few μm², the manageable nature of metal–OS contact resistance prevails even at levels of ∼10⁴ Ω μm. However, within the intricate structure of DRAM cell transistors, the negative impact of contact resistance will be amplified, particularly in the context of 3D DRAM technology where contact areas may decrease to the ∼100 nm² scale. Approaches to reduce contact resistance in OS FETs involve the insertion of suitable interlayers (ILs) or/and the formation of highly-doped n⁺ layers.^44–46 Li et al. inserted ITO IL between IGZO and Ni contacts to achieve substantial enhancement of on-current (1207 μA μm⁻¹) due to a reduction in contact resistance to 278 Ω μm (at 4.3 K) (Fig. 2c and d).⁴⁴

Several reports have demonstrated TMD-based FETs in achieving on-currents surpassing 450 μA μm⁻¹, due to their inherently excellent conductivity characteristics. These values align closely with the specifications outlined in the International Roadmap for Devices and Systems (IRDS) 2022.^47–49 Consequently, TMDs can be utilized for DRAM cell transistors with exceptionally rapid write speeds or for peripheral transistors requiring specifications comparable to high-performance logic devices. Simulation-based studies on TMD FETs suggest that they have the potential to outperform silicon-based MOSFETs in terms of on-current, provided certain challenges are addressed.^50,51 One such challenge is the high contact resistance; typical metal-TMD junctions exhibit contact resistance in the kiloohm range, which is several times higher than that of silicon–metal junctions. Although the metal-TMD Schottky barrier height is approximately 200 meV in the case of MoS₂, a representative n-channel TMD material, this junction is expected to have a lower carrier injection rate than silicon–metal junctions due to the absence of an established degenerate doping technique (Fig. 2e).^52,53 Moreover, there is a gap of approximately 0.3–0.5 nm at the metal–TMD interface, serving as an additional tunnelling barrier that impedes carrier injection (see Fig. 2f).^54,55 This combination of low doping level and an interface gap contributes to the high contact resistance observed in TMD–metal junctions, prompting ongoing research efforts to address these challenges. Notably, Li et al. achieved a substantial reduction in contact resistance to 42 Ω μm by employing a semimetal as the contact for MoS₂, resulting in an impressive on-current of 1400 μA μm⁻¹.⁵⁶ Their study highlights the potential for significantly enhancing the on-current characteristics of TMD FETs through effective mitigation of contact resistance.

When considering parameters related to channel conductivity, TMDs exhibit higher DOS, lower interface trap density (D_it), and lower mobility compared to silicon. Despite a theoretical mobility of 410 cm² V⁻¹ s⁻¹, the experimentally measured mobility in TMDs is notably low, ranging from 20 to 50 cm² V⁻¹ s⁻¹. This discrepancy is attributed to the immature growth technology of TMDs and interface defects with the gate insulator.^55,57 While TMDs ideally lack dangling bonds, the reality presents a high D_it in the range of 10¹²–10¹³ cm⁻³ when interfaced with high-κ materials (refer to Fig. 2g).⁵⁸ This leads to an increase in SS, a reduction in mobility, and, consequently, a decrease in on-current (as shown in Fig. 2h).⁵⁹ TMDs show inferior characteristics in comparison to silicon, which boasts a mobility of approximately 125 cm² V⁻¹ s⁻¹ and a D_it of 10¹⁰ cm⁻³. Therefore, advancing channel growth technology and developing techniques to minimize defects between the channel and gate insulator are crucial. In summary, TMDs exhibit conductivity that meets the on-current requirements outlined in IRDS 2022 for DRAM, despite facing challenges such as high contact resistance and low mobility in current TMD technology. There exists substantial potential for improvement through advancements in technology.

(2) Minimizing OFF-current (Table 2). In the pursuit of achieving low OFF-current, OSs exhibit superior characteristics to other channel materials, including silicon (Fig. 3a–c).^60–64 The exceptionally low OFF characteristics of OSs pose measurement challenges, primarily due to the conventional instrumental detection limit (approximately 10⁻¹⁴ A). The exceptionally low OFF current (<10⁻¹⁸ A μm⁻¹) in OSs comes from their notably wide bandgap and negligible hole density. The wide bandgap in OSs increases the energy barrier for carrier injection from the S/D under a negative gate bias, effectively minimizing the formation of electron/hole pairs in the channel bulk, leading to an extremely low off-current. Additionally, the generation of holes is impeded by the suppression of downward band bending during reverse gate bias, facilitated by the presence of substantial gap states between the mid-gap and VB edge. These features enable OSs to maintain an ultra-low off-current even when the channel thickness is scaled down to the order of several nanometers, distinguishing them from other materials in terms of device design rules. Despite their advantageous OFF characteristics for n-type access transistors, intrinsic challenges arise from the substantial hole effective mass, posing a formidable hurdle in achieving essential p-type characteristics crucial for complementary metal–oxide–semiconductor (CMOS) device fabrication. This inherent limitation stands as a persistent drawback, representing a longstanding issue in the domain of OS technology.¹²

Fig. 3 Temperature dependent transfer characteristics of (a) Si and (b) CAAC-IGZO FETs.⁶⁴ The off-currents of the OS FETs were below the measurement limit regardless of the temperature. (c) Transfer characteristics of OS TFTs with ultralow off-current (measured by circuit voltage drop).⁶⁰ (d) Band diagram illustrations of on and off states in TMD FETs. Leakage current occurs in the off state. (e) Transfer characteristics of TMD FETs with different SBH. Ambipolarity-induced leakage current is significantly higher than GIDL.⁶⁵

In comparison to silicon and OSs, TMDs demonstrate higher off-current characteristics, primarily due to the inherent ambipolar behavior exhibited by TMDs. In the context of n-channel TMD FETs, the application of a negative gate voltage elevates the SBH for electrons, reducing their injection and aiding in turn-off. However, this configuration leads to a decrease in the Schottky barrier width for holes, increasing the tunnelling probability of holes and resulting in high off-current (refer to Fig. 3d). Ambipolar behavior-induced leakage is also observed in p-channel TMD FETs. In contrast, silicon-based FETs, which operate with PN junctions and are unipolar, and OS FETs, characterized by a larger bandgap and lower hole concentration, do not exhibit ambipolarity. As a result, they show lower off-current compared to TMD FETs.⁸ The investigation of leakage currents, such as GIDL, subthreshold leakage, and junction leakage, has been limited in TMD FETs due to the challenges posed by ambipolarity (as shown in Fig. 3e). Nevertheless, GIDL and junction leakage in TMD FETs are expected to be relatively low considering the larger bandgap of TMDs compared to silicon. Conversely, subthreshold leakage is anticipated to be high due to the elevated D_it.^65,66 Consequently, research efforts aimed at mitigating ambipolarity should be given priority.

3. Issues to overcome

(1) Control of V_TH in OS FETs. Managing the trade-off between on-current and V_TH in OS FETs represents a critical challenge. The introduction of a high indium fraction in OSs leads to increased mobility, facilitated by the efficient formation of a percolation pathway in CB. However, this also produces oxygen vacancies (V_O) due to weak chemical bonds between indium and oxygen. As some of V_O acts as a shallow donor, it results in the negative displacement (so-called depletion mode) in the resulting FETs (Fig. 4a).^25,27 To address this issue for nanoscale OS FETs, novel processes such as work function engineering, implementation of a smart OS/gate dielectric stack, and design of a 3D device architecture should be explored.

Fig. 4 (a) Comparison of IGO FETs depending on the In–Ga composition ratio.²⁷ (b) PBTS comparison of device A (single HfO₂ layer as gate insulator) and device B (SiO₂/HfO₂ multilayer as a gate insulator including O₂ annealing). (c) Possible mechanism of stability degradation for device A (singe HfO₂ layer as gate insulator).⁴¹ (d) Grain boundaries and (e) wrinkles formed during TMD growth.^68,69 (f) Atomic force microscopy (AFM) topography images and height profiles of Al₂O₃ grown on MoS₂ and (g) surface coverage.⁷⁰

(2) Reliability of OS FETs. PBTI and NBTI of OS FETs have shown consistent improvement driven by a fundamental understanding of defects, particularly in the context of display applications.¹² However, in the realm of 3D DRAM applications, the unavoidable significant hydrogen incorporation in the OS channel can lead to unacceptable V_TH instability under the elevated temperature and thermal-bias condition (Fig. 4b and c).⁴¹ Identifying the role of double-face hydrogen-related defects in nanoscale OS FETs with a hydrogen-rich environment requires further theoretical and experimental studies. If hydrogen bi-stability proves to be a fundamental limitation in the amorphous OS substance, investigating the crystalline OS channel approach becomes imperative considering potential non-uniformity penalties related to grain boundary defects.

(3) Large scale growth of single-crystalline TMDs. Achieving the growth of single-crystalline TMDs on silicon substrates at the wafer scale remains a challenging task. The precise control of crystal size, orientation, and layer number during TMD growth poses difficulties, leading to the emergence of numerous defects and grain boundaries, as illustrated in Fig. 4d.⁶⁷ Specifically, grain boundaries have the potential to serve as paths for leakage current, posing a critical threat to DRAM cell transistors. Furthermore, during subsequent processes, peeling or wrinkling may occur due to the thermal expansion coefficient mismatch between the substrate and TMDs, as depicted in Fig. 4e.⁶⁸ Such issues can lead to degradation of device performance and an increase in device-to-device performance variability.

(4) Deposition of high-κ materials on TMDs using ALD. The capability to achieve uniform growth of high-κ materials through ALD is crucial for incorporating TMDs into 3D DRAM. Unlike conventional 3D semiconductor materials, TMDs pose a challenge in chemisorbing precursors due to the lack of dangling bonds. As a result, high-κ dielectrics exhibit island growth starting from the edges or defect sites of the TMDs, leading to the formation of non-uniform and defect-rich films, as illustrated in Fig. 4f and g.^70,71 Defects in TMD films can serve as leakage paths and contribute significantly to device variation. Consequently, the development of a technology that enables the uniform growth of high-quality high-κ materials on TMDs is essential for the successful implementation of TMD-based 3D DRAM.

D. Application to DRAM

As elucidated in the previous section, a discernible trend is emerging in the assessment of OS-based DRAM characteristics, driven by the excellent step-coverage capabilities of ALD processes and the ultra-low off-current exhibited by OSs. A recent contribution by Belmonte et al. exemplifies this trajectory, where the implementation of a 2T0C DRAM cell achieved an extraordinary diminutive off-current of <3 × 10⁻²¹ A μm⁻¹ and a long retention time of >4.5 hours through meticulous process optimization of OS FETs.⁷² Furthermore, Chen et al. made noteworthy strides by introducing a 2T0C cell transistor based on a vertically stacked CAA FET structure, featuring a 4F² feature size and endurance characteristics exceeding >10¹² cycles due to the exceptionally low off-currents of the OS FETs.⁷³ These findings underscore the potential of OS FET technology in next-generation DRAM, showing superior power efficiency and performance compared to traditional Si-based technologies. This paradigm shift is poised to exert a profound influence on the trajectory of future research and development endeavors in the 3D DRAM.

E. Perspectives

While certain challenges remain, the potential applications of OS and TMD channels extend beyond DRAM. The application of OSs extends beyond volatile memory to include frequent proposals for next-generation memories such as FeFET.^74,75 This is attributed to the OS's low off-current and the potential improvement in interface characteristics compared to silicon-based ferroelectrics. However, even in the application of components beyond DRAM, contact-limited behavior of OSs mentioned in part C and the need for improvement in hydrogen immunity continue to act as bottlenecks that require further enhancement. Despite the development of various memory devices using TMDs, their specific application in DRAM remains limited.^76–78 Also discussed in Part C, significant efforts are required to utilize TMDs as channel materials in DRAM cell transistors. These efforts should primarily concentrate on reducing interface and bulk trap density while mitigating ambipolarity-induced leakage current to minimize off-current and enhance SS.

F. Conclusion

We discussed the structures proposed for 3D DRAM architectures to date, the applicability of TMDs and OSs to 3D DRAM, and research on 3D DRAM with such materials, especially OSs. Samsung and Hynix proposed structures in which a horizontal capacitor is connected to a GAA FET and a double gate FET, respectively. Micron, on the other hand, presented a structure where a vertical capacitor is connected to a CAA FET. Ongoing research efforts aim to incorporate OSs and TMDs, next-generation semiconductor materials, into these 3D cell transistors. We explored the feasibility of applying OSs and TMDs in 3D DRAM through a comparative analysis of their properties. OSs are celebrated for their ultra-low off-current and low SS characteristics, as evidenced by recent achievements of OS-based DRAM. Nevertheless, there remains ample room for additional research, particularly in areas such as enhancing mobility, reducing electrical contact resistivity, and improving H-related thermal bias instabilities. TMDs exhibit outstanding conductivity characteristics, leading to a high on-current. However, ambipolarity-induced leakage current occurs in the off-state, resulting in elevated off-current characteristics. Therefore, further research is essential to address the leakage current associated with ambipolarity.

Conflicts of interest

The authors declare no conflicts of interests.

Acknowledgements

This research was supported by the National Research Foundation of Korea (NRF) (2022M3F3A2A01072215, 2021R1A2C2010026, and RS-2023-00235609). This work was also supported by the Institute of Information & communications Technology Planning & Evaluation (IITP) under the Artificial Intelligence Semiconductor Support Program to Nurture the Best Talents (IITP-2024-RS-2023-00253914) grant funded by the Korean government.

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Footnote

† These authors contributed equally to the paper.

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