Ji-Hoon
Kang‡
,
Junghee
Ryu
and
Hoon
Ryu‡
*
Division of National Supercomputing, Korea Institute of Science and Technology Information, Daejeon 34141, Republic of Korea. E-mail: elec1020@kisti.re.kr; Tel: +82 42 869 0610
First published on 27th November 2020
Charge stabilities and spin-based quantum bit (qubit) operations in Si double quantum dot (DQD) systems, whose confinement potentials are controlled with multiple gate electrodes, are theoretically studied with a multi-scale modeling approach that combines electronic structure simulations and the Thomas–Fermi method. Taking Si/SiGe heterostructures as the target of modeling, this work presents an in-depth discussion on the designs of electron reservoirs, electrostatic controls of quantum dot (QD) shapes and their corresponding charge confinements, and spin qubit manipulations. The effects of unintentional inaccuracies in DC control biases and geometric symmetries on the Rabi cycle of spin qubits are investigated to examine the robustness of logic operations. Solid connections to the latest experimental results are also established to validate the simulation method. As a rare modeling study that explores the full-stack functionality of Si DQD structures as quantum logic gate devices, this work delivers the knowledge of engineering details that are not uncovered by the latest experimental work and can serve as a basic but practical guideline for potential device designs.
Though qubits can be encoded using charges that are confined in Si nanostructures,5,19,20 due to the above-mentioned reasons, spin-based qubit encoding has been actively studied during the last decade,3,4,6–10 and electron spin qubits in Si QD structures are known to be able to retain their quantum states ∼103 times longer than other competing technologies such as superconducting qubits.21,22 Based upon the seminal work of Loss and DiVincenzo who conceptually proposed the designs of logic gate devices with electron spins in double quantum dot (DQD) systems,23 experimentalists have devoted huge efforts to investigating Si-based DQD systems. A successful coherent control of electron spins in Si DQDs was demonstrated by Maune et al.3 Veldhorst et al. then reported the individual addressability of multiple spin qubits6 and realized controlled-NOT (CNOT) gates by combining controlled-phase operations and 1-qubit operations.7 Zajac et al. reported ∼3× faster CNOT gates involving a single control step,8 and, most recently, Watson et al. demonstrated the successful implementation of a programmable 2-qubit quantum processor using the Si DQD platform, which has the capability to solve the Deutsch–Jozsa and Grover algorithms.9
Despite all the above-mentioned experimental efforts, there are still issues that should be examined for a better understanding of Si DQD quantum gates from the perspective of device design. The two issues that need urgent clarification, in particular, can be (1) the robustness of gate designs against any unintentional inaccuracy in design factors (unintentional inaccuracy would essentially occur in the real world scenario) and (2) the margin of control signals in which the stability of quantum logic operations can be guaranteed. An elaborate study of these issues needs to be pursued with computer-aided simulations since the experimental investigations of all the design variations would involve huge time and expense, and is non-trivial since it not only presents a formalized design guideline but can also invoke potential efforts to evolve the existing device designs towards advanced regimes. Accordingly, herein we propose a multi-scale scheme of device simulations that combines a semi-classical Thomas–Fermi model24 and electronic structure calculations based on a parabolic effective mass theory.25 Taking a recently reported Si DQD structure as a modeling target,8 we discuss the designs of a low-temperature 2D electron gas (2DEG) that is essential to secure DQD-embedded ohmic contacts. The full charge stability diagram is then modeled to explore the controllability of the DC biases applied on the three key gate electrodes, and the range of the control biases applicable for qubit initialization is investigated. By taking the control biases and the dimensions of the gate electrodes as factors subject to unintentional inaccuracy, the robustness of logic operations is also discussed by simulating 2-qubit time responses under a weak correlation. As a full-stack modeling study digging out engineering details that have not been clarified in previous studies, this work will contribute to extending the knowledge on the designs of Si quantum logic gates based on electrode-driven DQDs structures.
Fig. 1 Simulation domain and modeling approach. (a) A conceptual 2D description of the Si double quantum dot (DQD) structure reported in ref. 8. QDs are created in the middle Si layer by controlling the left (VL), middle (VM), and right (VR) gate bias, where the barrier gate bias (VB) is used to separate the QDs and 2D electron gases (2DEG). (b) A 2D simulation domain. The 2DEG regions are considered with a Dirichlet boundary condition coupled to the zero Schottky barrier height. A spatial distribution of the magnetic field along the [001] (Z) direction is taken from the stray field profile simulated for a cobalt micro-magnet in ref. 26. (c) A numerical flow of simulations. Given a potential profile, a charge profile is obtained in two ways: electronic structure calculations with a parabolic effective mass model (applied to the middle Si layer labeled as the quantum region in (a)) and Thomas–Fermi calculations (the other region labeled as the classical region in (a)). With a charge profile, a nonlinear Poisson equation is solved to achieve a new potential profile. These processes is repeated until the potential profile converges. |
For the self-consistent determination of the electrostatic profiles in the target DQD structure, we implemented a hybrid modeling approach using the numerical flow shown in Fig. 1(c). Given an initial potential profile, a spatial charge distribution is calculated using either a simple semi-classical Thomas–Fermi (TF) method24 or electronic structure simulations coupled with a single-band effective mass approach (EMA).25 The methodological choice for the charge calculations depends on the region of interest in the simulation domain. For a region that can be assumed to have no charges at very low temperatures (labeled as the Classical Region in Fig. 1(b)), the TF method is employed since there are no critical needs for quantum mechanical solutions that require a huge computing expense. In the middle Si layer and its surrounding region where the confined electrons are expected to reside (labeled as the Quantum Region in Fig. 1(b)), however, an EMA-based Schröedinger equation is solved for the precise prediction of quantized energy levels and spatial distributions of electron wavefunctions (note that the ESI† presents a more detailed explanation about how the EMA is used to model the electron spin-states in this work). Once the charge profile is determined, we solve a nonlinear 2D Poisson equation (with boundary conditions addressed in the previous paragraph)29 to obtain a new potential profile that will be again be used to obtain a new charge distribution unless the potential profile satisfies a user-defined convergence criterion (a mean square error less than 10−10 eV in our case). For all the modeling works, we assume a temperature (T) of 1.5 K.
Being injected from 2DEGs under a small electric field imposed along the [100] direction, the electrons could be confined in the channel with appropriate biases of the barrier (VB), left (VL), middle (VM) and right (VR) gate electrodes (Fig. 1(b)). To examine the contribution of these electrodes to electron confinement, we modeled a full charge stability diagram taking VL and VR as control factors, and the details of conductance calculations are available in the ESI.†Fig. 3(a) shows the result obtained at VM = 400 mV and VB = 200 mV, and the shape of the diagram is quite similar to that of the diagram measured for the reported physical DQD structure.8 Being identified with two numbers that show the number of electrons in the left/right QD, the charge states, for the convenience of discussion, are represented with points labeled as P00, P01, P10, and P11. The two control paths for channel initialization to the (1,1) state, which is the starting step of qubit logic operations, are described with white arrows, e.g., P00 → P01 → P11 or P00 → P10 → P11. In the P00 → P01 → P11 path, for example, the state is transferred from (0,0) to (0,1) at VR = 545 mV and VL = 535 mV (indicated with a red arrow), where the ground state energy-level of the right QD touches the EF value that is fixed by the 2DEG reservoirs. The state-transfer from (0,1) to (1,1) then occurs at VR = 555 mV and VL = 546 mV (indicated with a yellow arrow).
Fig. 3 Charge control and qubit initialization. (a) A full charge stability diagram simulated for the target structure at VM = 400 mV and VB = 200 mV. Being in excellent agreement with the diagram measured for the reported device,8 the result shows the four representative charge states (P00, P01, P10, and P11) with two control paths (white arrows) that can be used to initialize the double quantum dot (DQD) system for gate operations. (b) Conduction band minimum (EC) profile at each charge state. Once the channel is initialized to the (1,1) state, the energy valleys are vanished due to the screening effects of the electrons in QDs. (c) Feasibility of the channel initialization represented as a function of (VM, VL = VR). The two biasing points (P00 and P11 state) are included as examples for the clear description of the bias regime where the DQD channel can (white) or cannot be initialized (black). |
The electrostatic phenomena at the four charge states are shown in Fig. 3(b), where we present the spatial distribution of EC in the middle Si layer at each charge state with its 1D profile cut along the white dotted line marked in the 2D profile. When the system is at an empty state (P00 at VL = VR = 535 mV), the EC profile has a smooth double-well shape, as VL and VR are higher than VM(= 400 mV). Increasing VL(VR) continuously lowers EC around the left(right) QD when the channel is empty. Once the left(right) QD is filled with an electron (P10(P01) at VL = 555(535) mV and VR = 535(555) mV), however, the channel EC moves up due to the screening effect. When both QDs are filled with an electron (P11 at VL = VR = 555 mV), the EC profile of the middle Si layer no longer shows energy valleys, indicating that the channel has no chances to grab more electrons, which even though can be still injected from 2DEGs. As the stability diagram shown in Fig. 3(a) cannot explain the VM-driven charge control, we provide another diagram in Fig. 3(c), which shows the feasibility of channel initialization as a function of (VM, VL = VR). The two points, which correspond to the P00 and P11 states in Fig. 3(a), are marked as examples to help easy recognition of the bias regime where the channel can (white) or cannot (black) be initialized.
The main role of the middle gate bias VM is to control the barrier height between the two QDs, and the barrier height affects the exchange interaction of the two spin states that are occupied by confined electrons. Representing the coupling strength between the ground down-spin states, the exchange constant (J) acts as a control factor for the generation of quantum entanglement between two spin qubits in a DQD structure. The behavior of J under varying biases thus must be precisely understood. Fig. 4(a) shows the 1D profiles of EC (cut along the white dotted line marked in Fig. 3(b)) simulated at VL = VR = 535 mV and VM = 390–410 mV, where the barrier height is also plotted as a function of VM in the inset figure. Although VL and VR are fixed, increasing VM causes an overall reduction of EC in the middle Si layer. The reduction however is highest near the region below the middle gate; therefore, the barrier height between the two QDs reduces, and the modeling result indicates that the barrier height varies almost linearly and is inversely proportional to VM. As shown in Fig. 4(b), where the charge density profile at the (1,1) state (at VL = VR = 555 mV) is plotted for two different values of VM (400 mV and 405 mV), the reduced barrier height also affects the confinement shape such that the two electrons in the left and right QDs become closer. While VM exerts non-trivial effects on the barrier height (and coupling) between the two spin states, a noticeable change in the Zeeman splitting energy of each state, a critical factor that determines the frequency at which each electron spin resonates, is not observed. The results in Fig. 4(c) show that the Zeeman splitting energy of the ground state in each QD (EZR and EZL) fluctuates within 0.1% of its average in the range of VM, indicating that the resonance frequencies of the two spin states and their coupling strengths can be controlled independently. The sensitivity of J to VM, calculated from the electron distribution in each QD, turns out to be quite high, and hence J increases by ∼30 times with a ΔVM of just 5 mV (Fig. 4(d)) (for those who are interested, we have presented the numerical values of ΔEZR, ΔEZL and ΔJ per unit mV of ΔVM in Table S1 of the ESI†).
Once EZR, EZL and J at the (1,1) state are known with device simulations as discussed so far, the time responses of the electron spin qubits in the DQD system can be predicted by solving a time-dependent Schrödinger equation that is established with the Heisenberg Hamiltonian of two neighboring spins.28 Here, we chose the real-time 1-qubit NOT logic operation as a modeling target, and to control the electron spin resonance (ESR) in the QDs, a dynamic magnetic field BY, whose amplitude and frequency were user-defined factors, was assumed to be applied along the [010] direction. As addressed, the starting step of the qubit logic operations was the initialization of the DQD system, following which the ground down-spin state of each QD (|↓〉L and |↓〉R) was filled with a single electron. For this purpose, the system was simulated at VL = VR = 555 mV. VM was set to 400 mV to lead both QDs to perform independent 1-qubit operations with a weak correlation. In a 2-qubit frame, this initial state was represented with |↓↓〉 = |↓〉L ⊗ |↓〉R, where the symbol ‘⊗’ indicates a tensor-product operation. Fig. 5(a) and (b) show the corresponding 2-qubit time responses when the drive frequency of BY is set equal to the Zeeman splitting energies EZL (8.045 GHz) and EZR (8.134 GHz), respectively. When the frequency is 8.045 GHz, ESR occurs only in the left QD, and the spin qubit in the right QD remains unchanged from its initial down-spin state. Among the time responses of the four 2-qubit states in Fig. 5(a), therefore, only the two cases (|↑↓〉 and |↓↓〉), where the right qubit is |↓〉, show a Rabi oscillation. Likewise, at a frequency of 8.134 GHz that drives ESR only in the right QD, the oscillation was observed only in the time response of |↓↑〉 and |↓↓〉, as shown in Fig. 5(b). In both cases, a NOT logic operation was achieved when the probability of a specific output satisfied a certain condition. If ESR occurs only in the left QD (Fig. 5(a)), for example, a NOT logic operation can be achieved at all the time spots where P(|↑↓〉) (the probability that a |↑↓〉 state is measured) becomes 1.
Though we chose a bias point of VL = VR = 555 mV and VM = 400 mV to initialize the DQD channel, other (VL, VR) biases at VM = 400 mV, in principle, must be also available for the same purpose as long as they belong to the top-right regime in the stability diagram (Fig. 3(a)). However, if these DC bias points and the resulting ESR frequencies of the QDs are strongly correlated, the complexity in controlling the logic operations would increase. A modeling result of the corresponding correlation is shown in Fig. 5(c), where we plotted the relative variation of the drive frequency in the left QD as a function of (VL, VR). The frequency driven at VL = VR = 555 mV and VM = 400 mV is taken as a reference. With ΔVL and ΔVR at ≤5 mV, the maximum deviation of the frequency turns out to be under 0.02% of its reference value, and this deviation is more sensitive to ΔVL than ΔVR since the confinement of the left QD is affected more strongly by the left gate electrode than the right one (detailed dataset for the variation of ESR frequencies per unit mV of ΔVL and ΔVR is available with the corresponding valley-splitting energies in Tables S2 and S3 of the ESI†). The time responses of a |↑↓〉 state with ΔVL of ±5 mV are plotted in Fig. 5(d). Even though the frequency deviation driven by ΔVL is extremely small, the resulting phase-shift keeps being accumulated, and remarkable changes may be driven in the response as time elapses. However, up to ∼500 ns, the change in P(|↑↓〉) measured does not become noticeable (≪1%). The robustness of the logic operations against the unintentional inaccuracy in VL can be also explained with the modeling results. Assuming that the input bias has an uncertainty of ∼1 mV under the experimental conditions, we observed that the fidelity of the first NOT operation (at 34.5 ns) dropped by less than 0.2%. The fidelity is also depicted as a function of the unexpected deviation of J (dJ) in Fig. 5(e), which shows a fidelity of 99.96% even at dJ of 50%. Considering that J doubles up with the ΔVM of 1 mV (Fig. 4(d)), we conclude that 1-qubit operations in the target DQD system, represented by a NOT operation, are reasonably robust against the noise of input signals.
All the modeling results discussed so far assumed a perfect symmetry in relation to the device geometry. However, a perfectly symmetric DQD structure may not be always guaranteed in the real world scenario due to unintentional lithographical errors. Although the geometric symmetry can be broken by a variety of physical features, including non-uniform compositions in SiGe layers and surface and interface roughnesses, to explore the connection between the broken symmetry and device functionality, here we only focus on the case wherein the left and right gate electrodes have different sizes. As Fig. 6(a) shows, this size mismatch is introduced in the simulation domain with two variables (ΔWL and ΔWR) that also affect the size of the middle gate electrode. In spite of the broken symmetry observed in the DQD potential profile at VL = VR = 555 mV and VM = 400 mV, its effect on the major factors that determine 1-qubit logic operations turned out not to be quite remarkable in the considered range of (ΔWL, ΔWR). In Fig. 6(b), we show the 1D-cuts of the electron density profiles (along the [100] direction in the center of the middle Si layer) and the corresponding variations in J for four cases (ΔWL = ±4 nm and ΔWR = ±4 nm). Even with a size-mismatch of 4 nm corresponding to ∼7% of the reference size of the electrodes, the dJ value led by the change in the electron density profile stays under 2% with respect to the symmetric case. The Zeeman splitting energy (ESR frequency) of each QD is shown in Fig. 6(c) and (d) as a function of ΔWL and ΔWR, respectively, and the results indicate that the relative change in the frequencies is less than just 0.03% at a size mismatch of 4 nm, implying the robustness of the logic operations.
Footnotes |
† Electronic supplementary information (ESI) available. See DOI: 10.1039/D0NR05070A |
‡ These authors contributed equally to this work. |
This journal is © The Royal Society of Chemistry 2021 |