Low-voltage polymer monolayer transistors for high-gain unipolar and complementary logic inverters

Abstract

Cutting-edge integrated circuits based on organic transistors, though promising, encounter a notable obstacle due to their tendency for high power consumption, thereby constraining their broader practical applications. This study demonstrates low-voltage polymer monolayer thin-film transistors (TFTs) and high-gain logic inverters, wherein the utilization of thin films of AlO_x as gate dielectrics effectively enhances the gate controllability of TFTs. A photolithography-compatible method using a sacrificial layer is proposed to pattern the polymer monolayer, which significantly reduces off-state and gate leakage currents to 10⁻¹² A and achieves a steep subthreshold swing of 86 mV dec⁻¹. These device performances generate a maximum intrinsic gain of 10⁴ V/V, enabling the development of zero-V_GS-load logic inverters with voltage gains up to 251 V/V at a −3 V operation voltage (V_DD). Additionally, hybrid complementary inverters by integrating with amorphous indium gallium zinc oxide (IGZO) exhibit ultra-high voltage gains of 841 V/V at a V_DD of 5 V and 7436 V/V at a V_DD of 30 V, potentially setting a new benchmark for logic inverters across various semiconductor systems. These results open new avenues for advancements in low-voltage organic and hybrid logics tailored for portable and wearable electronics.

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Introduction

Semiconducting polymers have recently garnered extensive attention due to their unique advantages such as mechanical flexibility, low-temperature processability, tunable optoelectronic properties, lightweight nature and potential for mass production.^1,2 Similar to their inorganic counterparts, polymer thin-film transistors (TFTs) represent one of the most important building blocks in plastic electronics, with immense potential in emerging fields such as the internet of things (IoT) and artificial intelligence (AI).³ To date, much effort has been devoted to the chemical design of semiconducting polymers, resulting in polymer TFTs with impressive field-effect mobilities of around 10 cm² V⁻¹ s⁻¹ in both holes and electrons. For instance, diketopyrrolopyrrole-based polymers with well-defined microstructures exhibited a record-high hole mobility of 24 cm² V⁻¹ s⁻¹.⁴ Isoindigo-based polymers were reported to demonstrate favorable electron-transporting properties, and an electron mobility of 9.7 cm² V⁻¹ s⁻¹ was achieved.⁵

While mobility is undeniably crucial for assessing transistor performance, an exclusive emphasis on this parameter neglects other equally vital performance metrics that are capable of bridging the gap between laboratory research and practical applications. The voltage range over which the transistor operates effectively is an important consideration for power consumption,⁶ but polymer TFTs often utilize a high operating voltage (the maximum value between a drain voltage and a gate voltage) ranging from ±20 V to ±100 V, because of the relatively low dielectric constant (ε) of the used gate dielectrics such as SiO₂, Cytop, and poly(methyl methacrylate) (PMMA).^7,8 It should be noted that the thermally grown SiO₂ from silicon wafers typically offers an atomically flat surface, facilitating the crystallinity and molecular order of organic semiconductors.^9,10 A thinner dielectric is in favor of lower operating voltage, but the tunnelling effect often leads to a high gate leakage current.¹¹ Additionally, new types of organic, inorganic and hybrid dielectrics with high κ have been developed to enable low-voltage organic TFTs.^6,12

A lower subthreshold swing (SS), defined as the gate voltage required to modulate the drain current by one order of magnitude when the TFT operates in the subthreshold region, is also crucial for enhancing energy efficiency and reducing power consumption in TFTs.¹³ Typically, the SS of polymer TFTs ranges from 0.5 V dec⁻¹ to even a few V dec⁻¹, which is one order of magnitude higher than the Boltzmann thermionic limit (60 mV dec⁻¹ at room temperature). Another challenge to low power consumption in polymer TFTs is their high off-state drain current, primarily originating from the extra unpatterned semiconductor layer. In spite of recent progress in ink-jet printing¹⁴ for efficient patterning of organic semiconductors, photolithography-compatible strategies are preferred for achieving high-density polymer TFT arrays on a wafer scale.

In this study, low-voltage polymer TFTs are demonstrated with an operating voltage of only 3 V, wherein thin films of AlO_x are utilized as gate dielectrics. It is found that thinner AlO_x noticeably enhances gate controllability without affecting field-effect mobility. The polymer monolayer TFT exhibits identical transistor performance, with a significantly minimized off-state current and gate leakage current to around 10⁻¹² A through the sacrificial layer method that is compatible with conventional photolithography techniques. Importantly, the SS of the polymer monolayer TFT is remarkably reduced from 1106 mV dec⁻¹ to 86 mV dec⁻¹ due to the much improved off-state drain current, compared to control devices with 300-nm-thick SiO₂ as the dielectric. Consequently, the maximum intrinsic gain of such low-voltage polymer monolayer TFTs reaches 10⁴ V/V in the subthreshold regime, and the resultant zero-V_GS-load logic inverter exhibits a voltage gain of up to 251 V/V at an operation voltage (V_DD) of −3 V. In addition, hybrid complementary inverters integrated using a p-type polymer monolayer and an n-type amorphous indium gallium zinc oxide (IGZO) offer superior voltage amplification capabilities, achieving voltage gains of 841 V/V at V_DD = −5 V and 7436 V/V at V_DD = −30 V, respectively, and these results rank among the record for organic and hybrid inverters.

Experimental

Materials and morphology characterization

Poly[(5,6-difluoro-2,1,3-benzothiadiazole-4,7-diyl)[3,3′′′-bis(2-decyltetradecyl)[2,2′:5′,2′′:5′′,2′′′-quaterthiophene]-5,5′′′-diyl]] (PffBT4T-2DT) was purchased from Nanjing Zhiyan Ltd and used without further purification. The molecular weight (M_n = 116.4 kg mol⁻¹ and M_w/M_n = 1.87) was determined by gel permeation chromatography (GPC) at 150 °C with TCB as the eluent. The surface morphology of polymer thin films was recorded using an atomic force microscope (AFM, Bruker MultiMode-V). The sample for transmission electron microscopy (TEM) was prepared through an FEI Helios G4 UX dual beam focused ion beam/scanning electron microscope (FIB/SEM).

Transistor fabrication

A bottom-gate bottom-contact architecture was utilized for the fabrication of polymer TFTs. (I) The gate electrode (Ti/Au 5 nm/30 nm) was patterned using conventional photolithography and electron beam evaporation (lift-off). (II) A 20 nm AlO_x layer was deposited using ALD at 300 °C. (III) The source/drain (S/D) electrodes (Ti/Au 5 nm/30 nm) were patterned using photolithography and electron beam evaporation (lift-off), and then cleaned by oxygen plasma and then immersed into a 10 mM 2,3,4,5,6-pentafluorothiophenol (PFBT, Aldrich) solution in ethanol for 6 h to form a self-assembled monolayer. (IV) The contact pad of the gate electrode was etched for electrical measurements. (IV) A solution of PffBT4T-2DT in chloroform was prepared with a polymer concentration of 1 mg mL⁻¹, and then spin-coated onto the prepatterned substrate at 1000 rpm for 30 s with a film thickness of around 15 nm. The corresponding polymer monolayer was dip-coated from 0.5 mg mL⁻¹ chloroform solution with a pulling speed of 200 μm s⁻¹. Afterwards, these ultrathin polymer films were annealed at 100 °C for 30 min to remove the residual solvent in a nitrogen glovebox.

In order to pattern the organic semiconducting layer, the sacrificial layer of parylene/Cytop (300 nm/200 nm) was first deposited onto the organic semiconductors. Afterwards, the conventional photolithography and 10∼15 min of dry etching using oxygen plasma with a power of 100 W were performed to obtain the desired pattern. For the device with SiO₂ as the dielectric, the highly doped silicon wafer with 300 nm thermally grown SiO₂ was directly used. All electric measurements were carried out using a nitrogen glovebox.

Inverter fabrication

The deposition procedures of the gate electrode and AlO_x dielectric were the same as those described in the transistor fabrication section. As shown in Fig. 5a, a sequential deposition strategy of 5-nm-thick SiO₂ and 7-nm-thick a-IGZO thin films was conducted in the same chamber using magnetron sputtering. Such ultrathin SiO₂ acted as the modification layer by preventing the dissociation of H₂O and O₂ into an active layer.¹⁵ After photolithography, the sample was etched using a dilute nitric acid solution to remove the unprotected IGZO. Then the photoresist was removed by acetone, and the sample was washed with acetone and isopropanol, respectively. Consequently, the patterned IGZO active layer was achieved. The bottom-gate top-contact configuration was used for the IGZO TFT, and the bottom-gate bottom-contact configuration was used for the polymer monolayer TFT. The deposition for the source and drain electrodes was described above. Before the deposition of the polymer monolayer, the patterned IGZO was passivated by AlOx grown by low-temperature ALD (200 °C). The channel length and width of the TFTs are summarized in Table S1 (ESI†).

Results and discussion

Low-voltage polymer TFTs

Thin films of AlO_x are deposited as gate dielectrics by atomic layer deposition (ALD), which is compatible with traditional microelectronic processing, and a bottom-gate bottom-contact configuration is employed for transistor fabrication, as illustrated in Fig. 1a. The details of device fabrication are described in the Experimental section. A 15-nm-thick film is spin-coated from PffBT4T-2DT solution as the semiconducting layer, and nanofibrillar structures are observed (Fig. 1b). The transmission electron microscopy (TEM) image in Fig. 1c depicts the cross-section of the polymer TFT. The influence of the AlO_x thickness on the gate controllability in polymer TFTs is first investigated. It is clear that polymer TFTs operate well in the saturation regime at a drain voltage (V_DS) of −3 V across varying AlO_x thickness from 70 nm to 20 nm, with an achievable on/off current ratio of around 10³ (Fig. 1d–f). A near-ideal linear relationship between the square root of drain current (I_DS) and the gate voltage (V_GS) in the on-state ensures the accuracy of mobility extraction from transfer characteristics (red lines in Fig. 1d and e). The resultant saturated mobility is around 0.1 cm² V⁻¹ s⁻¹ and remains nearly independent of the AlO_x thickness (Fig. 1j). It is worth noting that the on-state current (I_on) is significantly enhanced with decreasing dielectric thickness, indicating the improvement of the gate controllability (Fig. 1k). This improvement is further validated by the output characteristics (Fig. 1g–i). As summarized in Fig. 1l, I_DS attains saturation at a smaller I_DS in the case of a thinner dielectric, corresponding to a smaller saturation drain voltage (V_DSAT). As a result, 20-nm-thick AlO_x is selected as the gate dielectric for further investigation.

Fig. 1 (a) Schematic illustration of the polymer TFT and the chemical structure of the semiconducting polymer used in this work. (b) AFM height image of the spin-coated PffBT4T-2DT thin film. The right bottom inset is the AFM image of the dip-coated polymer monolayer. (c) Cross-section TEM image of PffBT4T-2DT TFTs. (d)–(f) Transfer and (g)–(i) output characteristics of PffBT4T-2DT TFTs with varying AlO_x thickness. (j) Saturated field-effect mobility, (k) on-state drain current and (l) saturation drain voltage as a function of AlO_x thickness.

Patterning of the organic semiconducting layer

Scaling down the PffBT4T-2DT thin film to a single molecular layer (monolayer) has a negligible impact on transistor performance.^16,17 However, as evident in Fig. 1d–f, the absence of patterning the semiconducting layer leads to a relatively high off-state drain current and gate leakage current, both of which are detrimental to static power consumption. Therefore, a patterning strategy using the sacrificial layer is proposed for the polymer monolayer TFTs, as shown in Fig. 2a. Compared with the spin-coated thin film, the dip-coated polymer monolayer shows larger nanofibers with a thickness of approximately 2.4 nm,^16,18 indicating a higher degree of molecular order (inset of Fig. 2b). Despite the previous reports,^19,20 we find that the direct contact between parylene and PffBT4T-2DT leads to a severe doping effect, while the Cytop surface suffers from a low yield of the photolithography process. Hence, a double layer of Cytop/parylene is designed: (i)

Fig. 2 (a) Schematic illustration of the patterning method proposed in this study. A double layer of Cytop/parylene is utilized as the sacrificial layer, which is compatible with the conventional photolithography technique. (b) Transfer characteristics of the polymer monolayer TFT after patterning. (c) Transfer and (d) output characteristics of the polymer TFT with 300 nm SiO₂ as the gate dielectric. (e) Extracted saturated field-effect mobility as a function of V_GS.

Cytop acts as a robust encapsulation layer for the semiconducting polymer; (ii) additional encapsulation using parylene ensures compatibility with a conventional photolithography technique and subsequent dry-etching processes. Fig. 2b displays the transfer characteristics of the patterned polymer monolayer TFT, with a resulting saturated mobility of 0.1 cm² V⁻¹ s⁻¹. A significant benefit of patterning is the three-order-of magnitude reduction in the off-state drain current to around 10⁻¹² A, accompanied by an increased on/off current ratio of 10⁶. Furthermore, the resultant gate leakage current is also sufficiently minimized to 10⁻¹¹∼10⁻¹² A after patterning the polymer monolayer (Fig. 2b and Fig. S1, ESI†). Additionally, the patterning process contributes to a significant improvement in the SS, achieving a minimum value of 86 mV dec⁻¹, lower than that reported in the literature.^21,22

The polymer monolayer TFT with 300 nm SiO₂ as the dielectric layer is fabricated for comparison. As shown in Fig. 2c and d, the typical linear/saturation behavior of I_DS is observed, but high operating voltages of −50 V including V_DS and V_GS are necessary. The corresponding threshold voltage (V_TH) and SS are −12 V and 1106 mV dec⁻¹, respectively. In sharp contrast, the utilization of 20 nm AlO_x remarkably improves the device performance of polymer monolayer TFTs due to much improved gate controllability, as summarized in Table 1. The interface between the polymer monolayer and the gate dielectric is also studied. The SS can be expressed as follows:¹²

SS = k_BT × ln(10)(1 + q²D_t/C_i)/q (1)

where k_B is the Boltzmann constant, D_t is the defect trap density, and C_i is the dielectric capacitance per area. Notably, the extracted D_t is 1.23 × 10¹² cm⁻² eV⁻¹ for SiO₂ and 1.22 × 10¹² cm⁻² eV⁻¹ for AlO_x (Table 1), revealing an identical defect trap density at the semiconductor/dielectric interface in spite of pronounced differences in the operating voltage, SS and V_TH. Another intriguing observation is that despite the comparable saturated field-effect mobility, the enhanced gate controllability from the AlO_x dielectric results in faster mobility saturation compared with SiO₂, as depicted in Fig. 2e.

Table 1 Performance comparison of polymer monolayer TFTs with different gate dielectrics

Dielectric	V DS(GS) (V)	V TH (V)	SS^a (mV de^−1)	μ (cm^2 V^−1 s^−1)	I on/Ioff	D t (cm^−2 eV^−1)
a Subthreshold swing. b Saturated field-effect mobility. c Defect trap density.
SiO2	−50	−12	1106	0.12	10^5	1.23 × 10^12
AlOx	−3	−0.2	86	0.10	10^6	1.22 × 10^12

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Unipolar logic inverters

In display driver circuits, inverters serve as the foundational cornerstone, functioning not only as the core element but also as the fundamental building block upon which the entire circuit architecture is constructed.²³ On the basis of these low-voltage polymer monolayer TFTs, the logic inverter is integrated with a zero-V_GS-load architecture, where a normal structure TFT acts as a driver (M1) and a zero-V_GS TFT with a gate source electrode interconnected as a load (M2), as shown in Fig. 3a and b. The operating state of the driver TFT is made to switch between the on state and off state by varying the input voltage in order to observe a voltage jump at the output. Fig. 3c shows the output characteristics and the method of extracting output resistance (r_o) at a V_GS of 0 V of the load M2 transistor, with a resultant load resistance of 1.36 GΩ.

Fig. 3 (a) Circuit diagram and (b) corresponding optical image of the zero-V_GS-load inverter, which contains two polymer monolayer TFTs, M1 and M2. (c) Output characteristics of M2. (d) g_m and r_o and (e) A_i of M1 as a function of V_GS. (f) Measured performance of the polymer monolayer zero-V_GS-load inverter.

Before the inverter measurement, an intrinsic gain A_i of polymer monolayer TFTs needs to be clarified, which can be estimated by the following equation:

A_i = g_mr_o (2)

where g_m is the transconductance of TFTs. Fig. 3d summarizes the transconductance (g_m) and output resistance (r_o) of the M1 TFT as a function of V_GS. With increasing V_GS, g_m is gradually increased but r_o is noticeably reduced by more than two orders of magnitude. A relatively high transconductance efficiency (g_m/I_DS) that is essential for a high-gain amplifier at a low power is obtained, with a maximum value of 24.9 S/A. Due to the high g_m and r_o, a very high A_i on the order of 10³∼10⁴ V/V in the subthreshold regime is obtained, as shown in Fig. 3e. It has been emphasized that such a value is not only much higher than that of most of the Si-metal-oxide-semiconductor field effect transistors (Si-MOSFETs) that have only a single-digit intrinsic gain, but also higher than that of the inorganic Schottky-Barrier thin film transistor that is specifically designed to solve the high gain challenges of inverters.¹² This high A_i also predicts that high-gain inverters can be achieved using low-voltage polymer monolayer TFTs.

Fig. 3f exhibits the input–output characteristic of the polymer monolayer inverter with a zero-V_GS-load architecture, where V_DD= −3 V is applied. A steep level transition of input voltages (V_IN) is observed, suggesting clear voltage amplification with a voltage gain (A_v) up to 251 V/V at the peak. When V_DD is decreased to −2 V, the corresponding A_v is slightly reduced but can still reach 181 V/V (Fig. S2, ESI†), comparable to the previously reported record based on high-crystalline small molecules.¹²

Unipolar circuits only need to process one kind of semiconductor layer, simplifying the fabrication procedure of integrated circuits.² Besides the zero-V_GS-load architecture, the diode-load and pseudo-E structures are also popular with sufficient simplicity. In particular, the former consists of two TFTs. Despite the requirement of more TFTs, the latter allows adjustable gain and voltage jump points, effectively integrating the functions of a bias circuit and an amplification circuit. Fig. 4 depicts the input–output characteristics of polymer monolayer inverters with these two circuit designs, where a low V_DD of 3 V is applied. In both cases, clear inverting behaviors of the input signal phase by 180° are observed (Fig. 4b and e). The resultant voltage gain is 7 V/V for a diode-load inverter and 13 V/V for a pseudo-E inverter, and further decreased with decreasing channel width of the driver transistor and bias voltages (Fig. S3 and S4, ESI†). This inverter performance could be effectively improved using a dual-gate technology to precisely tune the threshold voltage.²⁴

Fig. 4 (a) and (d) Optical images, (b) and (e) input–output characteristics and (c) and (f) voltage gain of diode-load (top) and pseudo-E (bottom) inverters based on low-voltage polymer monolayer TFTs. Insets in (b) and (d) are the corresponding circuit diagrams. V_DD = 3 V in both cases.

Complementary logic inverters

In comparison to unipolar circuits, complementary inverters consisting of both p-type and n-type transistors are capable of enhancing the capability of pulling up and pulling down of output voltage, thereby improving the noise margin. Furthermore, in complementary inverters, one transistor is consistently in the off state, characterized by the low off-state drain current, resulting in notably reduced power consumption.² Due to the lack of high-mobility n-type conjugated polymers,²⁵ an amorphous indium–gallium–zinc–oxide (IGZO) TFT is utilized, offering distinct advantages such as high electron mobility and minimal off-state drain current. This IGZO TFT is seamlessly integrated with a polymer monolayer TFT, as depicted in Fig. 5a. To optimize performance, an ultra-thin SiO₂ layer is interposed between the IGZO layer and the AlO_x dielectric for interfacial modification. Meanwhile, the IGZO TFT undergoes passivation using low-temperature AlO_x prior to the deposition of the polymer monolayer.¹⁵

Fig. 5 (a) Schematic illustration of the process flow for complementary inverters composed of the polymer monolayer TFT and IGZO TFT. (b) Transfer and (c) output characteristics of the IGZO TFT. (d)–(f) Input–output characteristics of the resultant complementary inverter at V_DD of 5 V and 30 V. (g) Voltage gain of the complementary inverter as a function of V_DD.

Fig. 5b and c exhibits the transfer and output characteristics of the integrated IGZO TFT within the complementary inverter, and the resultant gate leakage current is generally below 10⁻¹⁰ A (Fig. S5, ESI†). The linear electron mobility measures approximately 13.6 cm² V⁻¹ s⁻¹, with an SS of 113 mV dec⁻¹, an on/off current ratio of 10⁷ and a threshold voltage of 1.7 V. Compared to the pristine polymer monolayer TFTs, the resulting complementary inverter operates with a slightly higher V_DD of 5 V, achieving an ultra-high voltage gain of up to 841 V/V (Fig. 5d and e). Such voltage amplification is in excellent agreement with the theoretical simulation (823 V/V) from small signal analysis,²⁶ which is mainly attributed to the large output resistance of both TFTs. It is worth noting that this inverter performance surpasses that of the unipolar zero-V_GS-load polymer monolayer inverter by a factor of three (Fig. 3f), and exceeds that of all-polymer monolayer complementary inverters in our previous study by a factor of seven,⁶ as outlined in Table 2. Notably, increasing V_DD remarkably enhances the voltage gain of this hybrid complementary inverter, reaching a maximum value of 7436 V/V at a V_DD of 30 V (Fig. 5f and g and Fig. S6, ESI†).

Table 2 Performance summary of polymer monolayer and hybrid inverters

Design		Dielectric	Configuration	|VDD| (V)	Gain (V/V)
Unipolar	Zero-VGS	SiO2^16	BG	5	3
	Zero-VGS	AlOx	BG	3	251
	Diode	AlOx	BG	3	7
	Pseudo-E	AlOx	BG	3	13
CMOS	n-Type polymer monolayer	Cytop^25	TG	30	113
	IGZO	AlOx	BG	5	841

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The remarkable voltage amplification achieved in our study is benchmarked against various semiconductor systems, including pristine semiconducting polymers^{16,25,27–37} (both unipolar and complementary configurations), p-type oxide semiconductors,^38–42 p-type organic semiconductors^43–52 (such as polymers and carbon nanotubes) and n-type IGZO (complementary). At V_DD < 10 V, the voltage gains reported in the literature typically fall below 50 V/V, representing a roughly 4-fold difference compared to our hybrid inverters composed of the polymer monolayer and IGZO. As V_DD increases to 10 V or higher, the reported maximum voltage gain ranges between 100 V/V and 400 V/V, whereas our devices demonstrate voltage amplification reaching the order of 10³ V/V, potentially setting a new benchmark for logic inverters (Fig. 6).

Fig. 6 Benchmarking of polymer inverters that have been reported so far. V_DD is the absolute value of the operation voltage. Data are from ref. 15, 24 and 27–37 for polymer inverters, from ref. 38–42 for oxide/IGZO inverters and ref. 43–52 for organic/IGZO hybrid inverters. “Organic” materials in this figure include semiconducting polymers and carbon nanotubes.

Conclusions

In conclusion, a thin film of AlO_x is grown by the ALD method and acts as the gate dielectric for polymer monolayer TFTs, which effectively reduces the operating voltage to 3 V with improved I_on and V_DSAT. To pattern the polymer monolayer, a photolithography-compatible strategy utilizing a sacrificial layer is developed, significantly reducing the off-state current and gate leakage current to approximately 10⁻¹² A. Consequently, the resultant polymer monolayer TFTs exhibit a steep SS of 86 mV dec⁻¹ and maximum intrinsic gains of up to 10⁴ V/V. These exceptional transistor performances have facilitated the development of high-gain logic inverters, achieving a voltage gain of 251 V/V for the zero-V_GS-load configuration at a V_DD of −3 V. On the other hand, complementary inverters are also realized by integrating p-type polymer monolayer TFTs and n-type IGZO TFTs, resulting in ultra-high voltage gains of 841 V/V at a V_DD of 5 V and 7436 V/V at a V_DD of 30 V, respectively. This study thus paves a new way for further improvements in power consumption and large-area fabrication of organic electronic devices.

Author contributions

M. L. conceived the idea and supervised the study; M. C. and L. Z. fabricated TFTs and conducted the electrical measurement; Y. Z. fabricated inverters and conducted the electrical measurement; J. Z. and Z. Y. measured TEM; M. L. prepared the manuscript with support from all co-authors; all authors discussed the results and contributed to this work.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was supported by the National Key R&D Program of China under Grant 2019YFA0706100 and the National Natural Science Foundation of China under Grant 62074163.

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Footnotes

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d4tc01715c

‡ Contributed equally to this work.

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