Composition-modulated anti-ambipolar behavior enabled by two-dimensional GeS_xSe_1−x/SnS₂ van der Waals heterostructures for high-performance logic inverters

Abstract

Logic inverters, which lay the foundation for the functionality of large-scale integrated circuits, are achieved using anti-ambipolar transistors (AATs) based on two-dimensional (2D) van der Waals heterojunctions (vdWH). However, the impact of the doping strategy on the figures of merit of logic inverters based on 2D vdWH AATs has not been comprehensively analyzed. Herein, 2D free-standing GeS_xSe_1−x (0 ≤ x ≤ 0.73) with precisely tunable composition was grown to fabricate GeS_xSe_1−x/SnS₂ vdWH AATs to achieve an optimal logic inverter. By leveraging elemental modulation in GeS_xSe_1−x, the proposed vdWH was tuned from type-II to type-III band alignment, allowing for a distinctive tunneling process at various bias conditions. The proposed devices with poor S content exhibited a better peak-to-valley ratio of 6.6 × 10³ at x = 0.29 and a maximum peak current of 1.4 × 10⁻⁷ A at x = 0. Furthermore, the inverter built with the GeS_xSe_1−x/SnS₂ device achieved the highest voltage gain of 8.83 at x = 0.29, while the device with an S-rich AAT delivered a low static power of 12.1 pW, which is attributed to the optimization of band engineering and the low driving voltage under the bottom h-BN/Au structure. This work contributes insights into the expansion of alloy engineering in the construction of high-performance multi-valued logic inverters.

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New concepts

Systematic studies show that the energy band alignment of GeS_xSe_1−x/SnS₂ (0≤ x ≤ 0.73) van der Waals heterostructures (vdWHs) can be continuously tuned from type II to type III by varying the composition, which markedly modulates the tunneling window and surface-potential difference. Replacing the conventional SiO₂/Si substrate with an h-BN/Au single bottom-gate architecture further boosts the electrical modulation capability, yielding a higher peak-to-valley ratio (PVR) under a lower driving gate voltage (ΔV_g). By leveraging band alignment and alloy engineering, composition-modulated anti-ambipolar transport is achieved. The PVR, ΔV_g and peak current (I_peak) could be precisely adjusted from 8.7 × 10¹ to 6.6 × 10³, 15.3 V to 5.8 V and 8.7 × 10⁻¹¹ A to 1.4 × 10⁻⁷ A, respectively. Configurable logic inverters built using these composition-dependent AATs delivered a record voltage gain of 8.83 at x = 0.29 and an ultralow static power consumption of 12.1 pW at x = 0.73, offering a promising route for the rational design of low-power, high-gain multi-valued logic inverters based on 2D vdWHs.

The most significant advantage of logic inverters lies in the use of complementary metal–oxide semiconductors (CMOS) as fundamental device units, which promote efficient digital signal transmission, reduce static power, and facilitate the development of high-performance very-large-scale integrated circuits (VLSICs). Conventional CMOS technology based on complementary p-type and n-type unipolar transistors typically involves extrinsic and complicated doping processes, such as ion implantation and thermal diffusion, to achieve selective doping with shallow donor and acceptor energy levels.^1,2 Such doping processes can induce lattice damage within the Si-based semiconductor, necessitating a time-consuming thermal annealing step for recovery. Furthermore, considering the growing demand for VLSICs, the inevitable shrinkage of device dimensions to the nanometer scale leads to a severe short-channel effect,³ which in turn degrades their performance and diminishes the feasibility and controllability of traditional CMOS technology. The advent of atomically thin two-dimensional (2D) materials has enabled the realization of anti-ambipolar transistors (AATs) based on 2D van der Waals heterojunctions (vdWH) either through negative differential resistance (NDR)^4–6 or negative differential transconductance (NDT).^7–9 For example, AAT devices with NDR (defined as R_diff = dI_D/dV_D) behavior based on 2D Esaki diodes^6,10 and tunneling diodes^5,11 were expected to play a pivotal role in multi-valued logic inverters. However, the development of a practical AAT device with NDR behavior has remained elusive, which is primarily ascribed to the operational requirement of cryogenic temperatures. Most of the AAT devices also deliver a relatively low peak-to-valley ratio (PVR). In contrast, AAT devices with NDT (g_m = dI_ds/dV_g) behavior typically possess a planar three-terminal structure. They rely on the band alignment at the p–n junction heterointerface and the moderate doping level in the individual channel.¹ These devices exhibit Λ-shaped transfer curves at room temperature and enable high PVR larger than 10³, which are extremely desirable for practical applications in high-gain logic operations.¹² Concurrently, a high peak current (I_peak) can enhance the signal-to-noise ratio and diminish the interference of external noise on the signal amplitude, which is particularly crucial during low-voltage operation. Therefore, achieving precise control over band alignment and doping level, as well as obtaining a deeper understanding of the composition-mediated modulation of the I_ds−V_ds characteristics and anti-ambipolar properties, are highly important for the rational design and practical operation of 2D vdWH-based AATs.

Commonly, the anti-ambipolar properties of AATs based on 2D vdWH can be improved effectively by applying an electrostatic field,^9,13–15 strain field,^16,17 or a light field.^18–20 For example, Miao et al.¹³ achieved dynamic modulation of conduction polarity and NDT in an MoTe₂/BP vdWH device by tuning the type-I and type-II band alignment under an external electric field. Apart from the conventional SiO₂/Si bottom gate structure, a HfO₂ dielectric layer has been utilized to construct a ternary logic inverter based on a 2D BP/ReS₂ vdWH device at lower driving voltages (ΔV_g) to realize multifunctional nonvolatile logic-in-memory applications.²¹ In addition, strain control in an InSe/WSe₂ vdWH-based flexible device allowed the fabrication of bi-anti-ambipolar transistors with two tunable threshold voltages (V_th) as a result of the optimization of the conduction pathway, leading to the achievement of multi-value logic inverters.¹⁷ Moreover, photo-induced doping in an anti-ambipolar MoTe₂/BP vdWH device enabled dynamic adjustment of the peak position of the drain-source current (I_peak).²⁰ In spite of the advancements and modulation of the anti-ambipolar properties, the above-mentioned strategies ignore the key mechanism in leveraging band alignment for composition modulation to achieve desired I_ds−V_ds characteristics and anti-ambipolar properties.

Alloy engineering, an effective strategy for tailoring 2D materials with specific band structures, has demonstrated the potential to modulate band alignment, electronic properties, and transport behavior in 2D vdWHs.²² For instance, through composition modulation of the work functions at the 2D metallic alloy contacts, the contact potential difference in VS_2xSe_2(1−x)/MoS₂ vdWH could be tuned from −71.5 mV to 0 mV to 59.3 mV, that is, from Schottky to ohmic contacts by varying x from 0 to 1.²³ Likewise, by introducing controlled amounts of V atoms as dopants, continuous electrical polarity modulation of monolayer WS₂ from intrinsic n-type to ambipolar, then to p-type, and ultimately, to a quasi-metallic state was achieved, with obviously regulated current on/off ratios, allowing the construction of homogeneous CMOS inverters based on monolayer WS₂ with different doping concentrations.²⁴ Clearly, continuous and precise modulation of band alignment in 2D vdWHs is sought for the construction of multifunctional electronics. Systematically investigating the impact of composition modulation in 2D vdWH-based AATs on the main figures of merit of logic inverters holds great importance²⁵ but remains a daunting challenge.

In this work, 2D free-standing GeS_xSe_1−x (0 ≤ x ≤ 0.73) nanoplates, with composition-tunable band structures, were grown by the low-pressure rapid physical vapor deposition (LPRPVD) method reported in our previous work.²⁶ Compared to other 2D materials, these GeS_xSe_1−x nanosheets offer polymer-free transfer processes and continuously tunable bandgaps, enabling precise control of the electrical properties of AATs. These features overcome the limitations of customizing the electrical parameters of 2D AATs and present a new research direction in the material engineering of ambipolar transistors. Therefore, we further developed a GeS_xSe_1−x/SnS₂ vertical vdWH with a h-BN/Au single bottom gate configuration for AATs. The principle of variation in band alignment from type II to type III and the related tailored anti-ambipolar transport mechanisms were elucidated by modulating the S content and optimizing the dielectric architecture. Particularly, compared with the SiO₂/Si bottom dielectric structure, the h-BN/Au structure exhibited a markedly reduced ΔV_g and a significantly improved PVR. Thus, as the S composition varied from x = 0 to x = 0.73, the proposed AATs with S-poor compositions (x = 0.29) demonstrated an outstanding PVR and ΔV_g of 6.6 × 10³ and 5.8 V at V_ds = 3 V, significantly outperforming those with S-rich compositions (x = 0.42, and 0.73). Meanwhile, the I_peak was regulated monotonously from 1.4 × 10⁻⁷ A to 8.7 × 10⁻¹¹ A. Most significantly, the verification of the binary inverters not only highlights the capability of alloy engineering in achieving composition-modulated anti-ambipolar behavior, but also unfolded impressive figures of merit, including a maximum voltage gain of 8.83 at x = 0.29 and a static power of 12.1 pW at x = 0.73. This achievement marks a substantial advancement in the rational design, modulation, and fabrication of high-performance 2D vdWH logic inverters.

Characterization of the GeS_xSe_1−x and GeS_xSe_1−x/SnS₂ vdWH devices

In the experimental procedure, 2D GeS_xSe_1−x nanosheets with different S compositions were grown using a LPRPVD technique.²⁶ The nanosheets were characterized by energy-dispersive X-ray spectroscopy (EDS) to identify their atomic stoichiometric ratios, as depicted in Fig. S1 (SI): GeSe (x = 0), GeS_0.29Se_0.71 (x = 0.29), GeS_0.42Se_0.58 (x = 0.42), and GeS_0.73Se_0.27 (x = 0.73), which confirm that the S composition in the alloys could be accurately customized. Fig. 1a shows a schematic of the growth of the nanosheets. Taking x = 0.42 as an example, the 2D GeS_xSe_1−x nanosheets exhibited free-standing growth on a SiO₂/Si substrate, which can be flexibly transferred to other substrates after mechanical pressing using a polydimethylsiloxane (PDMS) film. The optical microscopic (OM) images of the horizontally distributed GeS_xSe_1−x (0 ≤ x ≤ 0.73) nanosheets on a SiO₂/Si substrate are shown in Fig. S2 (SI). The compositional changes in GeS_xSe_1−x nanosheets were observed from the X-ray diffraction (XRD) patterns, as shown in Fig. 1b. All GeS_xSe_1−x (0 ≤ x ≤ 0.73) nanosheets exhibited the characteristic peak of (040), which obviously shifted towards large diffraction angles as the S content increased. According to the Bragg equation,²⁷

2d sin(θ) = nλ (1)

the interlayer spacing (d) continuously decreases with the substitution of the larger Se atoms by the smaller S atoms, resulting in the shifting of the (040) characteristic peak from 33.7° (x = 0) to 34.3° (x = 0.73).²⁸ The trend of the phonon vibration modes of the 2D GeS_xSe_1−x nanoplates with varying S composition can be observed from the normalized Raman spectra shown in Fig. 1c. At x = 0, the typical Raman modes A¹_g (80 cm⁻¹), B_3g (149 cm⁻¹), and A³_g (185 cm⁻¹) were present. Those three Raman modes underwent a blue-shift as the S composition increased, and the A¹_g mode disappeared at x = 0.73. Furthermore, another typical Raman mode A²_g (264 cm⁻¹) appeared at x = 0.42 and red-shifted to 236 cm⁻¹ as the S composition increased to 0.73. Fig. 1d depicts the evolution of the energy band structure of the GeS_xSe_1−x and SnS₂²⁹ monolayers with respect to the vacuum level, as calculated in our previous work²⁶ using the Perdew–Burke–Ernzerhof function. These theoretical results confirm that the bandgap (E_g) of GeS_xSe_1−x increases with the increment of S composition, while its conduction band minimum (CBM) and valence band maximum (VBM) gradually shift downward. The tunneling window is defined as the energy level difference between the VBM of GeS_xSe_1−x and the CBM of SnS₂, and the calculated results are shown in Fig. 1e. When 0 ≤ x ≤ 0.42, the tunneling window keeps narrowing from 633.9 meV (x = 0) to 195.3 meV (x = 0.42) with increasing S composition and disappears when the S composition increases to 0.73. This demonstrates that the theoretical energy band alignment of GeS_xSe_1−x/SnS₂ vdWH can be switched between type II and type III by adjusting the S composition.

Fig. 1 Characterization of the GeS_xSe_1−x nanoplates and the energy band alignment of the GeS_xSe_1−x/SnS₂ vdWH. (a) Schematic depicting the growth of the GeS_xSe_1−x nanosheet. (b) XRD patterns and (c) Normalized Raman spectra of the GeS_xSe_1−x nanosheets with different S compositions. (d) Theoretical band alignment, (e) tunneling window, (f) SPD and (g) height profile data of the GeS_xSe_1−x/SnS₂ vdWH with different S compositions.

Guided by the theoretical results, experiments were carried out to further investigate the electrical properties, including I_ds−V_ds and I_ds−V_g curves. First, fresh GeS_xSe_1−x/SnS₂ vdWH devices were fabricated on SiO₂/Si substrate with four different S compositions (0, 0.29, 0.42, and 0.73) and characterized. The OM images, atomic force microscopy (AFM) images, Raman spectra, and energy band alignments before and after contact are shown in Fig. S3–S6, respectively (SI). The atomic surfaces of the GeS_xSe_1−x, SnS₂, and overlapped regions were clean and smooth, as observed by OM and AFM. All the prominent Raman peaks of the individual materials appeared in the overlapping area with stronger intensities, indicating that these vdWHs maintained good crystalline quality after dry transfer and the device manufacturing process. The surface potential difference (SPD) across the heterointerface was evaluated by Kelvin probe force microscopy (KPFM) according to the formula shown in Note S1 (SI). As seen in Fig. 1f, the SPD of the GeS_xSe_1−x/SnS₂ vdWHs increased as x increased from 0 to 0.42, with values of 177 mV (x = 0), 249 mV (x = 0.29), and 376 mV (x = 0.42). However, when the S composition increased to 0.73, the SPD of the vdWH decreased to 142 mV, which is related to the transition of its band alignment type. In particular, regardless of the composition of the S dopant, the surface potential of GeS_xSe_1−x was always higher than that of SnS₂, which means that the direction of the built-in electric field is from GeS_xSe_1−x toward SnS₂. Moreover, the GeSe/SnS₂ vdWH is used as an example to demonstrate the diffusion and drift process of the charge carriers before and after contact, as shown in Fig. S3d.

Before contact, this vdWH exhibits a type-III energy band alignment, with a Fermi energy level (E_f) difference of 177 meV. After contact, the higher E_f of GeSe causes the electrons of GeSe to diffuse to the SnS₂ side and the holes of SnS₂ to transfer to the GeSe side until thermal equilibrium. This contributes to the upward band bending of GeSe and the downward band bending of SnS₂ at the interface edge. The built-in electric field, with a potential value of 177 mV, points from GeSe to the SnS₂ side. The band alignments of the other vdWHs (x = 0.29, 0.42, and 0.73) before and after contact are shown in Fig. S3d, S4d and S5d, respectively (SI). According to the theoretical analyses and KPFM results, the ΔE_f between GeS_xSe_1−x and SnS₂ first increases gradually with the increase in S composition, so that the energy band edge bending progresses steeply until the band alignment transforms from type III to type II at x = 0.73. As depicted in Fig. S7, the thicknesses of the h-BN nanosheets used in all the devices were between 55 and 65 nm, which can be easily obtained by mechanical exfoliation and is completely sufficient for a dielectric layer. As shown in Fig. 1g, the thicknesses of GeS_xSe_1−x and SnS₂ were both maintained in the range of 30–50 nm. This ensures that the thickness of these multilayered samples has a negligible influence on the energy band alignment and device performance, thereby precluding the effects of thickness engineering.

GeSe/SnS₂ vdWH FETs on different dielectric gate structures

GeS_1−xSe_x/SnS₂ FETs with a h-BN/Au single bottom gate configuration were designed specifically for high-performance logic inverter applications, as depicted in Fig. 2a. Specifically, multilayered SnS₂ nanosheets were obtained using the mechanical exfoliation technique together with a PDMS-assist transfer method, while the GeS_1−xSe_x nanoplates were directly transferred through a facile polymer-free pressing transfer method, benefiting from the free-standing growth mode.²⁶ To achieve optimal electrical performance, a h-BN/Au bottom gate structure was designed, in which the h-BN served as the 2D dielectric layer (ε_r = 3.5³⁰). h-BN has an atomically smooth surface without dangling bonds and can form a van der Waals interface with 2D GeS_xSe_1−x and SnS₂, which leads to a low defect density.³¹ Additionally, h-BN possesses a higher dielectric strength (∼0.8 V nm⁻¹) than SiO₂ (∼0.3 V nm⁻¹), allowing for the design of thinner dielectric layers and increased surface capacitance (C_ox = ε_rε₀/d), thereby enhancing gate control capability.³² Moreover, it can be more easily fabricated than the HfO₂ insulator layer,³³ thereby facilitating electrostatic modulation with low static power dissipation for enhanced gain.²⁰Fig. 2b displays the OM image of the typical GeSe/SnS₂ vdWH device. Notably, the chosen SnS₂ and GeSe nanosheets were successively stacked onto the pre-patterned source (S) and drain (D) electrodes, respectively, to circumvent performance degradation induced by organic solvents and high-energy deposition, which are prone to causing the Fermi pinning effect.³⁴ In addition, the single bottom Cr/Au gate electrode was completely below the whole channel of the device, enabling effective modulation of the carrier concentrations in different doping regions. Then, the electrical transport properties of the GeSe/SnS₂ FET were measured using the E₁–E₂ electrodes, while the E₁–E₃ and E₂–E₄ pairs were used to measure the electrical properties of individual GeSe and SnS₂, respectively.

Fig. 2 Field-effect electrical performance of the GeSe/SnS₂ AATs with two different bottom gate structures. (a) 3D Schematic and (b) OM image of the GeSe/SnS₂ device with a h-BN/Au bottom gate structure. (c) The I_ds−V_g curves of the individual GeSe and SnS₂ FETs with the h-BN/Au bottom gate structure at V_ds = 1 V. Comparison of the (d) I_ds–V_g curves, (e) PVR and I_peak, (f) ΔV_g and V_peak of the vdWHs with two different bottom gate structures at V_ds = 1 V.

The transfer curves of the devices in the linear scale and semilogarithmic scale are shown in Fig. 2c and Fig. S8 (SI), respectively. The transfer characteristics at V_ds = 1 V indicate the p-type and n-type conducting behaviors of the unipolar GeSe and SnS₂ FETs, respectively. The lower on-current observed in the GeSe transistors compared with the SnS2 counterpart is primarily attributed to a difference in intrinsic carrier concentration. Using the linear extrapolation method,³⁵ the current on/off ratio (I_on/I_off ratio) and the p-type threshold voltage (V_th,p) of GeSe were evaluated to be 10² and 3.9 V, respectively. While this method is widely used in 2D FET research^25,36,37 and shares similarity with CMOS, there are no traditional inversion channels in 2D FETs due to the atomic thickness limitation and the electrostatic modulation mechanism. Similarly, for SnS₂, the I_on/I_off ratio and the n-type threshold voltage (V_th,n) were 3 × 10⁶ and −5.6 V, respectively. To highlight the electrical modulation ability of the h-BN/Au single bottom gate structure, the electrical performance of individual GeSe and SnS₂ FETs on the SiO₂/Si substrate were also measured, as shown in Fig. S9 (SI). For the GeSe (SnS₂) FET on the SiO₂/Si structure, the values of V_th and I_on/I_off ratio were 20 V (−58 V) and 5 × 10¹ (4 × 10⁶), respectively. Clearly, the electrical parameters (I_on/I_off and V_th) of the FET with the h-BN/Au gate structure were superior to those on the SiO₂/Si substrate. The proves that our fabricated h-BN/Au gate structure, with the advantages of fewer scattering centers and high interface quality, can effectively control the carrier concentration under a narrower driving voltage (ΔV_g = V_off − V_on) of 9.4 V without a large gate leakage current.³⁸ The mobility of the SnS₂ channel was thereby boosted to 4.21 cm² V⁻¹ s⁻¹, substantially exceeding the values reported for its counterparts with conventional Si/SiO₂ substrates.³⁹ This distinct comparison directly verifies that the h-BN dielectric layer also possesses the capability to enhance carrier mobility. The I_ds−V_g curves of the GeSe/SnS₂ AATs with two different gate structures at V_ds = 1 V are shown in Fig. 2d (linear scale) and Fig. S10 (semilogarithmic scale), which exhibit distinct Λ-shaped curves (i.e., anti-ambipolar characteristics), demonstrating the switch between p-type and n-type characteristics as the gate voltage (V_g) was swept from 6 V to −6 V. As shown in Fig. 2e and f, the electrical parameters of the AAT device, including the peak-to-valley ratio (PVR), I_peak, ΔV_g, and peak voltage (V_peak),⁹ were calculated from the transfer curves presented in Fig. 2d. Obviously, the h-BN/Au gate structure endowed the GeSe/SnS₂ AAT with a higher PVR of 250 compared with the SiO₂/Si gate structure. Meanwhile, the h-BN/Au single bottom gate structure achieved a twofold higher I_peak (27.4 nA) than that of the normal SiO₂/Si gate structure (13.2 nA). The same tendencies were observed for ΔV_g and V_peak, as seen in Fig. 2f and reported in other similar works,^38,40,41 uncovering the superior electrostatic modulation capability of the h-BN/Au gate structure.

The overall advantages of the h-BN/Au gate structure, in terms of the electrical properties of the AAT device, can be ascribed to the smaller V_th and higher carrier mobility (μ) of individual GeSe and SnS₂ (Fig. 2c), which enables the carrier concentration to be fully depleted at a small V_g and accumulated rapidly in the ΔV_g. It is known that the V_on and V_off values of the heterojunction channel in the AAT can be explained by the electrical properties of

the individual p-type and n-type channels. The μ and V_th of the individual GeSe and SnS₂ FETs with the h-BN/Au gate structure were calculated, as shown in Note S2 (SI), and thus the μ and V_th of the GeSe/SnS₂ AAT were calculated using the following formulas:⁴²

where W is the channel width, C_i is the capacitance of the insulating layer between the gate and the semiconductor (i.e., the capacitance C_h-BN of h-BN), and L_p and L_n are the channel lengths of the GeSe and SnS₂ FETs, respectively.

The above relevant parameters of the GeSe/SnS₂ AAT, as well as the individual GeSe and SnS₂ FETs, with the h-BN/Au bottom gate structure are summarized in Table 1. It can be seen that the μ_n, μ_p, V_th,n, and V_th,p of the AAT almost match the parameters of the individual GeSe and SnS₂ FETs, indicating that the anti-ambipolar behavior in the heterojunction channel is mainly modulated by the V_th values and carrier mobility of the individual channels.

Table 1 The μ and V_th of the GeSe/SnS₂ AAT and individual GeSe and SnS₂ FETs with the h-BN/Au bottom gate structure at V_ds = 1 V

Structure	μn (cm^2 V^−1 s^−1)	Vth,n (V)	μp (cm^2 V^−1 s^−1)	Vth,p (V)
AT	4.21	−5.2	5.67 × 10^−2	4.2
GeSe	N/A	N/A	6.78 × 10^−2	3.9
SnS2	3.3	−5.6	N/A	N/A

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Rectification behavior and tunneling mechanism in GeS_xSe_1−x/SnS₂ AATs

Fig. S11 (SI) shows the OM images of the other GeS_xSe_1−x/SnS₂ (x = 0.29, 0.42, 0.73) FETs with the h-BN/Au bottom gate structure. The I_ds−V_ds curves of individual SnS₂ (E₂–E₄ pairs) and GeS_xSe_1−x (E₁–E₃ pairs) exhibited linear symmetric behavior between the semiconductor and Au, as seen in Fig. S12 and S13 (SI), which indicate that they possessed ohmic contacts, and the I_ds−V_ds curve of the heterojunction channel was dominated by the potential barrier region.⁴³ According to the formula σ = L/SR (L is the length of the current path, S is the cross-sectional area, and R is the resistance), the conductivity (σ) of the GeS_xSe_1−x decreased from 6.25 × 10⁻¹ S m⁻¹ to 3 × 10⁻⁴ S m⁻¹ as the S content increased, as depicted in Fig. S14b (SI), which is consistent with previous reports.²⁶ As for GeS_xSe_1−x/SnS₂, the corresponding I_ds−V_ds curves at V_g = 0 V are shown in Fig. 3a. It can be observed that the forward I_ds at V_ds = 3 V significantly decreased from 1.4 × 10⁻⁷ A to 4.8 × 10⁻¹¹ A with an increase in S composition. Fig. S15 (SI) depicts the output curves of the GeS_xSe_1−x/SnS₂ FETs. The rectification ratio (RR) is defined as the ratio of I_ds values at V_ds = 3 V and −3 V. As shown in Fig. S16, the output curves of the forward and reverse sweeps exhibited the same trend, and the trend of the double-sweep transfer curves was also the same. It is worth mentioning that the hysteresis behavior of the transfer curve may be mainly derived from the metal-semiconductor contact interface and the surface defects in the channel materials. As shown in Fig. S17, by comparing the transfer curves of the GeSe/SnS₂ devices with h-BN and SiO₂ gate dielectric, it was found that the device supported by the latter has a larger hysteresis window, further demonstrating the superiority of the h-BN/Au gate structure. The plots of the corresponding RR versus V_g are shown in Fig. 3b. In the forward V_g region, the RR at x = 0.29, 0.42, and 0.73 monotonously decreased with the increase of V_g. Nevertheless, the RR at x = 0 showed little variation caused by the high carrier concentration at the GeSe/SnS₂ interface, demonstrating the minimal effect of V_g on RR. Under a larger negative V_g, the RR decreased with increasing V_g because of the effect of the strong negative V_g, which can drive more holes from GeSe to accumulate in the heterojunction channel and lead to the domination of the hole drift current. Overall, the V_g of the GeS_0.29Se_0.71/SnS₂ FET had the most significant impact on the RR, which effectively changed from 21.8 to 2.5 × 10³, differing by two orders of magnitude. Simmons approximation was used to understand the intrinsic transport mechanism in the forward current region. The equations^44,45 used were as follows:where d is the tunneling width, Φ is the potential barrier height, and m* and h denote the effective electron mass and Planck constant, respectively. According to the above equations, the plots of ln (I_ds/V_ds²) versus 1/V_ds are displayed in Fig. 3c. Within the V_ds range of 0 V to 3 V, both direct tunneling (DT) and Fowler–Nordheim tunneling (FNT) were present in GeSe/SnS₂ and GeS_0.29Se_0.71/SnS₂ FETs, while the devices with x = 0.42 and 0.73 only exhibited the DT process. The GeS_0.29Se_0.71/SnS₂ vdWH FET was chosen as the representative to discuss the transport mechanism. It clearly showed a transition from the logarithmic state of DT at small V_ds (red region) to the linear state of FNT with a negative slope at larger V_ds (blue region). The transition voltage (V_trans) was 0.71 V. According to the formula Φ = qV_trans, the tunneling barrier height was concluded to be 0.71 eV.⁴⁶ Based on the transport mechanism, the band alignment diagrams of the GeS_0.29Se_0.71/SnS₂ vdWH at various V_ds values were deduced, as shown in Fig. 3d–f. Under reverse bias, a band-to-band tunneling (BTBT) process was observed. The I_ds was ultralow because the minority electrons in GeS_0.29Se_0.71 flow through the tunneling widow, with the electron depletion region in GeS_0.29Se_0.71 and the electron accumulation region in SnS₂.⁴⁶ At small forward bias (0 V < V_ds < V_trans), the trapezoidal tunneling potential barrier at the interface dominated charge transfer via DT.⁴⁴ However, at a larger forward bias (V_ds > V_trans), the potential barrier transformed into a triangular shape, allowing more electrons in SnS₂ to easily overcome the potential barrier and transfer to GeS_0.29Se_0.71. Therefore, the DT and FNT processes determine the electron transfer behavior from the CBM of SnS₂ through the potential barrier to the CBM of GeS_0.29Se_0.71, leading to a continuous increase in the forward I_ds. While the GeSe/SnS₂ FET exhibited the aforementioned transport behavior, it differed at higher V_ds. A narrow sublinear region was obtained in the presence of a space-charge limited region.^47,48 The phenomenon could be reproduced in two other GeSe/SnS₂ FETs with h-BN/Au and SiO₂/Si substrates, as shown in Fig. S18 (SI).

Fig. 3 Charge transport properties and intrinsic mechanisms of the GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) FETs. (a) I_ds−V_ds curves. (b) The RR versus V_g plots. (c) Fowler−Nordheim plots of ln(I_ds/V_ds²) versus 1/V_ds when scanned at V_ds > 0 V. Band alignment of the GeS_0.29Se_0.71/SnS₂ FET at (d) V_ds < 0 V, (e) 0 V < V_ds < V_trans, and (f) V_trans < V_ds.

Dependence of anti-ambipolar behavior on the S composition in GeS_xSe_1−x/SnS₂ vdWH

The transfer curves of the GeS_xSe_1−x/SnS₂ device with four different S compositions (0 ≤ x ≤ 0.73) at V_ds = 3 V are shown in Fig. 4a (linear scale) and Fig. S19 (semilogarithmic scale), which demonstrate obvious and composition-dependent Λ-shape transfer characteristics. It is clear that the transfer characteristics of the GeS_xSe_1−x/SnS₂ AAT devices can be divided into three regions based on the charge accumulation state, using which the on-set voltage (V_on) and off-set voltage (V_off) of the device can be determined. In region I, the SnS₂ layer is depleted, which gives rise to high resistance in the entire channel. The resistance of the entire channel decreases significantly with the rise in V_g, eventually approaching the V_th,n of the individual SnS₂ FET, which is denoted as V_on. In region II, both the SnS₂ and GeS_xSe_1−x layers are under the sub-threshold regime, and I_ds gradually increases with increasing V_g and reaches a peak current. In region III, the GeS_xSe_1−x layer is gradually depleted, and thus the current decreases more slowly than that in region I, which is mainly attributed to the relatively lower carrier mobility of GeS_xSe_1−x than that of SnS₂. Similarly, the resistance of the entire channel increases gradually with the increase of V_g until it approaches the V_th,p of the individual GeS_xSe_1−x FET, which is referred to as V_off. Notably, the values of V_on (V_off) of the GeS_xSe_1−x/SnS₂ AATs with lower S composition (x = 0 and 0.29, i.e., S-poor) were smaller than those with higher S composition (x = 0.42 and 0.73, i.e., S-rich), resulting in dynamic control of ΔV_g. As shown in Fig. S20 (SI), the transconductance (g_m = dI_ds/dV_g) drastically varied from a positive to a negative value across the V_peak, exhibiting the presence of NDT. The V_peak corresponding to the I_peak was consistent with that when the g_m changes from a positive to negative value.⁴⁹ Conversely, the values of V_peak of the GeS_xSe_1−x/SnS₂ AATs with S-poor composition were significantly higher than those with S-rich composition. As shown in Fig. 4b and c, the key electrical performance of the GeS_xSe_1−x/SnS₂ devices with S-poor and S-rich compositions were synthetically compared. The ΔV_g and |V_peak| of the GeS_0.29Se_0.71/SnS₂ AAT with S-poor composition reached the minimum values of 5.8 V and 2.6 V, respectively, which are nearly 3 times lower than those of the GeS_0.42Se_0.58/SnS₂ AAT with S-rich composition. Likely, the GeS_0.29Se_0.71/SnS₂ AAT with S-poor composition also achieved the maximum PVR of 6.6 × 10³. Distinctly, The I_peak decreased monotonously from 1.4 × 10⁻⁷ A to 8.7 × 10⁻¹¹ A with increasing S composition, which may stem from the decrease in the σ and hole mobility (μ_p) of the individual GeS_xSe_1−x FETs as the S composition increases (Fig. S21, SI). The transfer curves of GeS_xSe_1−x FETs under high-vacuum conditions are shown in Fig. S22. It can be observed that the electrical characteristics of the FETs changed with the variation in S composition, which not only rules out the effects of surface adsorption and humidity but also confirms that the changes in electrical characteristics are indeed primarily determined by the ratio of S and Se. Importantly, these results strongly confirm the significant tunability of the electrical properties of GeS_xSe_1−x/SnS₂ AATs through alloy engineering. The optimal comprehensive anti-ambipolar characteristics were obtained at x = 0.29. Table 2 summarizes the key parameters of the GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) AATs and provides a comparative evaluation of similar reported devices. It is evident that through sulfur content modulation, the band structure of the GeS_xSe_1−x/SnS₂ AATs can be tuned from type-II to type-III alignments. This behavior dynamically reshapes the carrier transport pathways between the channel and barriers, enabling precise configuration of anti-ambipolar characteristics. Specifically, at a sulfur content of x = 0.29, the device achieved a ΔV_g of 5.8 V, a significant reduction compared to conventional devices with the SiO₂ gate structure. The low ΔV_g will lower the power consumption and can suppress the voltage drift caused by interfacial defects. Concurrently, the V_peak was optimized to −2.6 V, approaching the zero-bias condition, which reflects balanced electron and hole injection barriers under the Type-III band alignment, thereby enhancing carrier injection efficiency and transport symmetry. Furthermore, the I_peak was regulated to 1.6 × 10⁻⁹ A, striking an optimal balance. This avoids noise sensitivity from insufficient current while preventing excessive static power consumption from large currents. Notably, the device attained a PVR of 10³, which is comparable to the values reported in the literature. Leveraging h-BN interfacial passivation to effectively suppress defect scattering, our work achieves synergistic optimization across power consumption, performance, and reliability. This circumvents the multidimensional performance trade-offs of traditional SiO₂-based devices and pioneers a new technical pathway for low-voltage, highly reliable anti-ambipolar transistors. To enhance the reliability of the above conclusions, another set of GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) AATs was prepared, as shown in Fig. S23–26 (SI). The key parameters were extracted and compared with the first set of devices, as summarized in Table S1 (SI), with each set comprising devices made of four distinct S compositions (x = 0, 0.29, 0.42, and 0.73). In total, eight devices were measured and analyzed in this study. The consistency of the data is evident from the insignificant variation between the two sets, and the same correlation between S doping levels and device performance was observed in both data sets.

Fig. 4 Transfer characteristics and transport mechanism of the GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) AATs. (a) The Λ-shape transfer curves with three transmission regions at V_ds = 3 V. (b) The ΔV_g and V_peakversus S composition plots and (c) PVR and I_peakversus S composition plots extracted from (a). (d) Equivalent circuit model and the correlating band alignments of the GeS_0.29Se_0.71/SnS₂ vdWH AAT in three distinct V_g regions at V_ds = 3 V.

Table 2 Summary of the device performance (ΔV_g, V_peak, I_peak, and PVR) of the as-fabricated AATs in comparison with previously reported AATs

AATs (p-/n-channels)	Dielectric layer	ΔVg (V)	V peak (V)	I peak (A)	PVR	Band alignment	Ref.
GeSe/SnS2	h-BN	9.4	−3.8	1.4 × 10^−7	1.5 × 10^3	Type-III	This work
GeS0.29Se0.71/SnS2	h-BN	5.8	−2.6	1.6 × 10^−9	6.6 × 10^3	Type-III	This work
GeS0.42Se0.58/SnS2	h-BN	15.3	−7	1.6 × 10^−10	5.5 × 10^2	Type-III	This work
GeS0.73Se0.27/SnS2	h-BN	13.8	−5.6	8.7 × 10^−11	87	Type-II	This work
WSe2/InSe	h-BN	20	−14	4 × 10^−6	10^4	Type-II	50
BP/MoTe2	SiO2	45	−5	1 × 10^−6	30	Type-I	13
WSe2/ReS2	SiO2	8	−6.7	4 × 10^−10	—	Type-II	51
MoTe2/h-BN	SiO2	≈30	≈0	3 × 10^−7	2 × 10^2	Type-II	52
WSe2/PdSe2/MoS2	h-BN	<1.5	<−0.1	1 × 10^−8	1.1 × 10^5	—	53
SnSe1.5S0.5/MoTe2	SiO2	≈46	−38	4.3 × 10^−8	6.7 × 10^3	Type-III	25
SnS2/MoTe2	SiO2	30	−13	8 × 10^−10	4.5	Type-III	33
InSe/BP	SiO2	—	2.22	1.5 × 10^−10	>10	Type-III	54
WSe2/SnS2	h-BN/SiO2	26	5	3 × 10^−8	10^4	—	55
MoTe2/CrOCl	SiO2	40	−20	3 × 10^−8	—	—	56

---

In order to deeply investigate the conductive behavior of the anti-ambipolar characteristics of GeS_xSe_1−x/SnS₂ AAT devices, the equivalent circuit model was utilized.³⁶ The I_ds obtained from the transfer characteristics curves can be defined as the shoot-through current in the CMOS inverter, which refers to the overlapping region of I_ds in the transfer curves of the individual GeS_xSe_1−x and SnS₂ FETs. Taking the GeS_0.29Se_0.71/SnS₂ AAT device as an example, Fig. 4d demonstrates the equivalent circuit model in three distinct V_g regions at V_ds = 3 V. In particular, the p-type GeS_0.29Se_0.71 FET and n-type SnS₂ FET can be regarded as a p-MOS and n-MOS, respectively. These two MOS parts are connected in series to form an equivalent circuit model. The circuit analysis can be sorted into three regions. In the three V_g regions, the direction of current flowing through CMOS coincides with the direction of hole movement described in the circuit diagram, which is depicted by the red arrows. (i) When V_g < V_on, the p-MOS is in the conducting state with holes accumulating near the gate, while electrons are turned off. (ii) When V_on < V_g < V_off, both p-MOS and n-MOS are in the conductive state, turning the circuit on. Within this region, as V_g monotonically increases, I_ds rapidly varies from an upward trend to a downward trend, because of depletion in the n-MOS due to its cutoff state, yielding a Λ-shape transition. (iii) When V_g > V_off, the circuit turns off again due to the complete depletion of p-MOS, even though the n-MOS is in a conductive state. Meanwhile, the band alignment analysis was also employed to further understand the anti-ambipolar transport process. At region i, holes are accumulated in the GeS_0.29Se_0.71 layer due to its p-type nature, while complete depletion of the n-type SnS₂ layer fully shuts off the overall heterojunction, resulting in a low I_ds. With increasing V_g (region ii), a moderate decrease in hole concentration occurs in the GeS_0.29Se_0.71 layer accompanied by a more significant increase in electron concentration in the SnS₂ layer, allowing both holes and electrons contribute concurrently to I_ds, and thus I_ds increases rapidly. Region iii refers to the stage in which the depletion of holes in the GeS_0.29Se_0.71 layer occurs more rapidly than the accumulation of electrons in the SnS₂ layer, which brings about the gradual reduction of I_ds until the whole heterojunction is turned off again.

Logic inverters based on GeS_xSe_1−x/SnS₂ vdWH AATs

This study demonstrates the application of GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) AATs in binary logic inverters. The schematic in Fig. 5a shows that the inverters consisted of p-type GeS_xSe_1−x FET and n-type SnS₂ FET.⁵⁷ The supply voltage (V_dd) was applied to the p-FET terminal, while the ground (GND) was applied to the n-FET terminal. The input voltage (V_in) and output voltage (V_out) were connected to the common V_g and the vdWH region, respectively. The corresponding equivalent circuit diagram is shown in Fig. 5b. The transfer characteristics of the GeS_0.29Se_0.71/SnS₂ (x = 0.29) AAT maintained an ‘Λ’ shape across varying V_dd, steepening with an increase in V_dd, as shown in Fig. S27 (SI). The V_out–V_in diagram of the inverter (x = 0.29) is shown in Fig. 5c, with the inset showing the truth table for the digital logic states. High V_out (i.e., logic “1”) corresponds to low V_in (i.e., logic “0”) and vice versa.⁵⁸ As V_dd increases, the logic state transitions of the inverter become more rapid, resulting in a higher voltage gain (Gain is calculated using the formula Gain = −dV_out/dV_in).⁵⁹ The Gain-V_in curves are illustrated in Fig. 5d, with the maximum gain of 8.83 at V_dd = 3 V. Similarly, the characteristics of the inverters changed with changes in the S composition. The voltage transfer characteristics (VTC) of the inverters at x = 0, 0.42, and 0.73 under V_dd = 3 V are depicted in Fig. S28, and the insets show the corresponding Gain versus V_in plots (SI). Regardless of the S content, all the devices displayed two logic states, and the voltage gain displayed a single peak, confirming their binary inverter functionality. However, with varying S composition, the binary inverters exhibited different transition voltages and transition region widths, which result in variations in voltage gain, as illustrated in Fig. S29 (SI). The binary inverter at x = 0.29 achieved the maximum gain, with decreasing gain observed in devices with increasing S compositions. Notably, the output leads were pre-deposited along with the source and drain electrodes to circumvent performance degradation induced by organic solvents and high-energy deposition steps. The P_out−V_in curves of the GeS_xSe_1−x/SnS₂ vdWH inverters, as shown in Fig. S30 (SI), were used to extract the maximum static power dissipation (P_static).^60,61 Consequently, the plot of P_staticversus the S composition is depicted in Fig. 5e. Specifically, the device with x = 0.73 had the smallest P_static, of about 12.1 pW. Moreover, the devices with x = 0.29 and 0.42 showed similar P_static, both at around 30 pW. Fig. 5f demonstrates a comparison of the P_static of GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) binary inverters and previously reported works,^62–71 and the P_static of inverters in the highlighted blue region exhibit the pW level. In the context of growing demand for power static optimization, the low-power characteristics of GeS_xSe_1−x/SnS₂ AATs, notably their static power consumption at the pW level, are promising for a wide range of applications in the field of high-performance computing and electronic devices and for the development 2D material integration processes, as they are and compatible with existing technologies.

Fig. 5 Binary logic inverters based on GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) vdWH AATs. (a) The schematic and (b) equivalent circuit diagram of the binary logic inverters. (c) V_out–V_in curves and (d) gain–V_in curves of the GeS_0.29Se_0.71/SnS₂ (x = 0.29) binary logic inverter with different V_dd. (e) P_static of the inverters with different S compositions at V_dd = 3 V. (f) Comparison of P_static with other previously reported inverters. The inverters in the highlighted blue area have P_static in the pW level.

Conclusions

In summary, we propose a series of composition-tunable GeS_xSe_1−x/SnS₂ (0 ≤ x ≤ 0.73) vdWH AATs with a h-BN/Au single bottom gate configuration for high-performance logic inverter applications. The S-poor AATs (x = 0, 0.29) exhibited rectification behaviors with DT and FNT transport mechanisms, while the S-rich AATs (x = 0.42 and 0.73) exhibited rectification behaviors with only DT transport mechanism, because adjusting the doping level of GeS_xSe_1−x through alloy engineering modulated the width of the tunneling window of the vdWH. Furthermore, all the anti-ambipolar characteristics, including ΔV_g, V_peak, I_peak, and PVR, could be dynamically modulated by adjusting S composition. Significantly, these devices exhibited a remarkable PVR of 6.6 × 10³ (x = 0.29) and the largest I_peak of 1.4 × 10⁻⁷ A (x = 0), which is attributed to the altered energy band alignment of vdWH induced by composition modulation. Therefore, the inverters fabricated using our device exhibited the highest voltage gain of 8.83 (x = 0.29) and the lowest static power consumption of 12.1 pW (x = 0.73). This work envisions composition-dependent tuning of anti-ambipolar transistors as a reliable strategy for realizing configurable multi-valued logic inverters, which offer a great opportunity for harnessing the full potential of the emerging parallel computing scheme.

Experimental methods

Material preparation

The 2D free-standing GeS_xSe_1−x nanoplates were synthesized using a two-inch quartz tube slide rail furnace (OTF-1200X-S50-SL, Hefei Kejing Materials Technology Co., Ltd). GeSe (purity 99.999%, Alfa Metal Materials Co., Ltd) and GeS (purity 99.999%, Alfa Metal Materials Co., Ltd) powders served as the growth precursors. The S composition of the GeS_xSe_1−x nanoplates was varied by adjusting the molar mass ratio of the powders. Specifically, the GeSe and GeS mixtures were placed in a quartz boat at the center of the furnace. The furnace was sealed, evacuated, and filled with Ar to expel oxygen, and set to 570 °C. Once the target temperature was reached, the heating source was quickly positioned in the center of the furnace for 4–5 minutes and then swiftly removed to the cooling zone after the growth process was complete. Moreover, the SnS₂ and h-BN nanoplates were obtained by mechanical exfoliation of the bulk crystal materials bought from Taizhou SUNANO New Energy Co., Ltd.

Device fabrication

All electrodes were patterned and deposited using the ARP-5350 positive photoresist (purchased from Taizhou SUNANO New Energy Co., Ltd), AR 300-26 developing solution (ALLRESIST GmbH, purchased from Taizhou SUNANO New Energy Co., Ltd), an Ultraviolet Maskless Lithography machine (TuoTuo Technology, UV Litho-ACA), and electron beam evaporation. First, an Au metal gate (with a thickness of 50 nm and an area of 40 µm × 40 µm) with an extended contact lead was fabricated on a 300 nm SiO₂/Si substrate. After that, the h-BN nanoplate was used to cover the entire metal gate area by the dry transfer method. To ensure a tight stack, the bottom gate structure was annealed in a 250 °C argon environment for 20 minutes to remove the organic and glue residues from the interface. Then, source-drain electrodes (10 nm Cr/40 nm Au) were prepared on the h-BN/Au bottom gate structure. Lastly, a PDMS stamp (17 mil, Gel park, bought from Shanghai Onway Technology Co., Ltd) was used to timely transfer GeS_xSe_1−x and SnS₂ nanoplates sequentially onto the designated electrode areas via a 3D transfer platform (Shanghai Onway Technology Co., Ltd), forming a vertically-stacked GeS_xSe_1−x/SnS₂ vdWH device. The entire process of device preparation was carried out in a clean room.

Characterization and electrical measurements

The OM images were captured using an optical microscope (SOPTOP BH200M, Ningbo Sunny Instruments Co., Ltd). The thicknesses and surface potential were obtained using a scanning probe microscope (Dimension FastScan from Bruker Co., Ltd) equipped with an atomic force microscope and a Kelvin probe force microscope. The Raman spectra were measured by confocal microscopy (Nost Technology Co., Ltd) using a 532 nm laser at room temperature and in an ambient atmosphere. All electrical properties of the devices were measured using a four-probe stage equipped with Keithley 2636B and Keithley 2611B and a three-probe stage equipped with a semiconductor parameter analyzer (Fs-Pro, Primarius Co., Ltd bought from Guangdong Avit Technology Co., Ltd).

Author contributions

W. Gao and T. Zheng: supervision of the entire project. Y. Long: methodology and writing-original draft. Q Deng, S Chen, Y. He, Y. Wang, Z. Zheng, N. Huo, D. Luo, X. Liu, Y. Sun, Z. Chen, and M. Yang: data curation. W. Gao, T. Zheng, and Q Deng: writing-review and editing.

Conflicts of interest

There are no conflicts to declare.

Data availability

The data supporting this article have been included as part of the Supplementary Information.

Supplementary information (SI): note S1: calculation of surface potential difference (SPD). Note S2: calculation of carrier mobility (μ) and threshold voltage (V_th). Fig. S1–30 and Table S1. See DOI: https://doi.org/10.1039/d5nh00508f.

Acknowledgements

We acknowledge the financial support from the Guangzhou Science and Technology program (No. 2025A04J1892), the National Natural Science Foundation of China (No. 62004071), the Science and Technology Program of Guangdong (No. 2024A0505040026), and the Basic and Applied Basic Research Foundation of Guangdong Province (No. 2024A1515110204).

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Footnote

† Y. L. and Q. D. contributed equally to this work.

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