Raised or recessed? Finding the optimal gate architecture for improving the static performance of graphene transistors

Abstract

As silicon CMOS technology approaches its scaling limits, graphene offers a compelling alternative as the active material channel in transistors due to its high carrier mobility and atomically thin profile, which provide strong electrostatic control and promise high-performance analog applications. However, roadblocks such as device-to-device variation, high contact resistance, poor dielectric interfaces, and non-uniform graphene quality have limited the adoption of graphene field effect transistors (GFETs). Hence, further investigations are required for mitigating these issues at a material, e.g., by improving graphene transfer, and device level, e.g., by finding an appropriate gate architecture. In this work, we directly compare two GFET structures through a controlled, side-by-side process split to evaluate the impact of gate stack architecture: raised vs. recessed buried local gate, in which both structures use hBN as the gate dielectric. Benchmarking is performed in terms of device performance and device-to-device variation. While the top-performing devices remain similar across the two proposed structures, significant statistical differences are seen in terms of device performance and yield in the two populations studied. A total of 256 identical devices from each gate architecture are electrically tested and characterized for a statistically significant comparison. The most significant difference is seen in the Dirac voltage, which is reduced from 1.2 V to 0.7 V with the recessed architecture, making it more suitable for low-power analog applications. Average hole mobility increases from 3383 cm² V⁻¹ s⁻¹ to 4794 cm² V⁻¹ s⁻¹, and device yield increases from 54.4% to 65.1%. Physical analysis, which includes spectroscopy and hysteresis measurements, indicates that these improvements are due to the proposed planarized gate architecture and reduction of interface defects. This study shows that direct statistical comparison studies of process conditions can help identify favorable process conditions to improve the manufacturability of graphene-based transistors.

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1 Introduction

Since the isolation of graphene, interest in atomically thin two-dimensional (2D) materials has surged, spurring progress in the fabrication of layered materials.¹ As sub-nanometer semiconductor technology nodes approach practical implementation through ongoing advancements in manufacturing, graphene and other 2D materials present significant opportunities due to their exceptional electrical properties, whether as monolayers or integrated with silicon in heterogeneous architectures.² Owing to its high carrier mobility, graphene stands out as a candidate for enabling terahertz (THz) and microwave communication, promising substantial improvements in data transmission speed and efficiency.^3,4 Graphene-based devices continue to show promise for high-frequency applications, including amplifiers, modulators, and resonators. Despite these advantages, achieving wafer-scale integration of graphene material-based devices remains challenging due to substantial device-to-device variability.⁵ This variability arises from factors such as transfer-induced imperfections, inconsistencies in fabrication, and process-related defects. The current research efforts aim to minimize such variability and enhance device yield, paving the way toward scalable and commercially viable graphene material-based electronics.

There are numerous fabrication methods for graphene-based devices,^6–11 with the selection of a specific approach typically depending on the intended application, targeted performance, and available fabrication resources. High-performance graphene field effect transistors (GFETs) often employ nanometer-scale channel lengths and process techniques to minimize source/drain capacitance.¹² Gate electrodes in high-frequency graphene transistors may follow a top-gated,¹³ buried,¹⁴ or trench-filled damascene design.¹⁵ Top or local gate materials can vary from gold or platinum to aluminum (Al), to reduce gate resistance, ease of integration, or to take advantage of the native oxide that is formed in the case of Al.¹⁴ Dielectric materials such as ultrathin aluminum oxide (natively grown or atomic layer deposited (ALD)), transferred hexagonal boron nitride (hBN), and other high-k materials are commonly used to enhance the performance of graphene transistors.^10,16,17 For example, graphene/hBN heterostructures have been shown to achieve hole carrier mobilities up to 60 000 cm² V⁻¹·s⁻¹.¹⁸ Large-scale (up to 6-inch) chemical vapor deposition (CVD) hBN and graphene films are available commercially and can be transferred with the same PMMA-assisted process.¹⁹ In addition, the substrate underneath the graphene channel also plays a crucial role as it significantly affects interface quality.^5,20

Despite promising progress, large-scale GFETs fabrication continues to face challenges with device-to-device variability.^21–25 Most of the studies dealing with the variability of performance indicators of large-scale fabrication, such as mobility and Dirac voltage, are based on GFETs using high-k bulk dielectrics. On the contrary, most published works of hBN as a dielectric for GFETs report only one device or a small number of devices.^26–33 One large-scale paper by Fukamachi et al., in 2023,³⁴ presented an integrated electrochemical hBN transfer method to create globally back-gate graphene field-effect transistor arrays via a lithography process. The hBN is used as the dielectric and was grown through a chemical vapor deposition (CVD) process on an iron-nickel alloy foil and had a thickness of about 5 nm. GFETs with SiO₂ as the dielectric were simultaneously fabricated as a control group. The maximum hole mobility increased from 5384 cm² V⁻¹ s⁻¹ to 7074 cm² V⁻¹ s⁻¹, and ultimately to 10 219 cm² V⁻¹ s⁻¹ when another layer of optimized hBN was used to encapsulate the devices. On the other hand, significant variability can be observed in the results of 62 tested devices, with hole mobilities as low as 2000 cm² V⁻¹ s⁻¹ in the optimized hBN encapsulated process. A second report by Martini et al., in 2023, presented a scalable process by growing a 10 nm nanocrystalline hBN film via an ion beam-assisted physical vapor deposition on a 1 cm × 1 cm. Transfer length method (TLM) measurements of PMMA-transferred graphene resulted in a carrier mobility of 7500 ± 850 cm² V⁻¹ s⁻¹.³⁵ A 2025 report by Zheng et al. shows improved top-gated GFET reliability with the use of hBN as the dielectric with minimal hysteresis shift even after >2000 sweeps.³⁶

It is essential to investigate the variability of graphene-based field-effect transistors and identify the underlying sources of variation. Although fabrication approaches for graphene devices often differ, the choice of process significantly influences device performance, application scope, and resource requirements. Prior studies generally have shown improved GFET performance or reduce variability when evaluating disparate device structures, materials, or fabrication flows, but focus only on “hero” devices that do not reflect broader statistical trends. This work employs a comparative process split to study the effect of the gate architecture on device performance, yield, and variability of GFETS using hBN as a dielectric. An Al/hBN/graphene gate stack is used as it presents advantages of simple integration and lattice match between the hBN and graphene, and has been shown to result in improved device performance.¹⁸ The choice of gate architecture (i.e., global back gate, raised local bottom gate, recessed local bottom gate, or top gate) can depend on the final application of the GFET, but also on the available resources and economically driven decision. In particular, this process split looks at the effect of local-back (a) raised Al gate versus (b) planarized and recessed Al gate. A local-back gate architecture has been chosen as it reduces the exposure of the graphene channel to subsequent processing steps and potentially preserves its quality. In addition, the local-back gate architecture is conducive to the fabrication of sensors which can be interrogated independently or as arrays.³⁷ Several studies using the local-back raised gate architecture have reported high performance of representative transistors but have also indicated that this may not be the ideal architecture due to the expected sharp transition as the graphene goes over the gate, as well as the effects of the sidewall roughness, and the potential air gap of the draping graphene.^38,39 As such, a planarized recessed architecture could present some advantages in device performance and variability. Finally, although the local-back raised gate architecture is simpler to implement as it does not require chemical and mechanical planarization (CMP) equipment, the recessed architecture can be easily integrated in the back-end-of-line (BEOL) of CMOS processes, and it may be proven to be a worthy investment in large volume manufacturing if clear performance improvements can be observed.

This report starts by briefly presenting the theoretical aspects of the different materials studied, as well as a presentation of a novel methodology employed to extract individual device mobility and, for the first time, contact resistance of a large number of individual transistors. Next, the fabrication splits and measurement methodologies are presented and discussed. Then, the physical and electrical results of the fabricated devices are presented. A total of 256 identical devices from each group are electrically tested and characterized for a statistically significant comparison. Finally, a discussion of the results is carried out, comparing the results of this experiment while providing insights and recommendations to improve GFET performance and reduce variability.

2 Theory

Graphene is a two-dimensional material composed of carbon atoms arranged in a hexagonal lattice. It exhibits high theoretical carrier mobility of up to 250 000 cm² V⁻¹ s⁻¹,⁴⁰ making it well-suited for high-speed GFETs that use graphene as the active channel material. In contrast to conventional silicon MOSFETs, where the channel lies within the crystalline silicon substrate, GFETs leverage the atomically thin, surface-level conduction of graphene to enable superior charge transport characteristics. Previous graphene transistors have frequently utilized atomic layer deposited (ALD) aluminum oxide (Al₂O₃) as the gate dielectric, chosen over silicon dioxide (SiO₂) for its higher dielectric constant of 9.8 versus 3.9, respectively,³⁷ as well as ALD's ability to deposit single atomic layer thick dielectric layers per cycle. Hexagonal boron nitride (hBN), by comparison, has a relative dielectric constant of approximately 4,⁴¹ similar to that of SiO₂. Oxide dielectrics like Al₂O₃ and SiO₂ are known to introduce trapped charges and surface roughness, which increase unintentional doping in the graphene channel.⁴² This leads to shifts in the Dirac point, reflecting changes in the Fermi level due to altered carrier concentrations. Such variability undermines electrostatic control and contributes to significant device-to-device variation.^41,43 In contrast, the atomically flat and chemically inert nature of hBN minimizes charge traps and dielectric-induced perturbations, thereby stabilizing the Dirac voltage and enhancing device uniformity.^44,45 As a result, the use of hBN has been correlated with improved yield and more consistent electrostatic performance in GFET fabrication.⁴⁶

While the contact resistance between bulk metal and a two-dimensional graphene channel is often extracted using the transfer length method (TLM), this study uses an alternative approach to measure this parameter for each individual transistor. TLMs are unable to capture localized variations in contact resistance that arise from van der Waals-dominated interactions at the graphene–metal interface. These interactions can vary significantly across a wafer, and imperfections at the contact region further exacerbate this variability.⁴⁷ To address this, we extract contact resistance by analyzing the transfer characteristics (I_DV_G) of individual transistors under varying drain biases, which has been proposed and published by Pachecho-Sanchez et al.⁴⁸ The contact resistance extraction method used in this study is based on a unipolar drain current I_D model of GFETs considering mobility degradation effects.⁴⁸ The methodology assumes that a weak V_DS-dependence of µ can be considered for two transfer curves at two close values of V_DS. Hence, the relation between I_D1 and I_D2, obtained at V_DS1 = 50 mV and V_DS1 = 100 mV, respectively, can be written as in eqn (1), where V₀ is a voltage related to a residual charge, V_GCO = V_GS − V_Dirac − V_DS/2-with V_Dirac = V_{GS|min ID}-, and R_C is the contact resistance. The value of Dirac voltage is extracted directly from the I_DV_G transfer plots as the value of V_GS when the drain current is minimum. By solving eqn (1) for R_C at |V_GS| >> |V_Dirac|, a straightforward expression shown in eqn (2) can be used for calculating this device parameter.⁴⁸

By following the same underlying transport model, eqn (3) can be used for obtaining a value for µ of a GFET without the influence of R_C, provided the oxide capacitance per unit area C_ox and the transconductance parameter β. The value of C_ox can be measured to avoid any uncertainties related to gate dielectric thickness and composition, as shown in the Methods section. The transconductance parameter β is equal to µ₀C_oxW/L, where µ₀ is the bias-independent low-field mobility, C_ox is the oxide capacitance per unit area, and W and L are the width and length of the device and is extracted experimentally from a modified Y-function method presented in,⁴⁹ i.e., from the slope of the plot of Y² versus V_GCO², where Y = I_D/g_m^1/2, and g_m = δI_D/δV_GS. An example of the use of this methodology to extract mobility is shown in the SI.

3 Materials and methods

3.1 Device fabrication

Two 4-inch silicon (100) wafers are used as the substrates for the fabrication of the different GFET structures analyzed. As shown in Fig. 1 and 2, device fabrication starts with an RCA clean prior to thermally growing 300 nm of SiO₂ at 1000 °C in an oxygen atmosphere. Then, the wafer with the recessed gate (b in Fig. 1 and 2) undergoes a partial 100 nm dry etch into the SiO₂ to define the gate electrode patterns and other dense rectangular CMP tiles. Then, 150 nm of aluminum is sputtered onto both wafers. A chemical-mechanical-planarization (CMP) process is then carried out on the recessed gate wafer to remove the excessive aluminum in the field area, leaving only aluminum in the previously etched trench region, forming the recessed gate. The gate electrode for the raised gate structure (a in Fig. 1 and 2) is then patterned and etched through a wet Al etch. The wafers are then processed together through the remainder of the steps. Next, hBN is transferred onto the raised and the recessed aluminum electrodes, respectively, using CVD-grown hBN on copper foil (6-inch × 6-inch), commercially purchased from Grolltex, Inc. in 2023. An area of 2″ by 2″ was cut out and transferred onto the surface of the wafer via a PMMA-assisted process that was identical to our graphene transfer technique detailed in prior work.³⁷ The graphene transfer process follows a previously reported PMMA-assisted technique with CVD grown material from Graphenea, Inc.³⁷ Graphene is then patterned through standard photolithography and etched by oxygen plasma for 45 seconds. The resist was removed by an overnight acetone soak and rinsed with DI water. Lastly, source drain electrodes of Ni/Au (5/95 nm) were thermally evaporated and patterned with a lift-off approach.

Fig. 1 Side-by-side process split for graphene on (a) hBN/raised Al gate, and (b) hBN/recessed Al gate.

Fig. 2 Process flow schematic for the proposed process split of (a) raised and (b) recessed Al gate with monolayer hBN dielectric.

3.2 Characterization and test methods

A scanning electron microscope (SEM) was used to inspect the fabricated graphene channels for any discontinuities and voids. The Tescan Mira3 Scanning Electron Microscope with a field-emission electron gun was utilized at the RIT Nanoimaging Laboratory to obtain all the shown SEM images at different tilt angles.

White light interferometry was used to observe the surface of the fabricated structures. The samples were coated with a 5 nm layer of Au in order to provide a reflective surface for accurate measurements. A Veeco Wyko NT110 was used to obtain 3D and 2D profiles at a 20× magnification. Phase shift mode was used to measure the expected dimensions accurately.

A Veeco Dimension 3000 AFM Atomic force microscope was used to inspect the active area of the Al gate electrode for surface roughness and topography while providing comparative results demonstrating that a CMP process reduces the topography of Al electrodes.

Raman spectroscopy was carried out with a JY Horiba Labram-HR Raman Spectroscope for further analysis on the quality of post-processing transferred graphene at multiple points of interest within the device's active area. A red 633 nm laser was used for the spectroscopy measurement with a measurement accumulation time of 30 seconds per measured data point.

Electrical testing was done with a semi-automated RK probe card station with an HP-4156 semiconductor parameter analyzer. Transfer characteristics curves were used to extract individual device Key Performance Metrics (KPMs) of Dirac voltage, mobility, and contact resistance as described in the Theory section.^48,49 A total of 256 devices, located within a rectangular area of 50 mm × 25 mm in the center of each 4-inch wafer, were tested. All these devices have a gate size of W = 20 µm and L = 10 µm.

The capacitor structures formed by the channel-to-gate overlap of larger GFETs were used for capacitance–voltage (C–V) measurements. A Keithley 4200A-SCS Parameter Analyzer at 100 kHz, 30 V-rms, as shown in the SI, was used to measure the value of C_ox for the extraction of mobility. Dielectric breakdown voltage to validate the C_ox values obtained was measured by increasing V_GS in steps of 20 mV, while keeping V_D and V_S at 0 V (see SI). Hysteresis sweeps, including 0 V-pulsed and 1 V-pulsed hysteresis sweeps (where V_GS is set to 0 V or 1 V prior to each measurement data collection), were used to evaluate interface traps of representative devices. More information on the hysteresis sweep method is presented in the SI.⁵⁰

Following the electrical testing, statistical analysis was conducted using JMP 19™ (JMP Statistical Discovery LLC, SAS Institute Inc) on Dirac voltage, mobility, and contact resistance. For each metric, the two groupings of data (raised Al gate and recessed Al gate) were compared utilizing an independent two-sample t-test. The t-test compares the average for each individual group as well as a pooled standard deviation between two normally distributed groups. The resultant p-value is then compared to an assumed alpha risk of 0.05 for a 95% confidence in the results.

4 Results

A schematic cross-section of the different structures under study in this work is shown in Fig. 3, showing a representation of local-back (a) raised and (b) recessed Al/hBN/graphene devices. The hBN dielectric is represented as purple and orange, while the graphene is represented as black. The gate electrode is designed as not to overlap the source and drain electrodes with a symmetrical ungated graphene access area with a length and width of 1 µm by 20 µm per side, respectively. The schematic representations are not to scale, as one would expect the raised aluminum gate not to be entirely vertical and have some isotropy, as well as the possibility that the hBN and graphene would drape over the raised gate and create an air gap.³⁹

Fig. 3 Device cross-section for (a) raised and (b) recessed Al gate with hBN gate dielectric.

Fig. 4 shows a side-by-side scanning electron microscope (SEM) image of a raised aluminum gate device (Fig. 4(a)) with a gate length of 10 µm as defined by the aluminum and a gate width of 20 µm as defined by the graphene, and a recessed aluminum gate device (Fig. 4(b)) of similar dimensions. As seen in the close-up SEM of Fig. 4(c), the step created by the raised Al gate is clearly visible as the graphene drapes over the 100 nm edge. Conversely, this step is not as visible in the recessed Al gate device shown in Fig. 4(d), but a transition region can still be seen as the graphene goes over the Al gate. Fig. S1 shows three-dimensional white light interferometry scans of the surface of representative raised and recessed devices. As seen in the 2D profile in Fig. S2, the transition over the raised aluminum gate is measured to be about 110 nm, whereas the recessed aluminum gate step is under 3 nm. It is also observed from Fig. S2 that the CMP tiles provide a uniform surface within the features of matched dimensions and show the effectiveness of the CMP process. In contrast, dishing is observed in larger structures; subsequently, additional optimization of the CMP process may be necessary to reduce the observed variation further.

Fig. 4 SEMs of raised (a and c) and recessed (b and d) Al gate devices with monolayer hBN gate dielectric.

Atomic force microscopy (AFM) analysis was carried out to understand (1) the surface roughness near the step/transition onto the gate electrode and (2) the roughness on top of the gate electrode itself. The average surface roughness (R_a) on the top of the electrode for the raised Al gate shown in Fig. 5(a) was 1.3 nm, while in Fig. 5(b), the recessed Al gate R_a was 0.566 nm, approximately half of its raised Al gate counterpart.

Fig. 5 AFM scan of (a) graphene on active area gate electrode hBN/raised Al gate with Ra of 1.3 nm, (b) graphene on active area gate electrode with hBN/recessed Al gate with Ra of 0.566 nm.

Raman spectroscopy was collected from the graphene film on top of SiO₂, and on top of the hBN dielectric on a raised and a recessed aluminum gate. As shown in Fig. 6, the qualitative spectra of the three structures are similar, which indicates that the quality of the graphene is not significantly different between the groups and does not seem to be influenced in great measure by the observed substrate smoothness.

Fig. 6 Raman spectra of graphene on SiO₂, and on hBN on a raised and recessed aluminum gate, as indicated in the labels.

Fig. 7(a) and (b) illustrate the I_DV_G transfer characteristics overlay of GFETs with a gate length of 10 µm and a gate width of 20 µm at V_DS = 0.1 V for raised Al gate and recessed Al gate devices, respectively. The transfer curves shown in the plots are normalized to the device gate width. Non-working devices, as well as the top and bottom 5% have been removed for all device structures in this investigation. Raw data, including all devices, is presented in Fig. S3 in the SI. The overlaid I_DV_G plots include both red and green transfer curves to illustrate the average and hero device performance of each group, respectively.

Fig. 7 Transfer characteristics overlay at V_DS = 0.1 V of fabricated graphene FETs with a gate length of 10 µm. Drain current is normalized to its width of 20 µm for (a) raised and (b) recessed Al gate with monolayer hBN gate dielectric.

As seen in the green curves of Fig. 7 and the values on the insets, the performance of the hero devices is similar between the two groups in terms of maximum current drive and extracted hole mobility. In contrast, there is a clear difference in the variability of the transfer curves between the raised Al gate and the recessed Al gate. When looking only at current drive and the mobility of the hero devices, one may infer that they behave similarly with similar current drive at V_GS = −1 V, V_DS = 0.1 V of 7 µA µm⁻¹ and 7.6 µA µm⁻¹. However, the average value increased significantly from 4.8 µA µm⁻¹ to 6.6 µA µm⁻¹, while the variation is also reduced in the recessed Al gate structures. In addition, the Dirac voltage of the recessed Al gate process is significantly lower in magnitude, from an average of 1.2 V to 0.7 V, and shows much less variability.

5 Discussion

Fig. 8 shows a statistical analysis of the KPMs in box plots of the working devices of each group. Out of 256 tested devices in each group, only 137 and 175 devices work properly for (a) raised and (b) recessed Al gate structures, respectively. These numbers represented a yield of 53.5% for the raised process and of 68.5% for the recessed gate structure, which represents an improvement over the 18% yield that was previously presented for a raised Al gate process with a 15 nm Al₂O₃ gate dielectric.³⁷ Fig. S3 presents the distribution of working devices in 7 mm × 7 mm dies of raised and recessed hBN devices. The distribution of working devices does not present a clear pattern, but the overall yield numbers are similar to those observed over the larger tested area of 50 mm × 25 mm. The improvement in yield between the processes with Al₂O₃ to hBN dielectric is related to the inherently better matching properties between hBN and graphene, which favor the adhesion on the substrate during fabrication.^35,51 On the other hand, the adhesion properties of Al₂O₃ and graphene need to be carefully designed for optimal results.⁵²

Fig. 8 Box and whisker illustration of device performance and variation of working raised and recessed Al gate devices determined by (a) Dirac voltage, (b) mobility, and (c) contact resistance.

5.1 Dirac voltage

As seen in Fig. 8(a), the recessed Al gate structure significantly reduces the Dirac voltage to an average of 0.7 V as opposed to 1.2 V for the raised Al gate. A t-test comparison of the two normal distributions showed a p-value of <0.0001. This indicates that there is a significant difference in the Dirac voltage between a raised and recessed Al gate structure. This significant reduction in Dirac voltage of the recessed Al gate structures is related to both the smoother transition step from the field to the gate structure, as seen in the SEM pictures, and the smoother surface of the gate area, measured via AFM. As shown in the results section, the transition step is reduced from 100 nm to just a few nanometer, and the surface roughness Ra of the gate region of the raised Al gate process is 1.3 nm, while the recessed Al gate R_a is 0.566 nm. The draped area of the raised Al gate structures and its rougher surface, which shows ripples and other derivations from a perfectly flat structure, can lead to electron–hole puddles,⁵³ strain-induced defects,⁵⁴ and adsorption of molecules and impurities, all of which led to Dirac point shifts.⁵⁵

When integrating atomically thin gate dielectrics such as hBN, aggressive scaling without compromising device performance may be achieved with its superior electrostatic control in graphene FETs, which is attributed to its high breakdown strength, lattice matching, and minimal interface traps.³⁵ Both the dielectric material and its thickness affect shifts in the Dirac voltage. Monolayer hBN provides an atomically flat and inert surface that reduces charge inhomogeneity and results in a more consistent Dirac voltage when compared to other dielectric materials; in addition, the thickness of the dielectric layer affects the electrostatics in the gated channel region, and thus, the electrical conditions to set a charge neutrality point (Dirac voltage).³⁵ The consistent standard deviation of 13-16% suggests that the improvement is mainly driven by material and structural changes, not outlier behavior. Achieving a Dirac point near 0 V is crucial for low-power non-linear analog applications, and this trend confirms the effectiveness of the hBN dielectric and recessed gate architecture.⁵⁶

5.2 Mobility

The mobility for each device can be calculated as described in eqn (3). The value used for C_ox = 5.5 × 10⁻³ F m⁻² was measured on large capacitor test structures as opposed to individual devices to avoid parasitic capacitances or other parameters already factored with the proposed extraction methods. An extended discussion of the C_ox measurement and calculation is presented in the SI, with C–V measurements of large area Al-dielectric-graphene capacitors shown in Fig. S1, dielectric breakdown voltage measurements in Fig. S4, and an estimation of the dielectric film composition in Fig. S5. The fact that the capacitance per unit area (F m⁻²) is consistent across each of the large area capacitors tested and the breakdown voltage is >3 V, indicates that a native AlO_x dielectric is present between the monolayer hBN and the gate aluminum electrode.³⁹

As seen in Fig. 8(b), the value of hole carrier mobility shows an improvement in the recessed Al gate structures. Although the Raman spectra shown in Fig. 6 did not indicate much differences in the graphene quality, the observable improvement in hole carrier mobility is both in terms of magnitude, which increases by 42% from 3383 V s cm⁻² to 4794 V s cm⁻², and variability, which is reduced by nearly 50%, from 36% to 18% standard deviation for the normally distributed populations of data. Performing the statistical analysis detailed in Section 3.2, a p-value of <0.0001 was produced, supporting that there is a statistically significant change in mobility with the recessed gate architecture. These improvements are supported by the smoother transition over the gate structure and the smoother surface roughness of the recessed Al gate process. In comparison, a much smoother surface provides a more pristine graphene film, especially when in contact with hBN in both the field and channel area, serving as the gate oxide, providing improved lattice-matching qualities. These improvements in surface topology lead to less scattering of the carriers and improved mobility.⁵⁷

5.3 Contact resistance

Fig. 8(c) shows the box plots of the contact resistance values of both groups. The contact resistance mean and percent standard deviation remain comparable between the two device structures, as contact materials and processes are identical between the two groups. The size of the measured contact area between the Ti/Au and graphene over hBN is 12 µm long by 20 µm wide. As mentioned before, the role of the hBN as an underlayer in this contact structure is to provide a matched lattice layer for the graphene as opposed to Al₂O₃ or SiO₂, which may introduce trapped charges and surface roughness.⁴² The mean contact resistance of the raised Al gate is 0.75 kΩ, which is only slightly higher than 0.67 kΩ for recessed Al gates. The relatively large percent standard deviation values are similar at 42% and 37%, respectively. Upon comparing the groups, however, a t-test p-value of 0.025 is observed, indicating there is a significant difference between the two device structures, albeit less so than for the Dirac voltage or mobility. This difference could be attributed to the presence of random defects rather than process or materials differences, and further investigation is necessary. In contrast, the contact resistance drops significantly when moving from Al₂O₃ to hBN as the contact underlayer dielectric, as shown in Fig. S11 in the SI. When compared to data presented previously by our group in,³⁷ substituting hBN in an identical Al₂O₃/raised gate process improves the contact resistance compared to an average of 2.59 kΩ measured in 37 devices. In addition, the standard deviation of the Al₂O₃/raised gate was 78%, likely due to poor interfacial quality, and increased roughness.³⁷

5.4 Hysteresis

Hysteresis sweeps of GFETs with non-pulsed and pulsed (based 0 V) bias are shown in Fig. 9(a) and (b) for a raised Al gate device, and in Fig. 9(c) and (d) for a recessed Al gate device. The purpose of the pulsed testing is to reduce the impact of traps, while under the assumption that the time constant associated with trap charging is greater than the pulse width.⁵⁸ A hysteresis window is reported next as the difference between V_Dirac at forward and backward V_GS sweeps. As seen in Fig. 9(a) and (b), the hysteresis window is 240 mV for GFET with a raised Al gate structure without pulsing, while a 30 mV hysteresis window is seen when pulse testing is applied. Additionally, when applying a 1 V pulse, the hysteresis window is further reduced to 15 mV as seen in Fig. S8 in the SI. These results indicate the presence of interface traps, which would lead to device variation during test.⁵⁰ As seen in Fig. 9(c) and (d), the hysteresis window is about 90 mV for GFET with the recessed Al gate structure without pulsing, while a 50 mV hysteresis window is seen when pulse testing is applied. The smaller 40 mV difference between the pulse and no-pulse method indicates that although interface traps exist, these are much less than with the raised Al topology. Although these results indicate that the step architecture and surface roughness of the raised aluminum gate topology lead to interface traps and increased variation, the effect of the different channel electrostatics cannot be ignored, and further studies are necessary.

Fig. 9 Hysteresis curves for raised (a) and (b), and recessed (c) and (d) Al gate GFETs with a no-pulse method (a) and (c), and a 0 V-pulse method (b) and (d).

In summary, the planarization process presented in this paper provides a statistical improvement in the performance and variability of graphene transistors in terms of the Dirac point and mobility when compared to a raised gate architecture. The reason for these improvements is related to the planarization process and the smoother transition and gate surface. Hysteresis measurements indicate that the level of traps in the hBN/graphene interface is much lower in the recessed process, which accounts for the reduced device-to-device variation. In addition, the non-homogeneous features of the raised gate architecture (i.e., unpolished aluminum, graphene draping) play a significant role in the mobility degradation and in the minimum carrier density affecting both the drain current and Dirac voltage.³⁸ When compared to other dielectrics, such as Al₂O₃,³⁷ hBN also offers advantages in terms of yield and contact resistance when used in a local-back gate process. In addition, the observed parameter variability is much reduced with the use of hBN as a dielectric due to better material compatibility during processing, which, along with other process improvement and considerations, could lead to the needed improvement in yield and reliability.^34,36,59

Finally, the presented results are compared to other published work that includes similar statistical data. Martini et al., 2023,³⁵ presented a scatter plot distribution of hole mobility versus V_Dirac measured on >100 TLM-like structures of graphene on hBN continuous films grown via ion beam-assisted physical vapor deposition directly on 300 nm-SiO₂ on Si substrates. The V_Dirac measurements have been transformed into the vertical electric field (E_field) by normalizing to the reported dielectric thickness in all cases. Martini et al. used a back-gate configuration so that the graphene channel had no topology. As such, this flat structure serves as a best-case scenario for our intended recessed Al gate architecture. As seen in Fig. 10, the hole mobility numbers reported by Martini et al. are slightly higher than ours in the recessed architecture, which corroborates the fact that our channels are not entirely flat and would benefit from improvements in the transition step between the field and gate regions. In addition, the E_field at V_Dirac is comparable between the flat and the recessed architecture. Moreover, this data corroborates that both the flat and recessed architecture improves the performance in terms of hole mobility and the E_field at V_Dirac when compared to the raised architecture.

Fig. 10 Scatter plot of mobility vs. E_field at V_Dirac comparing our study to Martini et al., 2023.³⁵ Shaded color areas are added to guide the eye and do not represent any statistical measurements.

6 Conclusion

While prior studies have aimed to improve GFET performance or reduce variability, most work has typically been done in evaluating disparate device structures, materials, or fabrication flows, and focusing only on “hero” devices that do not reflect broader statistical trends. In contrast, our work systematically integrates monolayer hBN as a gate dielectric and directly compares a raised versus a CMP-recessed aluminum gate within a unified fabrication platform, enabling direct, controlled comparisons across design variations. By analyzing complete device distributions rather than peak values alone, this study offers critical insights into how gate topology influences reproducibility. This work statistically demonstrates that the recessed Al gate topology not only enhances key performance metrics, including Dirac voltage and hole mobility, but also reduces device-to-device variation and increases yield. Due to the smoother surface, channel to gate transition, and lower number of interface traps, the recessed Al gate topology, as opposed to a raised gate, decreases the standard deviation of the extracted graphene hole mobility from 36% to 18%, while improving device yield from 54.4% to 65.1%. In addition, the Dirac point shifted closer to 0 V (from ∼1.2 V to 0.7 V), and the contact resistance was reduced from 0.75 kΩ to 0.67 kΩ. Ultimately, our findings establish practical design and process guidelines for realizing scalable, high-performance graphene electronics to bridge gaps between isolated breakthroughs and manufacturable, wafer-level technologies. The observed consistency suggests that a recessed Al gate structure with a hBN dielectric is a strong candidate for an optimal platform of scalable and high-performance GFET fabrication.

Author contributions

Conceptualization: T-J. Huang, I. Puchades. Data curation: T-J. Huang, A. Spencer, L. Ingraham. Formal analysis: T-J. Huang, A. Spencer, L. Ingraham, A. Pacheco, I. Puchades. Funding acquisition: A. Pacheco, I. Puchades. Investigation: T-J. Huang, L. Ingraham, A. Pacheco, I. Puchades. Methodology: T-J. Huang, A. Spencer, Project administration: I. Puchades. Resources: I. Puchades. Software: T-J. Huang, A. Spencer, L. Ingraham. Supervision: T-J. Huang, I. Puchades. Validation: L. Ingraham, A. Pacheco, I. Puchades. Visualization: T-J. Huang, A. Spencer, L. Ingraham, A. Pacheco, I. Puchades. Writing – original draft: T-J. Huang, A. Spencer. Writing – review & editing: L. Ingraham, A. Pacheco, I. Puchades.

Conflicts of interest

There are no conflicts of interest to declare.

Data availability

Data for this article are available at the Rochester Institute of Technology repository https://repository.rit.edu/data/3/ at [https://doi.org/10.58044/kgcoe-hy06]. The following data files are available.

IDVG of fabricated raised and recessed graphene transistors sorted by gate length: IDVG_Raised_GFETs.csv; IDVG_Recessed_GFETs.csv.

Calculated mobility sorted by gate type: GFET_Rsd_Rec_Mobility.csv.

Calculated contact resistance by gate type: GFET_Rsd_Rec_Contact Resistance.csv.

Measured VDirac by gate type: GFET_Rsd_Rec_Dirac.csv.

Mobility vs. Efield at VDirac sorted by gate type and compared to Martini et al. 2023: GFET_Rsd_Rec_u vs. Vdirac.csv.

Supplementary information (SI): 3D and 2D white-light interferometry of typical fabricated devices. ID–VG plots of all tested devices. Mobility extraction example. CV measurements of test structues. Gate dielectric breakdown voltage measurements. C_ox discussion. Hysteresis pulse test description and measurements. Heatmaps of key performance parameters and yield. Contact resistance comparison between hBN and Al₂O₃ as underlaying films. See DOI: https://doi.org/10.1039/d5na01086a.

Acknowledgements

This work was performed in part at the Cornell NanoScale Facility, a member of the National Nanotechnology Coordinated Infrastructure (NNCI), which is supported by the National Science Foundation (NSF) (Grant NNCI-2025233). T-J. Huang received funding from RIT's Kate Gleason College of Engineering. L. Ingraham acknowledges funding from NSF Award No. 2329784, U.S.-Japan University Partnership for Workforce Advancement and Research & Development in Semiconductors (UPWARDS) for the Future. A. Pacheco thanks the support of the research project CNS2023-143727 RECAMBIO funded by MCIN/AEI/10.13039/501100011033.

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