Open Access Article
Aedan Gibson
ab,
Canjie Wangab,
Urasawadee Amornkitbamrungab,
Yongjae Inab,
Seokhoon Hanbc,
Hyeon Jun Jeongab,
Hyun Suk Jung
de and
Hyunjung Shin
*abe
aDepartment of Energy Science, Sungkyunkwan University, Suwon 440-746, Republic of Korea. E-mail: hshin@skku.edu
bNature Inspired Materials Processing Research Center, Sungkyunkwan University, Suwon 440-746, Republic of Korea
cDepartment of Future Energy Engineering, Sungkyunkwan University, Suwon 440-746, Republic of Korea
dSchool of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon 440-746, Republic of Korea
eSKKU Institute of Energy Science and Technology (SIEST), Sungkyunkwan University, Suwon 440-746, Republic of Korea
First published on 9th May 2026
Perovskite solar cells (PSCs) have managed to achieve certified power conversion efficiencies (PCEs) of 27.3%, yet losses during device upscaling remain a major roadblock in the path to commercialization. Compared with mature photovoltaic technologies such as crystalline Si and thin-film CdTe or CIGS, PSCs show a more pronounced performance loss when transitioning from small lab-scale cells to larger modules. These losses are commonly attributed to increasing series resistance (Rs) in transparent conducting oxide (TCO) substrates and challenges in maintaining film uniformity over larger areas. Here, inverted PSCs were systematically fabricated and evaluated across active areas of 0.06, 0.25, and 1 cm2 without altering the device architecture, enabling isolation of intrinsic scaling losses. Atomic layer deposition (ALD) was employed to deposit an ultrathin nickel oxide (NiO) hole transport layer (HTL), allowing precise thickness control and highly conformal coverage compared to solution-processed nanoparticle (NP) and sol–gel NiO films. Thin film and interfacial characterization demonstrate superior coverage, electrical homogeneity, and surface wettability for ALD-NiO, resulting in an improved platform for perovskite growth. Devices incorporating ALD-NiO exhibit the smallest efficiency loss upon scaling, with PCE depreciation minimized to approximately 2% when increasing the active area from 0.06 to 1 cm2 (19.8% to 17.6%). While the open-circuit voltage (VOC) and short-circuit current density (JSC) remained stable, the PCE loss was primarily driven by a decrease in fill factor (FF). This work identifies ALD-deposited NiO as an effective, dopant-free HTL for mitigating scaling-induced losses in inverted PSCs and provides mechanistic insight into the interplay between interfacial conformity, perovskite microstructure, and scale-related resistive limitations. Overall, this work advances understanding of scaling-induced performance losses in PSCs and underscores the potential of ALD-enabled interface control for future large-area and tandem photovoltaic applications.
Broader contextSolar energy is central to global efforts to mitigate climate change and secure affordable, low-carbon electricity at the scale required for a sustainable energy transition. Perovskite solar cells have emerged as a promising next-generation photovoltaic technology due to their high efficiency and low manufacturing costs. However, a critical barrier to their real-world deployment is that devices performing exceptionally well at laboratory scale often lose efficiency when fabricated over larger areas, limiting their industrial relevance. This study addresses this scalability challenge by identifying how interfacial quality and electrical uniformity govern performance losses in larger-area devices. By applying a vapour-phase deposition technique to form ultrathin, uniform charge-transport layers, we demonstrate a practical pathway to significantly reduce efficiency losses during upscaling. Our findings provide fundamental insight into why scaling losses occur and show how they can be mitigated without relying on complex chemical additives or fragile interfacial treatments. This work highlights the importance of scalable interface engineering for translating laboratory advances into commercially viable solar technologies, supporting the broader goal of accelerating the global adoption of renewable energy. |
Despite rapid progress, commercialization remains constrained by three persistent challenges: long-term stability, lead (Pb) toxicity, and large-area upscaling. While considerable research has focused on mitigating stability and toxicity concerns, the issue of scalability remains comparatively underexplored. All PV technologies experience decreased PCE when transitioning from small-area cells to large-area modules.14–17 However, PSCs suffer a particularly pronounced drop, historically showing ≈10% reductions in PCE from champion small devices to modules greater than 10 cm2 in area.9,15,18
As illustrated in Fig. 1, this decline is far steeper than in mature c-Si, CIGS, or CdTe devices. This discrepancy clearly indicates that scalability remains one of the most significant obstacles to the commercial adoption of PSCs. The sources of these losses are multifaceted. A major contributor is the linear increase in series resistance (Rs) with increasing device area, stemming from the sheet resistance of the transparent conducting oxide (TCO) substrate.19,20
![]() | ||
| Fig. 1 Comparative power conversion efficiency (PCE) decline of c-Si (blue), perovskite (red stars), CIGS (green), and CdTe (orange) devices with increasing area. The ‘TARGET’ line uses the more favourable c-Si scaling trend to project performance that commercially viable perovskite modules should ideally achieve. Data from Solar Cell Efficiency Tables (Version 66).18 | ||
Equally important are non-uniformities and morphological defects that arise when producing large-area thin-films; including pinholes/cracks, increased grain boundary (GB) density and reduced film homogeneity. These issues collectively diminish the short-circuit current density (JSC) and, more notably, the fill factor (FF).21,22 Since FF is typically the most sensitive parameter to resistive and interfacial losses in PSCs, mitigating FF decline is essential for achieving favourable scaling behaviour.
In this context, inverted (p-i-n) PSCs (iPSCs) have gained significant attention. They exhibit improved operational stability, low hysteresis, compatibility with flexible substrates, and integration potential for tandem devices.11–13,23–27 In iPSCs, the hole-transport layer (HTL) plays a defining role in determining perovskite film formation, interface quality, and charge extraction efficiency due to its location directly beneath the absorber layer. Nickel oxide (NiO) has emerged as a widely adopted HTL due to its suitable energy alignment with perovskite, strong chemical, thermal and light stability, and compatibility with low-temperature, large-area processing.28–32 Nonetheless, solution-processed NiO films often exhibit low conductivity, interfacial defects, and non-uniform coverage—limitations that become markedly more severe during device upscaling.14,33,34 To overcome these challenges, this work employs atomic layer deposition (ALD) to fabricate the NiO HTL. ALD is a vapour-phase deposition technique that enables atomic-scale thickness control and exceptional conformality through sequential, self-limiting surface-reaction chemistry (Fig. 2). These characteristics are advantageous for PSC fabrication, as HTL thickness and uniformity strongly influence FF and overall device performance.22,35 In particular, ALD's ability to conformally coat high-aspect ratio features is critical for ensuring a uniform NiO layer across FTO substrates, mitigating shunting paths and local non-uniformities that can significantly hinder device performance during upscaling. Prior studies have demonstrated high small-area efficiencies using ALD-NiO iPSCs,30,36–39 yet the implications of ALD-NiO for device upscaling have not been systematically examined.
Here, we present a controlled study investigating the upscaling behaviour of ALD-NiO iPSCs compared to more traditional solution processed sol–gel and nanoparticle (NP)-NiO iPSCs across active areas ranging from 0.06 to 1 cm2. The device architecture and processing conditions are intentionally kept constant, enabling a direct evaluation of scaling effects. The HTL deposition method is the sole variable factor in the fabrication process, which allows for a clear analysis and comparison of ALD, sol–gel, and NP-deposited NiO layer suitability for upscaling iPSCs. Furthermore, unlike many reports that incorporate interlayers, dopants, surface passivation layers, or self-assembled monolayers (SAMs), this work isolates the intrinsic benefits and drawbacks of each HTL deposition method without additional performance-enhancing modifications. As such, the devices fabricated here are not intended to challenge current state-of-the-art PSCs but rather serve as a foundation for understanding the potential for ALD as a HTL deposition strategy to translate the high performance of today's champion iPSCs to larger areas more suitable for commercialization. The focus is intentionally placed on relative performance losses, identifying practical strategies for scalable fabrication rather than pursuing record efficiencies.
Our results demonstrate that ALD-NiO acts as a superior platform for triple-cation perovskite growth compared to solution-processed NiO-HTLs, resulting in improved film uniformity and reduced defect density. Device performance analysis reveals that FF remains the dominant loss mechanism upon increasing device area. To elucidate the underlying cause, we introduce a 3D model that quantifies the total internal GB area within the perovskite absorber. A simplified void-free and perfectly packed cubic geometry is utilised for mathematical clarity and to establish a direct quantitative relationship between GB density and FF deterioration, offering mechanistic insight into scaling-induced performance losses. Although real-world films deviate from this idealised symmetry, the model effectively aids relative trend analysis. Further details on model constraints are available in the SI. Leveraging ALD's conformality and thickness precision, scaling-induced PCE loss was minimized to approximately −2%, with efficiencies of 19.8% and 17.6% for active areas of 0.06 and 1 cm2, respectively. To the best of our knowledge, these values represent some of the highest reported efficiencies for dopant-free inverted PSCs employing ALD-NiO HTLs, underscoring the potential of ALD as a robust strategy for overcoming scalability limitations in PSCs.
As shown in Fig. 3d, JSC remains consistent across all ALD-NiO devices, with a modest improvement of approximately +4% when scaling from 0.06 cm2 to 1 cm2. In contrast, NP and sol–gel devices exhibit clear area-dependent losses of −5.3% and −12%, respectively. Although the HTL compositions are nominally identical, the ALD process produces NiO films with markedly different morphological and structural characteristics compared to NP or sol–gel counterparts, which directly influence charge transport and collection during device operation. The excellent conformality of ALD-NiO films—despite the underlying rough FTO substrate—likely facilitates more homogeneous deposition of the subsequent perovskite absorber. Variability in spin-coating is well-documented, and the technique is widely considered unsuitable for large-area fabrication.16,41–44 While solution processed perovskite films can appear uniform over small lab-scales, gradient spreading inevitably introduces thickness and compositional variations over larger areas, contributing to the observed JSC decline in sol–gel and NP devices. Alternative scalable deposition techniques, such as thermal evaporation or blade coating, have been shown to mitigate these losses while maintaining high performance.16,41–44 Overall, these results indicate that the fabrication method of the active layers—both the HTL and perovskite absorber—play a decisive role in JSC retention during area scaling, and consequently the PCE of iPSCs.
Lastly, fill factor (FF) data for devices is shown in Fig. 3e. Unlike JSC, which showed varying trends between devices with solution and vapour processed NiO HTLs, the trend of FF decreasing with increased active area is consistent across all devices. The maximum FF (absolute) values of all devices decrease by more than 10% when scaling from 0.06 cm2 to 1 cm2, while the average FF falls by −11.9% for ALD, −14.3% for sol–gel, and −15.6% for NP devices. Although ALD-based devices exhibit a less pronounced decrease compared to sol–gel and NP devices, the absolute reduction in FF remains significant and represents the largest performance loss among all J–V parameters. At 1 cm2, all device sets contain some devices with FF values below 60%, a sharp decline from the maximum values of around 80% in small-area devices. These results signify that FF is the critical limiting factor in upscaled devices, offering the greatest opportunity for improvement through interface and transport layer engineering. This observation motivates a deeper examination of the physical origins of FF loss, and the reasoning behind why ALD-based NiO HTLs mitigate these losses more effectively than NP and sol–gel NiO films.
Consistent with this expectation, ALD-NiO devices show stable shunt resistance (RSH) with increasing active area (Fig. 4b), whereas the series resistance (RS) increases notably (Fig. 4c). Fig. 4a compares the J–V characteristics of devices with different active areas. (The dependence of resistive parameters and FF on device area for sol–gel and NP NiO devices is shown in Fig. S1). While all devices exhibit nearly identical current densities at low bias, a pronounced roll-off in the high-bias region becomes increasingly severe as the active area increases. This roll-off occurs when voltage losses across the series resistance become comparable to the applied bias. At high current–densities near VOC, a growing fraction of the voltage is dissipated in resistive elements of the device, which weakens the internal field and limits charge extraction, producing the observed flattening of the J–V curve and corresponding reduction in FF.46,47 The behaviour is characteristic of RS-limited charge extraction and directly explains the observed reduction in FF for larger-area devices. The trend is summarized in Fig. 4d, where increasing active area leads to increased RS and decreased FF. The strong inverse correlation between FF and RS confirms that RS is the dominant factor governing FF loss, and therefore PCE decrease, upon device upscaling.
Resistive losses, however, originate from multiple aspects of device architecture, including geometry and charge transport layer (CTL) & electrode design. Several strategies have been shown to mitigate scaling-induced resistive limitations, such as implementing strip-like geometries, using modules composed of narrow interconnected sub-cells, and optimizing CTL layer thickness.48–53 Together, these findings emphasize that managing both intrinsic TCO resistance and device design is another essential consideration when trying to fabricate large-area devices near their performance limits.
Grazing-incidence X-ray diffraction (GIXRD) was used to probe the crystallinity of NiO layers. As shown in Fig. 5, diffraction features are observed at 2θ ≈ 37°, 43°, 62°, 75°, corresponding to the (111), (200), (220) and (311) planes of cubic NiO. The signal is weak for thinner films (sol gel, NP, and ALD 200 cycles) while a clear and higher-intensity pattern is observed for the thicker ALD film (500 cycles). This behaviour is attributed to the limited diffracting volume of the thinner films rather than to amorphous NiO. The increased diffraction intensity from 200 to 500 ALD cycles further reflects controlled thickness scaling in the ALD-grown NiO layers.
Field-Emission Scanning Electron Microscopy (FE-SEM) imaging of the bare NiO films on Glass/FTO substrates (Fig. 6a–c) reveals distinct differences in the morphology formed by ALD, NP, and sol–gel methods. The ALD-NiO film (Fig. 6a), being the thinnest at just ∼6.4 nm, forms a highly conformal layer morphologically indistinguishable from the surface of the FTO grains. Unlike other methods, ALD ensures uniform coverage over the rough FTO crystallites without significantly altering the surface texture. In contrast, the NP-NiO film (Fig. 6b) exhibits a rougher, granular texture composed of grain clusters approximately 20 nm in diameter, which appear to fully cover the underlying FTO. The sol–gel NiO (Fig. 6c), however, provides only partial coverage. As highlighted in the inset (red box), protruding FTO crystallites are clearly exposed, while the NiO appears to have preferentially accumulated in the valleys. Achieving full coverage with the sol–gel method would likely require a significantly thicker layer, which could be detrimental to device performance by increasing series resistance (Rs) and causing subsequent FF losses. Simultaneous comparison with Conductive-Atomic Force Microscopy (C-AFM) imaging provides a more comprehensive understanding of the effect of morphology differences on electrical homogeneity. C-AFM topography maps (Fig. 6d–f) confirm the high-aspect nature of the underlying FTO. Bright areas indicate high peaks, and valleys appear dark. Corresponding conductivity maps (Fig. 6g–i) reveal a stark contrast in film quality. The ALD-NiO film reveals the most spatially uniform conductive response with a low occurrence of high-current hotspots. Conversely, NP-NiO and sol–gel NiO films display frequent high-current features and significant heterogeneity in local current, indicative of local shunt pathways or non-uniform contact. The overlay of conductivity and topography (Fig. 6j–l) conclusively shows that current hotspots in sol–gel and NP-NiO films are concentrated around FTO peaks that were identified in the FE-SEM analysis. The superior coverage of the ALD-NiO layer, despite the roughness of FTO beneath, results in a much more qualitatively uniform conductivity map. Given that FF is highly sensitive to leakage and local shunts35—particularly in large-area devices—such conductivity inhomogeneities help explain why NP and sol–gel devices struggle to maintain FF during upscaling.
To elucidate the effect of the NiO deposition method on hole transport, current–voltage (I–V) curves for FTO/NiO(ALD)/Ag, FTO/NiO(NP)/Ag, and FTO/NiO(sol–gel)/Ag were measured (Fig. S3). All three NiO films exhibit a linear current–voltage relationship, indicating ohmic behaviour. Small slope differences likely reflect variations in leakage and contact resistance rather than the operating-condition series resistance, which is quantified separately in Fig. 4 and S1.
Contact-angle measurements (Fig. 7a–c) reveal that ALD-NiO is the most wettable (i.e. smallest contact angle ≈ 13.6°), followed by sol–gel (≈16.2°) and NP-NiO (≈26.2°). The lower contact angle on the surface of ALD films promotes more uniform precursor wetting during spin-coating of perovskite and hence improved nucleation and larger, more continuous grains. This trend in wettability correlates with the perovskite morphologies observed in SEM (Fig. S4). Each method produces distinct microstructures and grain sizes. ALD-NiO yields compact, well-covered perovskite films while NP and especially sol–gel films show poorer coverage, numerous voids, and smaller, more irregular grains that can facilitate shunts or non-uniform current pathways—factors that reduce FF as area increases. Histograms of perovskite grain size depending on the NiO deposition method are shown in Fig. S6. To provide qualitative insight into how grain size influences the effective internal grain boundary area, a simple geometric model was employed (Fig. S7–8). The model assumes idealized grain packing and is intended to illustrate scaling trends rather than provide a quantitative description of charge transport. The model parameters and equations are summarized in the SI (Tables S3–S4 and following text).
Steady-state photoluminescence (PL) measurements of Glass/FTO/(HTL)/perovskite stacks were carried out using a 455 nm excitation laser source. Fig. 7d compares the PL response of perovskite films deposited on ALD-, NP-, and sol–gel-NiO HTLs with a Glass/FTO/perovskite control and FTO-free Glass/NiO/perovskite reference structure. It should be noted that the FTO-free reference employs the same ALD-NiO layer as the corresponding Glass/FTO/NiO/perovskite stack, with the omission of underlying FTO being the only difference. In contrast to the Glass/NiO/perovskite reference, which exhibits clear PL quenching, all Glass/FTO/NiO/perovskite stacks show enhanced PL intensity relative to the Glass/FTO/perovskite control. Among the NiO HTLs, the ALD-NiO sample exhibits the highest PL intensity, followed by sol–gel and NP-NiO samples. The maximum PL peak positions for the FTO-containing samples remained largely unchanged, with emission maxima at 797 nm on FTO, 797 nm on NP-NiO, 794 nm on sol–gel NiO, and 798 nm on ALD-NiO, whereas the Glass/NiO/perovskite reference shows a modest blue-shift to 787 nm, which may be associated with changes in the dominant radiative recombination pathway under strong interfacial charge transfer conditions.54,55 PL quenching observed in the FTO-free reference is consistent with either efficient interfacial hole transfer or enhanced non-radiative recombination at the interface.56 In the present case, the FTO-free reference is included to demonstrate that ALD-NiO can induce strong quenching in a simplified structure. By comparison, the increased PL intensity observed in device-relevant Glass/FTO/ALD-NiO/perovskite stacks is consistent with reduced interfacial recombination while maintaining effective charge extraction, as support by the high performance of the corresponding devices. Similar behaviour, where NiO HTLs exhibit enhanced PL intensity despite efficient charge extraction and superior device performance have been observed in prior reports.36,38 Yang et al., observed that PL intensity decreased as the NiO HTL thickness increased. Despite a PEDOT: PSS sample showing PL quenching, and a NiO (ALD, 200 cycles) sample showing increased PL intensity, the NiO devices outperformed PEDOT:PSS devices in terms of the PCE and JSC.36 Taken together, the PL results and device metrics indicate that ALD-NiO forms a high-quality interface that mitigates recombination while maintaining effective hole extraction in device-relevant architectures.
Ultraviolet photoelectron spectroscopy (UPS) measurements of perovskite and NiO films (UPS Spectra shown in Fig. S5) were used to produce an energy level diagram, as shown in Fig. 7e. All three NiO deposition methods yield valence-band onsets close to the perovskite valence band maximum (VBM), but with subtle differences in work function and valence level. The measured valence energies for NP, sol–gel and ALD-NiO were approximately −4.66 eV, −4.79 eV and −4.81 eV, respectively, compared to the perovskite valence energy at −5.51 eV. The slightly deeper valence position of ALD-NiO compared to sol–gel and NP-NiO suggests marginally improved hole extraction, which could be a contributing factor to improved JSC and FF retention upon scaling in ALD-based devices.
The comparison in Fig. 8b places the present results within the broader context of ALD-NiO based PSCs and highlights the role of a controlled, systematic scaling approach. Furthermore, the 1 cm2 ALD-NiO devices exhibit negligible J–V hysteresis (Fig. 8c), confirming a high-quality interface between the HTL and absorber layer. ALD-NiO forms a seamless, low-loss contact with the perovskite, allowing for efficient hole collection even over larger areas. Unlike many literature reports where device area varies across unrelated architectures and processing conditions, this work examines performance evolution from small-to large-area devices within a consistent materials system and fabrication framework. The observed retention of PCE upon increasing active area therefore reflects intrinsic scalability of the ALD-NiO HTL and device design, enabling a more meaningful assessment of upscaling behaviour in PSCs.
![]() | ||
| Fig. 8 (a) Cross-sectional SEM image of iPSC full-device stack. (b) Power conversion efficiency (PCE) as a function of active area for perovskite solar cells employing pure ALD-NiO hole transport layers, comparing the present work with reported literature devices employing ALD-NiO HTLs,.31,37–40 The yellow shaded region highlights the large-area regime (≥1 cm2). Red stars indicate devices fabricated in this work. (c) J–V curves of champion 1 cm2 ALD-NiO device showing hysteresis behaviour. Measurements were conducted at a scan speed of 187 mV s−1 (12.5 mV step size, 50 ms voltage settling time). The device exhibited negligible hysteresis, yielding an average PCE of 17.5% (reverse-scan PCE = 17.6%, forward-scan PCE = 17.4%). (d) Comparison of PCE retention across different scalable NiO-HTL deposition methods. Values in parentheses represent the total absolute PCE loss between champion devices across the area range. Full numerical data are detailed in Table S5 of the SI. | ||
Lastly, the performance retention observed in this work was benchmarked against various scalable NiO deposition techniques reported in the literature (Fig. 8d and Table S5). While techniques such as magnetron sputtering and meniscus coating have achieved higher absolute PCEs, those results were contingent upon the use of multi-layer (sputtered-NiO/NP-NiO/SAM) HTL stacks and perovskite passivation. Despite these additional layers, those systems show scaling losses (−4.6% and −5.9%) more than double those of our baseline ALD-NiO devices (−2.2%). These results indicate that the superior uniformity of ALD-NiO provides a more robust morphological foundation for suppressing the interfacial defects that typically compromise performance in large-area PSCs that incorporate NiO-HTLs. Furthermore, by focusing on the 1 cm2 scale, we enable a precise evaluation of intrinsic HTL scaling losses without introducing further complexities of laser-patterning and interconnection required for perovskite solar modules (PSMs).
ALD-NiO films exhibited superior conformality, electrical homogeneity, and surface wettability on rough FTO substrates, yielding a favourable platform for subsequent perovskite growth. As a result, ALD-based devices demonstrated enhanced JSC retention and the smallest PCE loss upon upscaling, with efficiencies decreasing by only around 2% when increasing the active area from 0.06 to 1 cm2. Importantly, VOC remained stable across all device sizes, confirming reproducible fabrication and suppressed non-radiative recombination. FF emerged as the dominant limiting parameter for large-area devices, driven primarily by increasing series resistance and amplified by microstructural non-uniformities. While upscaling losses can also be influenced by factors such as perovskite crystallization kinetics, the concentration of trap-states, and electrode design; our results highlight that interfacial conformality is a critical prerequisite for maintaining performance as area is increased. This underscores the need for simultaneous management of both charge-transport interfaces and large-area film uniformity to bridge the cell-to-module efficiency gap.
To elucidate the physical origins of this behaviour, a 3D model was introduced to quantify the total internal grain boundary area within the perovskite absorber. The model establishes a direct connection between perovskite microstructure and FF deterioration, providing mechanistic insight into how conformal HTLs can suppress scaling-induced losses by promoting larger, more continuous grains. By minimizing internal grain boundary density, ALD-NiO enables devices to more closely approach resistive performance limits imposed by the TCO substrate.
These results demonstrate that ALD-NiO serves as an effective, dopant-free HTL for inverted PSCs, offering precise thickness control, excellent uniformity, and improved upscaling behaviour without the need for additional interlayers or chemical modification. While the absolute efficiencies reported here were intentionally achieved without the use of chemical doping, surface passivation layers, SAMs, or other high-performance interfacial strategies, such approaches are expected to be largely complementary to ALD-based HTL engineering and offer clear pathways to further enhance PCE while retaining favourable scaling behaviour. It is important to note that the NiO/perovskite interface is a recognized site of potential long-term degradation. Consequently, addressing interfacial chemical stability remains a vital consideration for future studies aimed at improving the operational lifetime of similar device architectures. In addition, the perovskite deposition method itself is known to play a critical role in determining large-area film uniformity and device performance; integration of scalable coating or vapour-based deposition techniques represents an important direction for future work beyond the scope of this study. More broadly, this work provides a mechanistic framework for understanding and mitigating efficiency losses during PSC upscaling, and highlights ALD as a promising route toward robust, scalable perovskite photovoltaics and future tandem solar cell integration.
:
1 volume ratio. The suspension was sonicated to ensure uniform dispersion and prevent nanoparticle aggregation. Following sonication, the solution was filtered to remove any impurities or large aggregates. 100 µL of the filtered solution was spin coated at 5000 rpm for 30 s under ambient conditions. The resulting ∼9 nm thick film was annealed on a hot plate at 150 °C for 20 min.
:
DMSO (4
:
1 v/v) solvent mixture (DMF
:
99.8% anhydrous, Aldrich; DMSO: ≥99.9% anhydrous, Aldrich). The solution was stirred at room temperature for 4 h and filtered through a polytetrafluoroethylene (PTFE, pore size ≈0.2 µm) membrane before use.
| This journal is © The Royal Society of Chemistry 2026 |