Grain size engineering via a Hf_0.5Zr_0.5O₂ seed layer for FeFET memory and synaptic devices

Abstract

This study demonstrates the use of a top-gate ferroelectric field effect transistor (FeFET) with the replacement electrode solid phase epitaxy (SPE) method and high deposition temperature during atomic layer deposition (ALD). By employing these engineering techniques, the average grain size was successfully reduced, and the formation of the non-ferroelectric monoclinic phase (m-phase) was effectively inhibited. In terms of ferroelectric properties, both the remanent polarization (2P_r) and coercive field (E_c) values demonstrated significant increases by 35% and 50%, respectively. Notably, improvements were observed in memory characteristics, with the memory window (MW) increasing from 0.3 V to 0.9 V and endurance enhancing by three orders of magnitude. In terms of synaptic properties, there was an enhancement in the number of conductance states from 100 to 136, an increase in the G_max/G_min ratio from 5.16 to 90, and an improvement in weight update linearity. The simulation results based on the MNIST dataset show an improvement in inference accuracy from 65% to 85%.

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Introduction

As the demands of scaling increase, the traditional von Neumann architecture, which separates the processing unit from memory, encounters a bottleneck due to the inherent limitations of sequential processing. This results in issues such as elevated power consumption and diminished processing speed.^1,2 In response to these challenges, a brain-inspired approach towards computing, known as neuromorphic computing, has been proposed as an alternative. In contrast to conventional systems, neuromorphic computing facilitates parallel processing, which results in reduced power consumption and enhanced energy efficiency.^2–4 The implementation of neuromorphic computing has been proposed to utilize emerging non-volatile memory (eNVM) as a suitable hardware platform, given its capacity for high-density weight storage and rapid parallel computing.⁵ Among the various options for eNVM, ferroelectric-based devices are particularly promising candidates, as they are capable of implementing synaptic plasticity.³

In comparison with conventional perovskite ferroelectric materials, hafnium-zirconium oxide (HZO) is a more suitable material for applications in ferroelectric field effect transistors (FeFETs) due to its scalability and compatibility with complementary metal oxide semiconductor (CMOS) technology.⁵ Nevertheless, there are still several issues that require further investigation and resolution. For instance, device-to-device variation increases with the size scaling of FeFET devices, which in turn results in a reduction in the memory window (MW) for significantly scaled FeFET arrays.⁶ To mitigate device-to-device variation and achieve robust ferroelectricity, it is important to decrease the dielectric component and reduce the grain size.^7,8 Increasing the ALD deposition temperature is an effective method for increasing the proportion of the orthorhombic/tetragonal-phase (o-phase, t-phase), which reduces the dielectric component and enhances ferroelectric properties.⁹ For grain size engineering, a reduction in grain size inhibits the formation of the non-FE monoclinic phase (m-phase).¹⁰ The utilization of the replacement electrode solid phase epitaxy (SPE) methodology enables a considerable reduction in grain size, thus enhancing ferroelectricity.¹¹ Furthermore, the control of grain size is also of great importance in the field of synaptic devices. It has been demonstrated that pivotal synaptic characteristics, such as multistate functionality and linearity, are intimately associated with the number and size of grains.^12,13

In this study, we investigated the effects of grain size control using the SPE method and high ALD deposition temperature on HZO-based FeFETs. These engineering approaches yielded significant improvements in memory properties and a notable reduction in device-to-device variation. Regarding the memory characteristics of the FeFET, improvements were observed in MW, I_on/off and endurance. Furthermore, significant improvements were observed in synaptic properties, including the number of conductance states, G_max/G_min, linearity, and inference accuracy.

Experimental

The SPE mechanism involves depositing an amorphous material onto a crystalline substrate and then performing annealing, during which the atoms in the amorphous phase rearrange to replicate the structure of the crystalline substrate.¹⁴ Instead of using a crystalline substrate, a crystalline seed layer of thin-film HZO was utilized. For HZO, the grain size decreases as the thickness decreases, which is why a thin 2.2 nm HZO layer was employed.^15,16Fig. 1 illustrates the structural configuration and process flow of the metal–ferroelectric–metal (MFM) capacitor and the metal–ferroelectric–insulator–semiconductor (MFIS) FeFET device. The fabrication process of the MFM capacitor is as follows. First, 35 nm of W was deposited as the bottom electrode on a P–Si/SiO₂ (300 nm) substrate through DC sputtering. Then, approximately 2.2 nm of HZO with a 1 : 1 cycle ratio of HfO₂/ZrO₂ was deposited as a seed layer using thermal ALD. In the ALD process, tetrakis-(ethylmethylamino)-hafnium (TEMA-Hf), tetrakis-(ethylmethylamino)-zirconium (TEMA-Zr), and O₃ were employed as the Hf precursor, Zr precursor, and oxygen source, respectively. The temperature during the ALD seed layer deposition was fixed at 280 °C. Subsequently, a 35 nm layer of W was deposited, after which the seed layer underwent crystallization via rapid thermal annealing (RTA) under an N₂ atmosphere at 600 °C for 60 seconds. Following the crystallization process, the W stressor was wet etched using an 80 °C APM solution (NH₄OH : H₂O₂ : H₂O = 1 : 1 : 5) to deposit the top layer. The 6.8 nm HZO top layer with a 1 : 1 cycle ratio of HfO₂/ZrO₂ was deposited at ALD stage temperatures of 280 °C and 320 °C. Gate patterning was then performed, and 35 nm of W was deposited again as the top electrode. Finally, the crystallization of the ferroelectric layer and the alignment with the seed layer crystallinity were carried out using RTA under an N₂ atmosphere at 550 °C for 60 seconds.

Fig. 1 Fabrication process flow and the schematic of an MFM capacitor and FeFET using the SPE method.

The fabrication process of the FeFET is as follows: the FeFET has a top gate structure and is fabricated using a gate-last process. First, patterning was performed on the p-Si/SiO₂ (300 nm) substrate, and the SiO₂ (300 nm) was wet-etched using buffered oxide etcher (BOE) to form the source/drain (S/D) region. Ion implantation was carried out using P⁺ ions for S/D region doping. After removing the photoresist (PR) with an SPM solution (H₂SO₄ : H₂O₂ = 1 : 1), dopant activation was carried out using RTA under an N₂ atmosphere at 950 °C for 10 seconds. To grow the interfacial layer (IL) as SiO₂, it was soaked in an 85 °C APM solution for 5 minutes. Then a HZO seed layer of 2.2 nm was deposited at an ALD stage temperature of 280 °C. Similarly, to crystallize the seed layer, 35 nm of W was deposited using DC sputtering, followed by RTA under an N₂ atmosphere at 600 °C for 60 seconds. Following the wet etching of the 35 nm W layer with an APM solution, the top layer of HZO 6.8 nm was deposited. The top layer deposition was conducted at ALD stage temperatures of 280 °C and 320 °C, respectively. Gate patterning was then carried out, and 35 nm of W was deposited as the upper electrode. For metal contact in the S/D, contact hole patterning was performed, and the HZO stack was wet-etched using BOE. 35 nm of W was employed as the S/D contact metal. Finally, RTA was carried out under an N₂ atmosphere at 550 °C for 60 seconds to crystallize the HZO stack. The crystallization temperatures of the seed layer and top layer were different because the seed layer is about 2.2 nm thin and requires a slightly higher temperature for crystallization.^16–18 Furthermore, if the crystallization of the top layer is performed at 600 °C, the seed layer would undergo additional heat treatment at the same temperature, which will result in an increased transition to the m-phase. To minimize this, the crystallization was carried out at a lower temperature.

Results and discussion

Fig. 2(a) depicts a cross-sectional high resolution transmission electron microscopy (HR-TEM) image of the gate of the FeFET device in which the top layer was deposited at 320 °C with SPE applied. Even if the deposition temperatures of the seed layer and the top layer are different, the TEM image shows well-crystallized layers with no noticeable boundaries between them. In Fig. S1,† it can be observed that the 2.2 nm HZO seed layer is well-crystallized. The yellow box in Fig. 2(a) contains both the fast Fourier transform (FFT) pattern and the inverse FFT image, from which the interplanar distance is determined to be 2.94 Å, confirming the presence of the o-phase within the ferroelectric HZO layer. Fig. 2(b) provides additional confirmation that the ratio of Hf to Zr is 1 : 1, as determined from the energy dispersive spectrometry (EDS) line scanning analysis.

Fig. 2 (a) Cross-sectional HR-TEM image with an inset showing the FFT pattern and inverse FFT image, and (b) EDS line scanning analysis of a device with the top layer deposited at 320 °C using the SPE method.

A top-view SEM analysis was conducted to investigate the effect of SPE application on grain size in 9 nm HZO films. To extract the grain size from the SEM image, the software ImageJ was used. The diameters of 100 grains were measured to calculate the average grain size for each device. Fig. 3(a)–(c) illustrates that the application of SPE results in a reduction in grain size. Fig. 3(d) illustrates the distribution of grain sizes observed in each device, as determined from the SEM images. In the absence of SPE, the mean grain diameter was observed to be 12.75 nm. In contrast, the application of SPE at top layer deposition temperatures of 280 °C and 320 °C resulted in a reduction in the average grain diameter, with values of 10.54 nm and 10.2 nm, respectively. Furthermore, the reduction in grain size resulting from the SPE process leads to a more uniform grain size distribution. The standard deviations were found to be 3.26, 2.12, and 1.85 for devices without a seed layer, with the top layer deposited at 280 °C, and with the top layer deposited at 320 °C, respectively. Full width at half maximum (FWHM) was extracted from the grazing incidence X-ray diffraction (GI-XRD) pattern as shown in Fig. S2.† It can be seen that this is consistent with the trends in Fig. 3.

Fig. 3 Top view SEM images of: (a) 9 nm HZO film without a seed layer, (b) top layer deposited at 280 °C with SPE and (c) top layer deposited at 320 °C with SPE. (d) Grain size distribution of 9 nm HZO with and without the SPE method.

In HfO₂-based materials, the o-phase and t-phase are structurally very similar, causing the X-ray diffraction (XRD) peaks to overlap around ∼30.5°. Nevertheless, the o-phase and t-phase can be distinguished at 30.4° and 30.8°, respectively, by using the lattice parameters of the HZO film and Vegard's law.¹⁸Fig. 4(a) shows the GI-XRD spectra of devices with and without the SPE method applied, within the 2θ range of 26–34°. The application of the SPE method results in a shift of the peak around ∼30.5° to the left. When the top layer is deposited at 320 °C, the peak shifts further left, indicating an increased proportion of the o-phase. To ensure an accurate comparison of the phase ratios of the HZO films in each device, the peaks around 30.5° were carefully deconvoluted and are shown in Fig. 4(b). Peaks at 28.5°, 30.4°, 30.8°, and 31.6° correspond to m(−111), o(111), t(011), and m(111), respectively.^19,20 The application of the SPE method in conjunction with an elevated deposition temperature for the top layer results in a reduction in the t-phase ratio and an increase in the o-phase ratio. Additionally, the m-phase ratio was observed to decrease, which is likely attributable to the sufficient heat treatment time, resulting in a reduction of the dielectric component.⁷

Fig. 4 (a) GI-XRD pattern in the 2θ range from 26° to 34° and (b) relative ratio of the phases of HZO films with and without SPE.

Prior to the fabrication of the FeFET, the ferroelectric properties of the HZO ferroelectric layer were evaluated through the fabrication of an MFM capacitor. Fig. 5(a) compares the P–V characteristics of devices with and without the SPE method after wake-up. The wake-up procedure was performed using the positive up negative down (PUND) pulse as illustrated in Fig. 8(a), with ±3 V and 10⁴ cycles applied. To extract the P–V hysteresis loop, a triangular pulse of ±3 V was applied to each MFM capacitor. The results of the P–V curve obtained through the PUND pulse to verify ferroelectricity excluding leakage components are shown in Fig. S3.† When the seed layer and top layer deposition temperatures were set at 280 °C and 320 °C, respectively, an additional improvement in ferroelectric properties was observed, with 2P_r reaching about 50 μC cm⁻², which is approximately 35% higher than the device without a seed layer. These improvements can be attributed to the reduction in grain size, as observed in Fig. 3. In HZO, the formation of o- or t-phases is more probable with smaller grain sizes.²¹ As mentioned earlier, applying the SPE method resulted in an increase in the proportion of the o-phase. Furthermore, the reduction in the proportion of the m-phase is also confirmed, as the Gibbs free energy of the t-phase is lower than that of the m-phase for smaller grain sizes, which inhibits the formation of the m-phase.²² Additionally, E_c also increased by about 50%, reaching 2.4 MV cm⁻¹. This is attributed to the fact that a lower dielectric constant necessitates a stronger electric field to induce polarization switching,²³ as depicted in Fig. 8(c). Furthermore, as the grain size decreases, the energy barrier for domain wall propagation increases, which leads to a reduction in the velocity of the domain walls.²⁴ This is why there is an inverse relationship between grain size and E_c.^24,25 There is also a strain related factor. As the thin film grows, crystallites grow and form grain boundaries as they come into contact with each other. When grains merge, they coalesce quickly due to a rapid zipping phenomenon. During this process, elastic deformation occurs, and the smaller the grain size, the more frequent these coalescence processes are, thereby increasing the overall stress.²⁶ Thus, a lot of tensile stress aids in the formation of the o-phase,²⁷ and the enhancement of ferroelectricity also influences the increase in E_c.^28,29Fig. 5(b) shows the cumulative distribution of P_r when using grain size reduction engineering. A reduction in grain size results in a notable decrease in device-to-device variation. This is due to both the reduced grain size and improved crystallinity. The total annealing time through RTA is longer for the device with SPE compared to those that did not. A sufficient heat treatment time results in a reduction of the dielectric component and an increase in the ferroelectric phase, thereby improving the uniformity of the crystals.⁷

Fig. 5 (a) P–V hysteresis loops of 9 nm HZO FeCAPs, highlighting the effects of applying SPE and varying the deposition temperature of the top layer. (b) Device-to-device variation of each device.

Fig. 6(a) shows the I_d–V_g curve of FeFET devices with and without the SPE method. The FeFET devices have a width and length of 40 μm and 20 μm, respectively, and were measured with a ±3.5 V voltage sweep at the gate and an 80 mV voltage at the drain. The reason for setting the drain voltage relatively low is that a high drain voltage degrades the MW and on/off current ratio.³⁰ The MW was extracted using the constant current method, I_d = W/L × 10⁻⁷ [A], as illustrated in Fig. 6(b).³¹ MW is largely influenced by the E_c value and can be expressed as follows:³²

Fig. 6 (a) I_d–V_g characteristics and (b) extracted MW with and without the SPE method of HZO-based FeFETs.

where ε₀, ε_FE, T_FE, and P_s are the permittivity of vacuum, the permittivity of the ferroelectric layer, the thickness of the ferroelectric layer, and spontaneous polarization, respectively. From this equation, it can be seen that MW is heavily influenced by the E_c value.

All devices exhibited anti-clockwise behavior, indicating ferroelectric properties. The device without a seed layer exhibited an MW of 0.3 V, while the SPE device fabricated at 280 °C demonstrated an MW of about 0.4 V. Notably, the device with the top layer deposited at 320 °C showed a considerable increase in MW, reaching approximately 0.9 V. The observed increase in MW can be attributed to the following reasons. In FeFET, MW is influenced by both the 2P_r and E_c values, with the latter having a greater impact.³² As illustrated in Fig. 5(a), both 2P_r and E_c increased significantly with the SPE implementation.

Another contributing factor is the reduced charge trapping with SPE. In ferroelectric materials, electrical displacement can be expressed as follows:

D = ε₀ε_FEE_FE + P_s = Q_s + Q_trap

where E_FE, Q_s, and Q_trap are the electric field in the ferroelectric, mobile charge, and trapped charge, respectively. Approximating this, P_s ≈ Q_trap and ε₀ε_FEE_FE ≈ Q_s.³³ This implies that the amount of trapped charge can be compared through the P_s value. Fig. 7(a) shows the relationship between the P_r and P_s values for each device to compare the trapped charge. The device without a seed layer had the lowest P_r/P_s value of about 0.68, which increased to 0.80 and 0.935 following the introduction of SPE, indicating a reduction in the trapped charge.³⁴ This is because oxygen vacancies or oxygen interstitial atoms, which create shallow or deep trap states, serve as the primary contributors to charge trapping.^35,36 X-ray photoelectron spectroscopy (XPS) analysis was performed to verify the oxygen vacancy content in HZO thin films with and without SPE application. Fig. 7(b) shows the XPS analysis results of HZO thin films. The O 1s spectra of the HZO film were deconvoluted into Hf–O bonds and sub-oxides (oxygen vacancies). The application of the SPE method resulted in a reduction in the content of oxygen vacancies. The reduction in oxygen vacancies resulted in a decrease in the amount of trapped charge, which in turn led to an increase in the MW. Additionally, the off current in the transfer curve decreased, which was also due to the reduction in oxygen vacancies. Another reason for the reduction in charge trapping is due to the decrease in grain size. Charge trapping at the ferroelectric/dielectric interface is one of the factors that deteriorate MW.³¹ Smaller grains create a relatively flat HZO/SiO₂ interface. This flat interface causes less charge trapping compared to a rough interface, resulting in a decrease in trapped charges.^37,38

Fig. 7 (a) The relationship between P_r and P_s values in devices with and without SPE. (b) The sub-oxide (oxygen vacancy) ratio in the XPS spectra of O 1s for each device.

Fig. 8(a) shows the PUND pulse scheme used for the endurance test. Fig. 8(b) shows the endurance characteristics of FeFETs with and without SPE application. Pulses with a width, interval, and amplitude of 10 μs, 10 μs, and ±5 V, respectively, were applied. While FeFET without a seed layer broke down at around 10³ cycles, the SPE FeFETs exhibited robust endurance characteristics, lasting up to 10⁶ cycles without breakdown. These endurance characteristics can be explained by considering the effects of the dielectric constant, leakage current, oxygen vacancies, and grain size. Fig. 8(c) presents a comparison of the dielectric constants (ε_r) derived from the C–V curve measured at 100 kHz. The SPE-applied devices showed unambiguous ferroelectric butterfly shapes, whereas the device without a seed layer exhibited anti-ferroelectric characteristics with a dominant t-phase. The device without a seed layer also showed anti-ferroelectric characteristics in the P–V and I–V graphs without wake-up cycles (not shown here). However, without applying a wake-up cycle, the C–V curve appears to mix the o-phase and t-phase, but after the wake-up, the butterfly shape shows dominant ferroelectric properties (Fig. S4†). This is because the phase has transitioned due to electrical stress.³⁹ The device without a seed layer exhibited the highest dielectric constant, which was attributed to the dominance of the t-phase (ε_r = 35–40) over the m-phase (ε_r = 15–20) and o-phase (ε_r = 25–30), in accordance with the observed trend in Fig. 4.¹⁶ An increase in the dielectric constant of the ferroelectric layer increases the E-field applied to the SiO₂ interfacial layer, which in turn accelerates its degradation and leads to an earlier breakdown. Fig. 8(d) compares the leakage current of the devices, showing that the SPE-applied devices exhibited a reduced leakage current, whereas the device without a seed layer demonstrated the highest leakage current. The reduction in leakage current with the SPE is due to the decreased oxygen vacancies, leading to improved endurance characteristics. Additionally, grain size can also affect endurance characteristics. Reduced grain size enhances dielectric strength and reduces the dielectric constant.⁴⁰ Furthermore, reduced grain size increases grain boundaries, creating a longer leakage path or a breakdown path that dissipates energy, resulting in higher breakdown strength and lower leakage current, which in turn improves endurance.⁴¹ The reason a current peak occurs near −1 V in the I–V curve of the device with top layer deposition at 320 °C is the negative differential resistance effect. This occurs when ferroelectric domains switch at once at −1 V, causing a sudden charge injection at the gate. Afterwards, when the switching temporarily saturates, the current rapidly decreases, forming a current peak. However, this phenomenon only occurs during the first cycle and disappears when the second cycle is applied.^42–44

Fig. 8 (a) PUND pulse scheme used for wake-up and endurance tests. (b) Endurance, (c) dielectric constant and (d) leakage current characteristics of three different FeFETs.

Among the various artificial synaptic applications, FeFETs are particularly well-suited for use as artificial synaptic devices due to their ability to finely regulate the threshold voltage (V_t) through partial polarization switching. The term ‘synaptic weight’ is used to define the strength of connections between biological neurons. The processes of potentiation and depression refer to the strengthening and weakening of these connections, respectively. In analog synaptic devices, the synaptic weight is represented by the channel conductance, and it is crucial to precisely control this conductance.

To evaluate the ability of FeFETs to modulate channel conductance and emulate the long-term memory characteristics of synapses, an examination of their long-term potentiation (LTP) and long-term depression (LTD) characteristics was conducted, as shown in Fig. 9(a)–(c). The measurements were conducted using an incremental pulse scheme, with a fixed pulse width and delay of 1 μs as depicted in Fig. 9(d)–(f). The number of conductance states increased from 100 in the device without a seed layer to 136 when SPE was applied. This increase is attributed to the reduction in the grain size, which led to an increase in the number of domains.⁶ The G_min values for devices without a seed layer, with the top layer deposited at 280 °C, and with the top layer deposited at 320 °C are 3.2, 1.8, and 2.18, respectively, while the G_max values are 16.5, 143, and 197, respectively. The G_max/G_min ratio of the device without a seed layer was only about 5.16, but it significantly improved to around 90 when the top layer was deposited at 320 °C with SPE. The increase in the G_max value is attributed to the suppression of surface roughness increase after annealing, due to the reduction in the grain size, which helped mitigate the decrease in mobility.³⁸ Additionally, the reduction in G_min was due to the decrease in oxygen vacancies, which act as leakage paths.

Fig. 9 LTP/LTD synaptic characteristics of: (a) FeFET without a seed layer, (b) top layer deposited at 280 °C with SPE and (c) top layer deposited at 320 °C with SPE FeFETs. (d)–(f) Schematic of potentiation/depression incremental pulse waveform.

In order to extract the linearity from the LTP/LTD curves, we analyzed the conductance change as a function of the applied pulse voltage using the following equations:

G_p = B(1 − e^−P/Ap) + G_min

G_d = B(1 − e^{P−P_max/A_d}) + G_max

Here, P, P_max, G_p, G_d, A_p, A_d and B represent the pulse number, maximum number of pulses, conductance during potentiation, conductance during depression, potentiation linearity, depression linearity, and a fitting factor, respectively. The A_p and A_d values for the device without a seed layer were (2.49, −5.28), indicating poor linearity. However, the devices with top layers deposited at 280 °C and 320 °C showed significant improvements in linearity, with values of (1.68, −3.6) and (1.57, −4.2), respectively. A decrease in grain size increases the number of domains.⁶ This prevents abrupt polarization switching due to having various polarization directions (various E_c) and shows analog-like incremental behavior rather than digital behavior in potentiation/depression, achieving better linearity.^13,45–48 The reason linearity is poorer in depression is due to the behavior of holes. The barrier when a negative gate voltage is applied is thicker than the barrier when a positive gate voltage is applied, making hole tunneling more difficult than electron tunneling. Moreover, electrons are trapped in donor traps near the conduction band where de-trapping can occur at lower energy levels, while holes are trapped in acceptor traps that require relatively high energy to de-trap. Therefore, it is difficult for holes to de-trap and tunnel.⁴⁹ Consequently, in voltage ranges where hole tunneling is difficult, there is almost no change in conductance until a specific voltage range where tunneling becomes possible, causing a sudden change in conductance. This results in depression showing poorer linearity compared to potentiation.

Finally, to investigate the system-level inference accuracy of our FeFET synaptic devices, we performed simulations using the NeuroSim system-level macro model based on the Modified National Institute of Standards and Technology (MNIST) dataset.⁵⁰ The neural network used in the simulation was a 2-layer multi-layer perceptron (MLP) comprising 400 input neurons, 100 hidden neurons, and 10 output neurons as depicted in Fig. 10(a). Fig. 10(b) shows the inference accuracy of each device as a function of training epochs. The device without a seed layer achieved an inference accuracy of only ∼65%, which improved to ∼80% with SPE applied. Moreover, the deposition of the top layer at 320 °C resulted in an additional increase in accuracy to ∼85%. This enhancement in inference accuracy is attributed to improvements in linearity, the number of conductance states, and the G_max/G_min ratio.

Fig. 10 (a) Schematic of the 2-layer MLP neural network. (b) The inference accuracy for the MNIST handwritten digit image with and without SPE FeFETs.

Conclusion

In this study, we fabricated FeFETs by increasing the ALD deposition temperature and applying the SPE method, and we investigated the impact of these engineering techniques on the memory and synaptic properties. We demonstrated that a significant enhancement in ferroelectric properties was achieved as a result of a reduction in grain size and the higher ALD deposition temperature. Moreover, the device-to-device variation was also improved. The application of these engineering techniques to FeFETs resulted in excellent memory characteristics, including improved MW, I_on/I_off ratio, and endurance. Furthermore, the synaptic properties, such as the number of conductance states, linearity, and G_max/G_min, were significantly improved, ultimately leading to an increase in inference accuracy to 85%. The proposed approach offers a means of controlling the grain size and quality of the ferroelectric film, which in turn allows the manipulation of ferroelectric and synaptic properties.

Data availability

Our data in this paper are original and can be accessed under authors’ permission.

Conflicts of interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgements

This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (NRF-2022R1A2C2012333, RS-2022-00154752, no. RS-2023-00260527, and no. RS-2024-00407767). This work was also supported by the Technology Innovation Program (RS-2024-00509266) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

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Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d4nr05381h

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