Method of high-order advanced lithography overlay correction to enhance the manufacturing performance of integrated circuits

Abstract

As integrated circuit (IC) manufacturing advances toward smaller technology nodes, conventional lithography methods are increasingly challenged by the diffraction-limited resolution, escalating process complexity, and rising costs. Among these challenges, overlays have a particularly pronounced impact on manufacturing quality. To address this issue, this paper proposes a high-order overlay correction model that employs a two-dimensional fifth-order polynomial to accurately fit and characterize the distribution of overlays. The model's effectiveness is validated through finite element simulations. By incorporating an array of piezoelectric actuators, thermally induced deformation control units, and micro-mechanical clamping mechanisms, the model enables precise regulation of complex stress fields and localized temperature variations along the mask boundary, thereby enabling effective compensation of high-order overlay errors. Simulation results demonstrate that the proposed approach reduces the |mean| + 3σ of overlay to below 1 nm. It achieves nearly 100% correction for 1st-order and 2nd-order overlay components, over 80% correction for 3rd-order and 4th-order components, and a correction rate of 68.16% for 5th-order errors. Multiple randomized verification tests indicate average compensation efficiencies of 96.85% in the x-direction and 97.36% in the y-direction, highlighting the model's robustness and consistency. In practical processes, the model successfully reduces actual wafer overlay to |mean| + 3σ values of 4.22 nm and 6.26 nm in the x and y directions, respectively. This study presents an efficient and reliable solution for high-order overlay compensation in advanced lithography, offering significant benefits for enhancing IC manufacturing performance and reliability.

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1. Introduction

Lithography is a critical process in integrated circuit (IC) manufacturing, wherein photochemical reactions are employed to transfer predefined patterns from a mask onto a wafer surface.^1–3 Lithographic technology has evolved significantly—from early g-line and i-line light sources to deep ultraviolet lithography (DUVL) utilizing 193 nm excimer laser, and further to extreme ultraviolet lithography (EUVL) at a wavelength of 13.5 nm—each technological leap pushing the limits of manufacturing capabilities.^4–6 As technology nodes continue to shrink, conventional optical lithography faces increasing challenges due to the diffraction-limited resolution, the growing complexity and cost of light source fabrication, and rising process intricacies.⁷ To overcome these limitations, a range of emerging lithography techniques have been proposed in recent years, including near-field lithography (NFL), substrate conformal imprint lithography (SCIL),^8–10 surface plasmon lithography (SPL),^11–13 and nanoimprint lithography (NIL).^14–17 These advanced approaches offer promising pathways to surpass the classical diffraction limit, enabling low-cost, large-area, and high-resolution patterning for next-generation semiconductor manufacturing.^18–20

In IC manufacturing, multiple layers are sequentially fabricated starting from a silicon wafer, and positional deviations between layers—referred to as overlay errors—inevitably arise during the process.^21,22 Overlay accuracy is a critical factor influencing lithographic quality, which in turn directly affects the performance, yield, and reliability of ICs.^1,23 As feature sizes continue to shrink in advanced lithography nodes (7 nm and below), the impact of overlay errors on manufacturing quality becomes increasingly pronounced. According to the 2022 International Roadmap for Devices and Systems (IRDS), for the 3 nm technology node, the critical dimension (CD) control requirement for logic metal layers is 1.8 nm (3σ), while the allowable overlay error is constrained to 2.4 nm (3σ).^23,24 These specifications are expected to become even tighter over the coming decade. Currently, high-order overlay correction techniques such as high order process correction (i-HOPC) are adopted to mitigate intra-field overlay errors.^25,26 However, state-of-the-art lithography systems are typically limited to supporting precise correction up to the third-order terms.

In advanced multilayer IC structures, the increasing number of process layers gives rise to pronounced challenges such as local structural distortion, high-order nonlinear deformation, and non-uniform strain induced by thermal stress mismatches.²⁷ Traditional overlay compensation methods based on linear models or low-order polynomial fitting are no longer sufficient to address these complex variations,²⁸ highlighting the urgent need for a high-precision and high-robustness correction scheme capable of addressing high-order overlay. To this end, the present study proposes an effective method for correcting high-order overlay in advanced lithography processes. This approach aims to enhance overall pattern alignment accuracy, reduce manufacturing defect rates, and meet the stringent requirements of future ultra-precise chip fabrication. The structure of this paper is as follows: Section 1 provides the introduction. Section 2 describes the proposed high-order polynomial-based overlay compensation method. Section 3 presents the simulation validation and discussion. Section 4 concludes the study.

2. Theoretical analysis and modeling of overlays

2.1 The source of overlay error and correction model for high-order overlays

Modern IC manufacturing involves a series of complex processes including wafer growth and preparation, lithography and patterning, as well as etching and deposition,^21,29 as illustrated in Fig. 1(a). This process encompasses a wide range of technologies and requires precise control and meticulous attention at every stage. In particular, advanced lithographic techniques typically involve steps such as photoresist coating, soft baking, exposure, post-exposure baking, development, and overlay metrology. Several key factors critically influence overlay accuracy in lithography, including the gravitational deformation of the mask, thermal effects on the mask, wafer-induced distortions, projection lens distortion in the lithography scanner, and mechanical non-uniformities in the movement of various stages.^30,31 These effects become increasingly significant as semiconductor manufacturing advances toward smaller technology nodes. For instance, the mask may undergo slight bending due to gravity, causing pattern misalignment, while absorption of light during exposure leads to localized heating, further affecting pattern dimensions and positions.³² The combined impact of these effects contributes to increased overlay, which varies dynamically with lithography throughput and exposure dose. Optimizing mask design, chuck architecture, and lithography tool inspection and feedback mechanisms can effectively mitigate these issues. Such improvements enhance the overlay accuracy and reliability of advanced lithography processes, thereby fulfilling the stringent requirements of next-generation semiconductor fabrication at ever-decreasing technology nodes.

Fig. 1 Schematic diagram of the modern IC manufacturing process and the high-order overlay error correction in the advanced lithography process.^19,28 (a) Modern IC manufacturing process. (b) The high-order overlay correction in the advanced lithography process.

From the perspective of a macroscopic lithography system, several feasible approaches for overlay error compensation are available in conventional projection lithography systems, as illustrated in Fig. 1(b). These include optical lens aberration correction, mask pattern adjustments, and wafer stage control. However, in emerging lithography techniques such as SPL, NIL, SCIL, and NFL, the absence of projection optics renders traditional lens-based overlay correction methods ineffective. To address this limitation, a generalized high-order overlay correction model is proposed that can be adapted across various lithography platforms, including the aforementioned non-projection types, while remaining compatible with conventional projection lithography systems. The proposed high-order correction framework relies primarily on three types of precision actuators: an array of piezoelectric actuators for the fine control of complex stress distributions along the mask boundary, thermally induced deformation units that regulate localized temperature fields to induce controlled shape changes, and micromechanical clamping mechanisms that apply directional forces to the mask edges, enabling precise in-plane translation and rotation. Notably, this study implements a compensation strategy consisting of 16 distributed force application units positioned around the mask periphery and 143 sub-millimeter thermal control pixels within a 2 mm × 3 mm (6 mm²) lithography field region. Future work may explore denser stress distribution configurations and extend the thermal actuation resolution below 1 mm², thereby enabling even finer control of overlay.

2.2 The high-order process analysis model

The overlay error data are normalized based on a two-dimensional coordinate system within the exposure field, and all coordinate points are transformed into a standardized unit square domain. Inspired by the third-order correction method employed in ASML's intra-field exposure control, this study adopts a two-dimensional fifth-order polynomial as the basis function to fit and model the distribution of the overlay. The corresponding fifth-order polynomial decomposition model is expressed as follows:

δx(x,y) = k₁ + k₃·x + k₅·y + k₇·x² + k₉·xy + k₁₁·y² + k₁₃·x³ + k₁₅·x²y + k₁₇·xy² + k₁₉·y³ + k₂₁·x⁴ + k₂₃·x³y + k₂₅·x²y² + k₂₇·xy³ + k₂₉·y⁴ + k₃₁·x⁵ + k₃₃·x⁴y + k₃₅·x³y² + k₃₇·x²y³ + k₃₉·xy⁴ + k₄₁·y⁵, (1)

δy (x,y) = k₂ + k₄·y + k₆·x + k₈·y² + k₁₀·xy + k₁₂·x² + k₁₄·y³ + k₁₆·y²x + k₁₈·yx² + k₂₀·x³ + k₂₂·y⁴ + k₂₄·y³x + k₂₆·x²y² + k₂₈·yx³ + k₃₀·x⁴ + k₃₂·y⁵ + k₃₄·y⁴x + k₃₆·y³x² + k₃₈·y²x³ + k₄₀·yx⁴ + k₄₂·x⁵. (2)

In the equation, k_j(j = 0, 1,⋯, 41, 42) represents the controllable overlay compensation coefficients implemented via various actuators within the lithography system. (x, y) denotes the normalized intra-field coordinates of each exposure field. δx(x, y) and δy (x, y) represent the overlay in the x-direction and y-direction, respectively.

In the thermo-mechanical coupling module of the finite element software, the mathematical and physical models of the lithography system under the parameters listed in Table 1 are typically described using partial differential equations, including the heat equilibrium equation and the structural equilibrium equation. The heat equation governs the evolution of the temperature field, while the structural equation characterizes the resulting displacements and stress distributions caused by thermal variations. For the proposed high-order overlay compensation model, the thermo-mechanical coupling problem is formulated accordingly. Within the elastic deformation range of the mask, the overlay deformation induced by stress in this compensation scheme exhibits linear superposition behavior.²⁸ The mathematical formulation is as follows:

In the equations, α_i and β_i represent the contribution coefficients the n stresses f_i to the total stress in the x-direction and y-direction, respectively. E = FL/A·dL denotes the Young's modulus, and ν is the Poisson's ratio. δx_force and δy_force respectively represent the x-direction and y-direction overlay errors for the stress compensation around the mask. Except for the stress variables, all other parameters in eqn (3) and (4) are fixed coefficients, implying that the resulting overlay compensation exhibits a linear relationship with the input stresses. Furthermore, according to thermal deformation theory, within the elastic deformation range, the following can be derived:In the equation, γ denotes the mask thermal expansion coefficient, c is the specific heat capacity of the mask, ρ represents the mask density, and V = L_x·L_y·t represents the volume of m local heat input areas. δx_heat and δy_heat respectively represent the x-direction and y-direction overlay errors of pixel-level heat compensation within the mask lithography field. Accordingly, within the elastic deformation range of the mask, the proposed high-order overlay correction model can compensate the overlay errors within the lithography field as follows:

Table 1 Lithography simulation related parameters.^19,28

Parameter	Symbols	Value
Mask thickness (mm)	t	6.35
Density (kg m^−3)	ρ	2200
Young's modulus (Pa)	E	7.05 × 10^10
Poisson's ratio	v	0.164
Bulk modulus (Pa)	K	3.497 × 10^10
Shear modulus (Pa)	G	3.0284 × 10^10
Coefficient of thermal expansion (1/°C)	γ	4.6 × 10^−7
Isotropic thermal conductivity (W m^−1 °C^−1)	κ	1.38
Exposure absorption efficiency	η	20%
Convection coefficient (W (m^−2 °C^−1))	μ	10

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Combining eqn (1), (2), (7) and (8), where the parameters of each overlay compensation actuator serve as variables while all other parameters remain fixed coefficients, the high-order compensation model exhibits linear superposability between the generated overlay correction and the applied stress and localized thermal control doses.²⁸

2.3 The principle and method of high-order overlay compensation

The main procedure of this high-order overlay error correction model is illustrated in Fig. 2(a) and is fundamentally similar to the conventional overlay correction process used in traditional lithography tools. After completing the exposure and development of the current layer, overlay metrology is performed on intra-field overlay marks, and the measured overlay distribution is fitted using the high-order polynomial model. The resulting coefficients are then converted into actuator control parameters through the response mapping function, which correspond to distributed piezoelectric forces and localized thermal inputs. These parameters are applied to the mask stage before the next exposure step is initiated, so that the physical and thermal-induced distortions expected during the upcoming exposure are pre-compensated in advance. This predictive correction procedure is repeated for each wafer or lot, enabling continuous adaptation to dynamic process variations. The subsequent steps involve exposure, post-exposure overlay accuracy measurement, and, if necessary, repeated compensation cycles.

Fig. 2 The overlay compensation flowchart based on the high-order overlay correction model. (a) The flowchart for achieving overlay correction with this model. (b) The flowchart for establishing a high-order overlay compensation model.

The construction process of the fifth-order overlay correction model is illustrated in Fig. 2(b). To avoid destructive experiments, a rigorous finite element simulation is employed to establish the compensation model. The simulated overlay error data are subjected to statistical analysis. By extracting statistical features and ranking the significant weights of the high-order overlay parameters k, the modeling dimensionality can be significantly reduced. This not only simplifies the subsequent development of compensation strategies and the overlay error response function, but also reduces the overall modeling complexity. In this study, a least-squares-based parameter significance test is used to rank the influence of polynomial terms. This enables the identification of dominant terms that have a critical impact on compensation and the extraction of a representative set of compensation control parameters k, thereby improving the efficiency and robustness of the subsequent overlay compensation modeling.

First, a fifth-order polynomial model as defined in eqn (1) and (2) is constructed based on the input overlay distribution data. The estimation of the overlay parameters k is then obtained by minimizing the sum of squared deviations between the measured overlay errors and those predicted by the model.^19,28

Next, hypothesis testing is performed to evaluate the statistical significance of each overlay compensation parameter k_j in influencing the overlay, by assessing the corresponding P-values of the hypothesis tests for each parameter k_j.

Subsequently, the P-values are calculated based on the test statistics t_j obtained from the t-tests, which evaluate the statistical significance of each parameter:

where t̂j denotes the estimated value of the parameter k_j, and SE (k̂j) represents the standard error of the estimate. Based on the t-distribution and the computed t-value, the corresponding P-value is calculated as:

P_j = 2 × Prob(T > |t_j|). (13)

Then, based on the calculated P-values for the high-order overlay compensation scheme, the k parameters with P < 0.05 are selected to simplify the model. Finally, all statistically significant polynomial terms corresponding to the effective overlay compensation parameters from various correction schemes are aggregated and identified as the key polynomial components influencing the actual overlay error. A response mapping model is then established to describe the relationship between the dominant high-order overlay error parameters k_j and the specific control actions of the overlay compensation actuators.

k_j = f_j(p₁, p₂, …, p_n+m). (14)

Here, p_i represents the control parameters related to complex peripheral stresses and localized thermal fine-tuning around the mask, such as the magnitude of electromagnetic actuation forces and the dosage of localized thermal regulation. k_j denotes the response parameters corresponding to the key high-order polynomial terms of overlay error. This functional model can be utilized in a reverse manner to predict the specific actuator control parameters that must be applied by the lithography system in order to achieve a desired overlay error compensation target. In this way, an analytical solution for active compensation control can be obtained. This formulation enables predictive modeling and control of overlay error responses under varying stress and localized thermal modulation conditions.

Furthermore, this paper defines the processing formula for the correction ratio of the mask compensation:

where δ_ori and δ_res are the |mean| + 3σ value of the original overlay error and the after corrected point-by-point overlay residual, respectively. This metric reflects the percentage reduction of the overlay error variation achieved by the compensation method.

3. Simulation results and discussion

3.1 Compensation effect of each order overlay

Based on the previously described high-order overlay correction model, we conducted simulations to verify the reliability and feasibility of the proposed compensation approach. By employing a fifth-order polynomial decomposition of the overlay error, the simulation results are presented in Fig. 3. This figure illustrates various types of initial random overlay error distributions, the corresponding localized thermal effects, and complex peripheral stresses around the mask as calculated by the model. The residual overlay errors before and after compensation are evaluated on a point-by-point basis. As shown in the figure, the high-order overlay error correction model effectively reduces the overlay (|mean| + 3σ) to below 1 nm. Specifically, for linear and second-order overlay distributions, the model achieves near-complete correction, with residual overlay (|mean| + 3σ) as low as 0.1 nm. In comparison, it is significantly superior to the effect of a certain third-order lithography correction method.²⁸

Fig. 3 The compensation effect of the high-order overlay correction method is simulated randomly under different initial overlay error distributions.

For 3rd-order and 4th-order overlay error distributions, the proposed model is also capable of achieving more than 80% correction rate, with the residual overlay error reduced to approximately 0.5 nm. Furthermore, for 5th-order overlay error distributions, the model still achieves a correction rate of 68.16%, with residual overlay less than 0.4 nm, demonstrating strong reliability. It is worth noting that for conventional DUVL systems, reliable correction of 3rd-order and higher-order components is often unachievable due to the limited degrees of freedom in optical lens-based compensation mechanisms. In summary, the proposed high-order overlay compensation model demonstrates effective correction performance across various types of random overlay distributions.

3.2 Average correction of the overlay

To more comprehensively evaluate the process reliability and stability of the proposed high-order overlay error correction model, we conducted multiple validation tests using fifth-order polynomial-based intra-field overlay correction. The compensation performance for randomly generated 5th-order overlay errors—each consisting of 42 k parameters—is shown in Fig. 4. As indicated by the dashed average lines in the figure, the model achieves an average correction rate of 96.85% in the x-direction and 97.36% in the y-direction across 40 high-order overlay distributions. Additionally, the results from individual compensation instances show that the correction rate consistently remains above 95%, with only a few cases dropping to around 90% due to the presence of stronger high-order components.

Fig. 4 The average correction effect of the overlay error. (a) The compensation effect in the x-direction after several random overlay compensations. (b) The compensation effect in the y-direction after several random overlay compensations.

3.3 Verification and analysis of overlay compensation in the actual process

To further assess the practical performance of the proposed high-order overlay error correction method, we conducted validation and analysis using overlay error data collected from within the exposure fields of actual fabrication processes. These data were obtained from real wafer manufacturing environments and reflect the true distribution characteristics of overlay errors under complex industrial conditions. This evaluation aims to determine the compensation quality of the high-order correction model in practical applications.

Fig. 5 illustrates the overlay distribution at a specific wafer location in a real fabrication process, along with the corresponding compensation results obtained using the proposed high-order correction model. As shown in Fig. 5(a), the actual overlay distribution from the manufacturing process was fitted using a fifth-order polynomial, with the resulting fitted distribution presented in Fig. 5(b). Notably, Fig. 5(c) shows the residuals between the actual overlay errors and the fifth-order polynomial fit, with the (|mean| + 3σ) residual overlay errors measured at 3.87 nm in the x-direction and 5.43 nm in the y-direction. This indicates that, under a fifth-order compensation scheme, 15.70% and 30.15% of the intrinsic overlay in the x and y directions remain uncompensated. Without incorporating correction mechanisms beyond the fifth order, these residual errors can be considered random and are beyond the compensation capability of current lithography systems. By inputting this data into the proposed high-order correction model, the resulting spatial distribution of the compensation mechanism is shown in Fig. 5(d), and the corresponding corrected overlay distribution is depicted in Fig. 5(e). Fig. 5(f) presents the point-by-point residual overlay map after applying the high-order mask-based correction model in an actual process environment, demonstrating effective compensation rates of 82.87% in the x-direction and 65.27% in the y-direction. The residuals in the x and y directions are 6.71 nm and 6.21 nm, respectively. As a result, the residual overlay errors were reduced to 4.22 nm and 6.26 nm in the x and y directions, respectively. If a third-order polynomial is employed for compensation, Fig. 5(g) represents the inherent overlay residual distribution. The corresponding overlay distribution after third-order compensation is shown in Fig. 5(h), while Fig. 5(i) illustrates the point-by-point overlay residuals before and after correction. Compared with the third-order overlay compensation model, the fifth-order overlay correction model can effectively reduce the overlay in the x-direction. However, the improvement in the y-direction is not significant. Therefore, in practical processes, the selection of the model should be based on the randomness of overlay data to avoid excessive overlay compensation.

Fig. 5 The distribution of overlay errors in actual processes and the compensation map of this high-order overlay correction model. (a) The overlay distribution within a field of an actual process wafer; (b) the fitting results of the actual overlay errors using a 5th-order polynomial; (c) the residual distribution of overlay errors between the actual process and the 5th-order polynomial fit; (d) application of the correction scheme calculated by the high-order overlay compensation model; (e) the distribution of overlay errors that can be compensated by this model; (f) the compensation residual distribution between the high-order overlay correction model and actual overlay errors; (g) the residual distribution of overlay between the actual process and the 3rd-order polynomial fit; (h) the overlay distribution map using 3rd-order overlay compensation; (i) the overlay residual map using 3rd-order overlay compensation.

3.4 Analysis of limit correction for overlays based on the k parameter

To provide a more intuitive understanding of the compensation performance of the proposed high-order intra-field overlay control method across different types of overlay distributions, Fig. 6 presents the overlay error compensation results for expansion-induced and shrinkage-induced errors of various polynomial orders. In the figure, the red bars represent the initial overlay errors without any correction (i.e., the randomly generated error distributions), while the blue bars indicate the residual overlay errors after applying the proposed high-order compensation method. It can be observed that, for both expansion and shrinkage overlay effects, the method achieves over 97% correction rate for linear and 2nd-order components. By comparing Fig. 6(a) and (b), we note that the compensation performance for shrinkage-induced errors is comparable to that for expansion-induced errors across all orders. Notably, the compensation results for 4th-order overlay errors outperform those for 3rd-order and 5th-order distributions, with residual overlay errors reduced to approximately 6.11% after compensation.

Fig. 6 Diagram of the compensation effects for the overlay of each order. (a) The compensation effect diagram of the overlay for various orders of expansion effects. (b) The compensation effect diagram of the overlay for various orders of shrinkage effects.

To further analyze the ultimate performance limits of the proposed overlay compensation method, each of the 42 fifth-order polynomial k-parameters was individually evaluated for compensation performance, as illustrated in Fig. 7. This figure enables a quantitative assessment of the compensation capabilities for different k-parameter distortions, providing insight into the model's ability to address overlay errors arising from both expansion and shrinkage effects. As shown in Fig. 7(a), for expansion-induced overlay errors, the compensation efficiency exceeds 95% for all overlay components associated with 2nd-order or lower k-parameters. However, for high-order components, particularly those corresponding to K15, K17, K19, K20, K28, K33, K38, K40, K41, and K42, residual point-by-point overlay errors remain above 20%. Notably, for the expansion effect, the residual overlay errors for K19, K20, K38, K41, and K42 are 30.35%, 33.33%, 32.97%, 52.11%, and 49.01%, respectively, indicating that the proposed high-order compensation method is ineffective in fully correcting these five specific k-components. It is worth noting that similar to commercial lithography systems such as ASML's framework, certain high-order k parameters remain beyond the compensation capability of the current actuator configuration due to physical constraints, including thermal–mechanical coupling nonlinearities and actuator spatial resolution limits, etc. Under the present model architecture, the method can stably compensate overlay components up to approximately the 4th–5th polynomial order.

Fig. 7 Correction effect diagram of the high-order correction model under the k-parameter limit case. (a) The overlay compensation effect of the expansion effect under the k-parameter limit. (b) The overlay compensation effect of the shrinkage effect under the k-parameter limit.

Similarly, the compensation performance for shrinkage-induced overlay distributions is illustrated in Fig. 7(b), which presents the corresponding compensation limits. Using the proposed high-order correction approach, residual overlay exceeding 20% remains for the shrinkage-related components K16, K19, K20, K27, K28, K30, K34, K37, K38, K41, and K42. Notably, the model fails to effectively correct K20, K38, K41, and K42, indicating limited compensation capability for these components under shrinkage-dominated overlay conditions.

4. Conclusion

This study addresses the challenge of high-order overlay error correction in advanced lithography by proposing a compensation solution based on high-order polynomial modeling. The aim is to enhance the overall performance and reliability of IC manufacturing. The paper begins by analyzing the origins of overlay errors in modern IC fabrication processes and introduces a high-order overlay correction model, which employs a two-dimensional fifth-order polynomial to fit and characterize the spatial distribution of overlays. The process flow of the proposed correction method is then described, followed by a detailed explanation of the mathematical modeling procedure. Finally, the reliability and feasibility of the high-order overlay correction model are validated through multiple simulations, demonstrating its consistency and robustness.

Simulation results demonstrate that the proposed model effectively reduces overlay errors, bringing the value of |mean| + 3σ below 1 nm. For linear and 2nd-order overlay distributions, the model achieves complete correction, with residual errors less than 0.1 nm. For 3rd-order and 4th-order distributions, more than 80% of the overlay can be corrected, with residuals around 0.5 nm. Furthermore, for 5th-order overlay distributions, the model achieves a correction rate exceeding 68.16%, with residual errors under 0.4 nm. Across multiple randomized simulations, the model shows an average compensation efficiency of 96.85% in the x-direction and 97.36% in the y-direction. In practical manufacturing scenarios, the model effectively compensates for overlays observed on actual wafers, reducing the |mean| + 3σ metric to 4.22 nm and 6.26 nm in the x-direction and y-direction, respectively. In addition, the compensation performance under extreme high-order overlay distributions was investigated. Although certain k-parameter components still exhibit residual overlay errors, the overall correction performance remains significant, demonstrating the model's robustness and applicability in high-precision overlay control.

In conclusion, the high-order overlay correction model proposed in this study offers an effective solution for compensating overlay errors in advanced lithography processes. While some residual errors remain under certain high-order k-parameter components, the model has demonstrated strong adaptability and stability in practical manufacturing environments. Looking forward, the integration of more complex stress modeling, finer localized thermal corrections, and AI-driven real-time compensation systems is expected to further enhance the accuracy and robustness of the approach, thereby supporting the manufacturing demands of future technology nodes with tighter overlay requirements.

Conflicts of interest

The authors declare no conflicts of interest.

Data availability

Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.

Acknowledgements

This work was supported by Frontier Technology Collaboration Project (QYJS-2023-2900-B), Strategic Priority Research Program of Chinese Academy of Sciences (XDA0330303), University of Chinese Academy of Sciences (118900M032), and Fundamental Research Funds for the Central Universities (E2ET3801).

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