High on/off ratio SiO₂-based memristors for neuromorphic computing: understanding the switching mechanisms through theoretical and electrochemical aspects

Abstract

Memristors have emerged as promising elements for brain-inspired computing applications, yet the understanding of their switching mechanisms, particularly in valence change memristors, remains a topic of ongoing debate. We report on the SiO₂-based memristors, demonstrating a high on/off ratio (>10⁵). Particularly, this study aims to enhance the fundamental understanding of switching behaviors and mechanisms. Our approach involved an extensive investigation using finite element analysis to provide visual insights into the conductive path evolution in these memristors over the set/reset bias cycle. Electrochemical impedance spectroscopy experimentally validated the theoretical investigations by interpreting the switching behavior through the lens of the equivalent circuit. In addition, we evaluated synaptic characteristics and incorporated them into neural networks for image recognition tasks with MNIST and fashion MNIST datasets. Our comprehensive exploration of both the underlying principles and potential applications is of practical relevance to studies that aim to realize and implement SiO₂-based memristors in neuromorphic computing.

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Introduction

The silicon (Si) microelectronics research and industry promisingly consider memristors a promising contender in emerging memory technologies. This increasing interest in memristors is attributed to their potential performance advantages, including lower power consumption and higher scalability, compared with other non-volatile memory technologies such as FeRAM (ferroelectric RAM) and MRAM (magnetoresistive RAM).¹ These distinct characteristics of memristors position them as a compelling choice for implementing in-memory computing, offering a path to challenge and potentially revolutionize traditional Von Neumann architectures.

A wide range of oxide materials, from semiconductors to high-k materials, including InGaZnO,² SiO₂,³ HfO₂,⁴ and TaO_x,⁵ have been reported to serve as switching layers in memristors. The majority of materials utilized in memristors are either expensive to grow or only partially compatible with the prevalent Si-based complementary metal–oxide semiconductor (CMOS) manufacturing process. Historically, SiO₂ has been one of the most extensively researched dielectric materials, largely due to its direct growth capability out of Si.⁶ However, much of this research has been centered around the destructive and irreversible dielectric breakdown for traditional CMOS and very large-scale integration (VLSI) technologies.⁷ Recently, a shift in focus has been noted within the memristor field, as SiO₂ has demonstrated reversible soft breakdown behaviors, also known as resistive switching.^3,8 This has prompted an increase in interest and research into the potential applications of SiO₂ within the realm of memristor technologies.⁹

Memristors based on SiO₂ have been investigated and reported with an achieved performance of on/off ratio of 10²–10⁵.^8b,10 Bilayer structure (SrTiO₃/SiO₂¹¹) was demonstrated for realizing stable switching through engineering different ion transport rates in these two layers where the role of SrTiO₃ is to confine filament growth. Nanorods of SiO₂ were also investigated to lower the firing energy for an artificial neuron.¹² The use of columnar growth in silicon oxide was leveraged to create defect-rich sites at the column edges, resulting in low variability.^10b To further advance the development, it is crucial to fundamentally understand SiO₂-based memristors’ switching mechanisms, which in turn will provide insightful engineering criteria to address the challenging issues above. Thus far, the oxidation-reduction (redox)-based switching mechanisms have been suggested and categorized into two mechanisms, depending on the composition of the conductive filaments: electrochemical metallization mechanism (ECM) and vacancy-associated valence change mechanism (VCM). In an ECM device, Cu or Ag is widely chosen as an active electrode which can be partially oxidized and then reduced to form the metallic filaments.¹³ On the other hand, the conductive path of VCM devices relies on the generation and accumulation of oxygen vacancies.¹⁴ The evolution of conductive filaments in the ECM memristors has been evidenced through transmission electron microscopy (TEM),¹⁵ and this work enhanced understanding of the switching behavior of ECM and PCM memristors.¹⁴ However, the direct visualization of conductive filaments in VCM-based memristors is rarely reported due to the technical difficulties,¹⁶ for example in TEM characterizations, of low image contrast between oxygen-rich and -deficient regions in TEM characterizations, which makes the VCM switching mechanism remain controversial.¹⁷

In this work, we selected SiO₂ as the switching element for memristor applications. To solely limit the contributing charge carriers to oxygen vacancies for the switching behavior, an inert metal Pd was employed as the top electrode. The dynamic evolution of oxygen vacancy conductive filaments in the SiO₂-based memristors was mechanistically visualized by a numerical solver, which delineates a selective growth process and the inhibition effect exerted on filaments nearby the established dominant paths. The equivalent circuit interpretation from non-destructive electrochemical impedance spectroscopy (EIS) measurements supplementarily corroborated our theoretical understanding about the switching mechanism. Importantly, our SiO₂-based memristor can be considered as the weights in artificial neural networks (ANNs) because it exhibited multi-conductance phenomena in response to pulse train stimuli. Given these synaptic characteristics, our SiO₂-based memristors were incorporated into a neural network for image processing tasks, benchmarking with MNIST and fashion MNIST datasets. Our fundamental studies and concept validation may propel advances in SiO₂-based memristors, pushing the boundaries towards real-world neuromorphic computing applications.

Results and discussion

Fig. 1a is a schematic illustration of a SiO₂-based memristor in a vertical configuration. The top electrodes were defined using in situ shadow masks during the fabrication, of which the circular pattern diameters vary from 150 to 300 μm with a 50 μm increment. A cross-sectional high-angle-annular dark-field (HAADF) TEM micrograph of the SiO₂ memristor is false-colored and exhibited in Fig. 1b. A vertical memristor structure consisting of top (Pd, ∼100 nm) and bottom (heavily-doped Si) electrodes and switching layer (SiO₂, ∼20 nm) between the electrodes was clearly identified. An associated energy-dispersive X-ray spectroscopy (EDS) mapping image in Fig. 1b indicates the major elements of each layer of the memristor, indicating a clear interface between layers without interdiffusion. In the high-resolution TEM images (Fig. 1c), distinct morphological features are evident: the TE/SiO₂ interface exhibits protrusions approximately 1 nm in size (Fig. 1c1), while the SiO₂/BE interface is characterized by a notably flat surface (Fig. 1c2). A false-colored SEM image of the Pd top electrodes with diameters of 200 and 150 μm is displayed in Fig. 1d and a magnified image of a 150 μm Pd top electrode is shown in Fig. 1e. The typical vertical memristor structure is technically the same as that of a capacitor and particularly the characteristics of the high-resistance state are governed by the dielectric performance of the switching layer (SiO₂ in this study). To evaluate the dielectric property, as an initial figure of merit, of the switching layer and the devices, capacitance–voltage (CV) measurements were conducted on SiO₂-based memristors as a function of switching layer thicknesses and top electrode size within a voltage range from −2 V to 2 V under 1 MHz. The CV results from the 5 nm SiO₂ switching layer are summarized in Fig. 1f. Overall, the capacitance of 5 nm SiO₂-based memristors is at 10⁻¹⁰ F level. From the C–V measurements, the capacitance densities of the SiO₂ switching layers with different TE sizes are comparable to each other, approximately 3.5–4.2 fF μm⁻². The relative permittivity extracted from the resulting sputtered SiO₂ is 3.3, which is close to the reference values 3.7–3.9.¹⁸ The slightly lower value may be resulted from the room temperature sputtering condition and mild annealing temperature (550 °C), compared with the reference values obtained from high temperature (1000–1200 °C) thermal oxidation.

Fig. 1 Pd/SiO₂/P⁺⁺Si memristors: (a) schematic illustration of device structure of SiO₂-based memristor with Pd TE and heavily-doped Si BE. (b) A false-colored cross-sectional HAADF-TEM micrograph, and associated EDS elemental mapping of a Pd/SiO₂/P⁺⁺Si memristor. (c) High resolution TEM images to reveal the morphology of (c1) the TE/SiO₂ interface, showing ∼1 nm protrusions and (c2) the flat SiO₂/BE interface. (d) A false-colored SEM plan-view image of the top electrodes with diameters of 200 μm and 150 μm, and (e) an extended image for the typical size 150 μm. (f) C–V measurements at 1 MHz for 5 nm-thick SiO₂-based memristor with various TE diameters (300, 250, 200 and 150 μm).

The electrical characteristics of SiO₂-based memristors were examined by cyclic DC sweeping. The electrical biases were always applied on the palladium top electrode and the P⁺⁺ Si bottom electrode was grounded. The sweeping bias ranged from −5 V to 7.5 V with a starting voltage of 0 V, and a compliance current (I_cc) was set at 60 μA during the positive sweeping. Fig. 2a shows the current–voltage (I–V) property of a 5 nm-SiO₂ switching layer memristor, including consecutive 100 cycles of DC sweeping curves with the same measurement parameters. The I–V sweeping curves appear as a butterfly shape which is a typical pattern for a bipolar memristor.²¹ The bipolar switching resulted from the formation (with positive biases) and annihilation (with negative biases) of the filament, caused by field induced oxygen vacancy migration with alternating opposite directions of bias application.¹⁹ This is different from the unipolar switching which has been proposed, where the annihilation of the filament is achieved by Joule heating using a consistent bias direction.²⁰ When the bias increased from 0 V to 7.5 V, abrupt current jumps were observed which indicates a conduction filamentary SET process, i.e., a transition from high resistance state (HRS) to low resistance state (LRS). And the transitions (turn on) mostly happened at a voltage ranging from 4 V to 6 V. The LRS was maintained during the sweeping from 7.5 V to 0 V and subsequent 0 V to negative bias. It should be noted that the turn-on voltage of the first cycle of DC sweeping was ∼6 V which was applied on the top electrode (Pd). From the SET voltage statistics distribution in Fig. 2f (bottom for 5 nm thick SiO₂), it is on the maximum side, but not too far from the medium/mean value of ∼5 V. Thus, we can consider our device to be a near-forming free device, which is defined as the initial SET voltage of the device is similar to the subsequent SET voltages.²¹ During the negative voltage sweeping, a current level drop was observed which means the cell was turned back to HRS, a RESET process was finished (i.e., off state). The current values at a read voltage of 0.3 V for each sweeping cycle were extracted from the I–V curves, then converted to resistance values and plotted as resistance versus cycle number to yield the endurance performance of the device exhibited in Fig. 2b. The results demonstrate that no deterioration in HRS and LRS during continuous cycling was observed, indicating reasonable endurance of the SiO₂-based memristor. A large memory window, i.e., on/off ratio, is clearly observed as high as >10⁵. To characterize the on/off ratio more quantitatively, the cycle-to-cycle statistical distributions of HRS and LRS are demonstrated in Fig. 2c. At the cumulative probability of 50%, the notable high on/off ratio is further validated as ∼1.4 × 10⁵. The achieved high on/off ratios are attributed to the low off-state current and the high on-state current. The low off-state current behavior mainly depends on the intrinsic quality of the switching layer (i.e., dielectric property). As the capacitance–voltage characteristics are provided in Fig. 1f, our sputter-processed SiO₂, followed by air annealing, demonstrates decent dielectric performance, comparable (or slightly less) to bulk and thermally grown SiO₂. Therefore, our SiO₂-based memristor achieved an off-sate current as low as on the order of 10⁻¹¹–10⁻¹⁰ A. For the on-state behavior, various parameters are related to the overall on-state property, such as the intrinsic characteristics of the switching layer, thickness, and the transport behavior of the charged carriers (oxygen vacancy in this case), and hence the resulting conductivity of the filament. In addition to these intrinsic and processing parameters of the materials and device, a measurement parameter of the compliance current (I_cc) is also an important factor in determining the on/off ratio, as it limits the maximum current flowing through the device. This not only prevents the device from experiencing a hard breakdown but is also proposed to control filament growth.²² With I_cc = 60 μA in our study, the conduction filament, once formed, has sufficient conductivity (Fig. S1 in the ESI†) to achieve a relatively high on-current, thereby exhibiting resistive behavior. Furthermore, the regulated filament can be near-fully ruptured during the RESET process to get the low current again, contributing to the high on/off ratio.²³ To assess the stability of our device, the retention characteristics were evaluated with a read voltage 0.3 V at an evaluated temperature 85 °C. As depicted in Fig. 2d, both the LRS and HRS show a prolonged retention time of 10⁴ seconds. In regard to the device-to-device variation, all the processing parameters and annealing environment are carefully controlled and monitored for the processing of our SiO₂ memristors, to minimize any processing variations and hence the possible performance variations. The performance of our SiO₂-based memristors slightly varies among the devices and particularly the on/off ratio is found to be reasonably consistent as shown in Fig. 2e, demonstrating 0.9–1.6 × 10⁵. Additionally, the SET voltage exhibits very small device-to-device variation of 2.90% (Fig. S2, ESI†). This device-to-device evidence, in conjunction with previous cycle-to-cycle tests, underscores the reasonable reliability of our devices. To evaluate the effect of the thickness of the SiO₂ layer, similar electrical characterizations were also carried out on 10 nm, 20 nm, and 30 nm SiO₂ switching layer memristors. The I–V characteristics for these switching layer thicknesses can be found in Fig. S3 (ESI†). It is observable that devices with thicker switching layers require a higher voltage for stable resistive switching. The SET voltages are statistically summarized in Fig. 2f. A clear quantitative trend is confirmed, indicating that SET voltage increases with the thickness of the switching layer. The difference in SET voltage between the 5 nm and 30 nm SiO₂ devices is approximately 9 V. From a practical perspective, thinner SiO₂-based memristors offer higher energy efficiency. Fig. 2g compares the on/off ratio of the present study with those available in the literature. For objective comparisons, the other two widely-considered oxides of TaO_x (as Work 4,²⁴ 5,²⁵ and 6²⁶) and HfO_x (as Work 7,²⁷ 8,²⁸ and 9²⁹) are also included in Fig. 2g as well as SiO_x (as Work 1,^10e 2,³⁰ and 3³¹). The achieved on/off ratio of >10⁵ from our SiO₂ memristors outperforms those (∼10¹–10⁴) of state-of-the-art HfO_x- and TaO_x-based memristors. In addition to the on/off performance, the unit price of these switching materials is also compared. Due to the abundance, SiO₂ is significantly cost-effective (100–700 times lower) than the other competitors.³² In order to make our comparison more comprehensive, we compared the endurance and retention in our work with those in other literature. The comparisons are presented in Table S1 (ESI†), where our device exhibits reasonable reliability, in terms of both endurance and retention, demonstrating on the order of 10² cycles and 10⁴ s.

Fig. 2 (a) I–V characteristics of the Pd/SiO₂ (5 nm)/P⁺⁺-Si memristor in semi-log scale, where arrows, labeled in alphabetical order, indicate HRS, SET, LRS, RESET, and HRS, respectively. (b) Endurance graph for 100 cycles, two distinct HRS and LRS remain without damping. The resistance values at HRS and LRS are recorded at a read voltage of 0.3 V. (c) Statistical distribution of resistance at HRS and LRS, from which the on/off ratio is extracted to be ∼1.4 × 10⁵ at a cumulative possibility of 50%. (d) The retention characteristics of 5 nm SiO₂ memristor at LRS and HRS, examined at 85 °C, exhibit reasonably good performance. (e) The statistical distribution of R_HRS and R_LRS for 5 different devices. The on/off ratios were obtained by using the same method in (b). Similar high on/off ratios of ∼10⁵ are obtained from all the devices. (f) Statistical distribution SET voltages for different thicknesses of SiO₂ switching layers. (g) Comparison of the on/off ratio of the present study with those from the literature. (h) Analysis of electric transport processes of the SiO₂-based memristor in log–log scale.

To analyze electric transport processes, the linear scale I–V curve in Fig. 4a was replotted in double-log scale in Fig. 2h to examine the power law behavior between the current and voltage (i.e., I ∝ V^m). During the HRS, the curve exhibits three regimes where m ≈ 1, m ≈ 2, m > 2, representing ohmic, trap-unfilled (Child's square law), and trap-filled regimes, respectively, according to the well-known space-charge-limited conduction (SCLC) mechanism, describing the electric conduction process in a memristor.¹⁴ During the LRS, the linear fitting slope is close to one with a R² = 0.999, indicating the ohmic conduction mechanism (Fig. S4 shows other conduction mechanisms exhibit inferior fits, ESI†), which is widely considered to be attributed to the formation of a conductive filament bridging the TE and BE in a metallic-like way.³³ Additionally, our area effect study in Fig. S5 (ESI†) shows that the current levels in the LRS do not significantly vary with the size of the electrode, suggesting the presence of filamentary conduction.^10e,34 And the results in Fig. S6 (ESI†) for the temperature effect investigation show that the resistance values increase along with the increase in temperature, a metallic characteristic, indicating the filament is established at LRS.³⁵ These electric transport, area effect, and temperature effect studies synergistically support that our SiO₂-based memristors depend on the filamentary switching mechanism, which is further validated by the FEA (Fig. 2) and EIS (Fig. 4c) investigations in our study.

In order to enhance the fundamentals of the switching process through the evolution and rupture of an oxygen vacancy-based conduction filament as well as to complement the macroscale electrical and electrochemical measurements, we performed a series of FEA analyses as a function of applied bias. The physical modeling details are elaborated in Note S1 (ESI†). It should be noted that the switching behavior of the memristor in this study is governed by oxygen vacancies (i.e., VCM) due to the inert Pd (TE) and stably covalent-bonded Si (BE), which indicates that no electrode-related ions are involved in the conduction. A Multiphysics-fields coupled model, which describes the diffusion and drift flux of the at the nanoscale, was adopted to study the switching process of the memristor. Several protrusions at the top electrode with various radii (r₁ = 0.3 nm, r₂ = 1.2 nm) were considered to reflect the roughness of the TE/SiO₂ interface (Fig. 1c1). There is no chemical or structural difference between protrusions and top electrode Pd. In the left of Fig. 3a–d, the overall intensity of n_D/n_D0 (concentration ratio of at current stage to at original stage) gradually increased from stage I to stage IV over the course of SET process, indicating the concentration of was augmented in the turn-on process with increasing bias. Compared with the flat region and small protrusions on the top electrode, the protrusions with the larger radius have higher concentrations of , and exhibit a higher intensity of n_D/n_D0, which suggests that the is preferentially concentrated at larger protrusions. This concentration difference can be explained by the variation in the electric field, induced by the intrinsic roughness of the TE/SiO₂ interface. The significantly enhanced localized electric field under the large protrusion, as confirmed in the middle of Fig. 3a–d, tends to attract more to regions under the protrusions with larger radius.³⁶ Thus, our FEA analysis indicates that the selectively distributed may limit the random growth of the conduction filaments. This provides an insight for engineering memristors that implementing well defined protrusions may mitigate the issue regarding performance variation of memristors. The bright regions under larger protrusions at stage IV became redder and wider compared with stage III, which implies that the formed conduction filament would grow thicker. Associated schematics at each stage that elaborate the SET process are also shown on the right of our simulation results. When a positive bias is applied to the Pd TE, oxygen ions (O²⁻) are pulled away from the switching matrix by the external field, migrating towards the Pd TE.³⁷ This leads to the simultaneous generation of positively charged oxygen vacancies . In general, this process is often described by the motion of the corresponding oxygen vacancies, i.e., the positively charged oxygen vacancies migrate towards the grounding BE and subsequently accumulate there, forming a conductive filament that bridges the TE and BE.³⁸ Upon arriving at the Pd TE, the oxygen ions are oxidized to O₂ and accumulate around the TE/SiO₂ interface.^17a,39 The models with different thicknesses of the switching layer were simulated as well (Fig. S7–S9, ESI†). The calculated results are consistent with the model with the SiO₂ layer of 5 nm except for the turn-on voltage applied to the top electrode was increased which was led by the thicker SiO₂ layer in the models.

Fig. 3 The FEA visualization and schematic elaboration for the evolution of conductive filaments at (a) stage I, where small positive bias for DC sweeping is initially introduced on TE of the device, positively charged oxygen vacancies are migrating towards BE; (b) stage II, where the magnitude of sweeping DC voltage is increasing, oxygen vacancies start accumulating at BE; (c) stage III, with voltage increasing continuously, the conductive filaments are growing; (d) stage IV, after a SET voltage applied, the conductive filaments are connecting the bottom and top electrodes, where the protrusion radii are r₁ = 0.3 nm, r₂ = 1.2 nm.

EIS is instrumental in acquiring a deeper understanding of the fundamental electrochemical mechanisms through the evaluation of impedance variations at various sinusoidal frequencies and resulting equivalent circuit interpretation.⁴⁰ Since redox-based memristors’ switching behaviors are reliant on electrochemical reactions, this non-invasive EIS technique provides a unique way to characterize and perceive memristors’ switching behavior.^40b,41 Thus, the EIS measurement was carried out on SiO₂-based memristors. To directly interpret the EIS results on an associated equivalent circuit model, the I–V characteristics of memristors (5 nm SiO₂) were rearranged on a linear–linear scale in Fig. 4a. The green part of Fig. 4a shows I–V characteristics in a linear–linear scale for the initial high resistance state of the memristor. The EIS measurement was employed on the memristor at this state. And the resulting Nyquist plot (left; green) in Fig. 4b, exhibiting a straight line (parallel to the y-axis) supports the capacitive property of HRS of memristors. Based on the simulation, the equivalent circuit at this state consists of a resistor R_c at 10² Ω level and a capacitor C_s at 10⁻¹⁰ F level, connected in series. The resistance at this state of the resistor is attributed to contact resistance.⁴² The capacitance value is aligned with our CV measurement from pristine devices (Fig. 1f). And this capacitive property at the “initial state” is conceptually explained in the right part of Fig. 4a: the structure of a memristor at the initial state is the same as that of a capacitor and there are few native oxygen vacancies in the SiO₂ switching layer. After turning on the memristor, i.e., at the state of Fig. 4a in the orange color period, an EIS measurement was repeated on the SiO₂-based memristor to understand the on-state conduction behavior of the memristor. A clear semicircle in the Nyquist plot is observed in Fig. 4c (middle; orange). Compared to the equivalent circuit at the initial state, a new resistor (R_f) at 10⁵ Ω level appears in the equivalent circuit at LRS, and it is connected to the capacitor in parallel. The new resistance value (∼10⁵ Ω) is aligned with the value measured in the I–V DC sweeping at LRS (Fig. 2a–c). Therefore, the emerged resistor (R_f) in the equivalent circuit represents the filament(s) in the switching layer which was validated by the electric transport investigations in Fig. 2h (i.e., Ohmic conduction mechanism at LRS). This EIS result complementarily supports the switching behavior suggested by the FEA analysis. At the same time, the majority portion of the memristor is still not connected with the conduction paths, thus, the capacitor component remains in the equivalent circuit. For simplicity, only one conductive path is illustrated in the schematic in Fig. 4a to elucidate the LRS. A RESET process changed the LRS of the memristor back to HRS, as shown in the blue portion of the I–V curve in Fig. 4a. The device was turned off and showed the capacitor behavior with a negative bias, similar to the previous HRS state. The EIS measurement in Fig. 4d (right; blue) also verified the HRS of the memristor where a vertically straight line appeared in the Nyquist plot again. The simulated equivalent circuit returns to a configuration of one resistor and one capacitor in series, with values at the same level as the initial state. This capacitive behavior at HRS (after RESET) indicates that the conduction path was almost completely dissolved (schematically described in Fig. 4a right; blue), and the capacitor symbol describes the state of high resistance of the memristor. The annihilation of filaments can be ascribed to the back motion of oxygen ions under a reverse bias which in turn causes the recombination of oxygen ions and vacancies. Since the filament was regulated by compliance current, it can be near-fully ruptured during the RESET process. Thus, our EIS results on the capacitive properties at initial and after-RESET HRS validate the near forming-free behavior of our memristors as well. Additionally, the EIS measurements at LRS were conducted on SiO₂-based memristors featuring varying device areas (Fig. S10, ESI†) and different thicknesses of switching layers (Fig. S11, ESI†). Their Nyquist plots uniformly exhibit semicircular shapes, which corroborates the area effect study shown in Fig. S5 (ESI†) and the FEA in Fig. S7–S9 (ESI†), affirming the filamentary switching mechanism.

Fig. 4 (a) A typical cycle of I–V characteristics from 5 nm SiO₂-based memristors is shown in a linear–linear scale. The initial HRS, LRS (SET), and HRS (RESET) are colored with green, orange, and blue, sequentially. These three states are schematically explained on the right: the initial HRS of the device has a small number of intrinsic oxygen vacancies (white ball shapes). At LRS, an oxygen vacancy-based conductive filament is well established, connecting the TE and BE. At the HRS resulting from RESET, the conductive filament is dissolved, and fewer oxygen vacancies are present again. (b) A Nyquist plot from EIS measurements on initial HRS of SiO₂-based memristors, of which the vertical line shape (parallel to the y-axis) indicates the pseudo-pure capacitive property. Based on the simulation, the equivalent circuit consists of a resistor in series with a capacitor, and it is displayed in the upper right corner. (c) A semicircle shape appears in the Nyquist plot at LRS. Another resistor is paralleled with a capacitor in the simulated equivalent circuit. (d) The Nyquist plot at HRS after RESET becomes a straight-line shape again. The associated equivalent circuit is back to a series connection of one resistor and one capacitor.

As a two-terminal device, memristors, consisting of a switching layer and two electrodes in a simple sandwich structure closely resemble the structure of a chemical synapse in the brain. This similarity is demonstrated schematically in Fig. 5a, particularly in the orange dashed circle for the synapse and the blue dashed circle for the memristor. The synaptic cleft corresponds to the switching layer of the memristor, while the pre-synapse and the post-synapse correspond to the top electrode and the bottom electrode of the memristor, respectively.

Fig. 5 (a) The process for signal transportation between neurons. The structure and function of the synapse in this process are illustrated in the dashed orange circle (left). In the dashed blue circle (right), the synapse is schematically embedded into the SiO₂-based memristor to demonstrate the similarity between them. Next, a SiO₂-based memristive crossbar prototype is exhibited towards neuromorphic computing. Finally, a neural network for image recognition is explained with instances from MNIST and fashion MNIST data sets (b) the synaptic characteristics evaluated from SiO₂-based memristors with 50 identical positive pulses and 50 identical negative pulses, demonstrating gradual variations of the conductance. The model accuracy examinations with (c) MNIST and (d) fashion MNIST as a function of epochs on test sets.

In the signal transmission process from one neuron to the next, as illustrated in Fig. 5a, the action potential (i.e., pulse bias in memristor operation) is first transferred from the soma to the end of the neuron (i.e., the presynaptic neuron) via the axon.⁴³ Then, from the presynaptic neuron, synaptic weights are altered by the release of neurotransmitters. This neurotransmission process leads to the dynamic modulation of synaptic connection intensity. Our SiO₂-based memristor can mimic this synaptic behavior by tuning the conductance level with electrical pulses. The mechanism of updating weights for SiO₂-based memristor is similar to a chemical synapse, in which the oxygen vacancies function like neurotransmitters, forming a conductive path in the switching layer (i.e., connecting the top and bottom electrodes) and changing the conductance level of the device.⁴⁴ A proposed SiO₂-based memristor crossbar prototype is illustrated in the upper right corner of Fig. 5. Such crossbar structure features two sets of wire electrodes, categorized as word lines (WLs) and bit lines (BLs). At each junction where these wires intersect, a resistive switching layer is present. Voltage pulses are fed through WLs then traverse through synaptic crossbar and converge at the BLs. The resulting output current is a function of both the initial input voltages and the conductance properties of the memristors in the crossbar, as described by Ohm's and Kirchhoff's laws.⁴⁵ We should note that the practical large-scale crossbar may experience disturbances caused by parasitic effects like series resistance and sneak path complications. The current flowing through the metal wires can cause a notable reduction in voltage, particularly affecting the cell at the greatest distance within the array. This phenomenon ultimately leads to what is commonly termed the “IR drop” problem. This issue not only compromises the reliability of memory read operations but also reduces the accuracy of vector-matrix multiplication computations. Reducing the wire resistance or enhancing the intrinsic resistance of the memristor can effectively address this issue by employing advanced device architectures that promote increased integration and scaling through the reduction of line width/length, along with the utilization of more highly conducting metallization. Another parasitic issue sneak path refers to an unintended electrical pathway that allows current to flow through multiple memristors, rather than through the targeted cell for a particular operation.⁴⁶ Such sneak path issue may trigger operational malfunctions and excessive energy consumption.⁴⁷ To alleviate the sneak path issue, various strategies involve redesigning the basic units. For example, adding an access component to the single-memristor (1R) cell can create composite cells like one-transistor-one-memristor (1T1R) or one-switch-one-memristor (1S1R) to suppress the sneak current.⁴⁸

Neuromorphic computing capability of our SiO₂-based memristors was evaluated through pulse measurements with the pulse width of 5 ms and with continuous 50 positive pulses, followed by 50 negative pulses at the amplitude of 5 V for both positive and negative pulses. In Fig. 5b, a prominent multi-conductance behavior is observed in the memristor, which mimics the information transportation between synapses. 10 cycles (a total of 1000 pulses) of LTP and LTD behaviors are achieved from our SiO₂-based memristor (Fig. S12, ESI†), demonstrating consistent repeatability with a relatively linear potentiation behavior and a less linear trend in depression. It should be noted that the resistance state is within the LRS regime during the pulse measurements (i.e., dynamic range) where the conduction filament experiences thickening (potentiation) and shrinkage (depression).⁴⁹ To validate this proposed switching mechanism, the retention (Fig. S13a and b, ESI†) and EIS (Fig. S13c–e, ESI†) measurements were conducted at three different LRS states. The Nyquist plots in Fig. S13c–e (ESI†) have a similar shape with one semicircle at LRS to that in the main text Fig. 4c, revealing that the filaments exist at multi-states of the device. Thus, the EIS results with the one semicircle shape and increased conductance support our proposed switching mechanism where (1) the synaptic process operates in the dynamic regime (i.e., conduction filament already formed between the TE and BE) and (2) the thickness of the conduction filament increases during the potentiation process.

The asymmetric non-linearity factor (ANL) was calculated by using the following equation:

where G_max, G_min, G_P(N/2), and G_D(N/2) represent the conductance maximum, conductance minimum, median value of potentiation, and medium value of depression, respectively.⁵⁰ The asymmetric non-linearity factor (ANL) value ranges from “0” to “1”, with “0” indicating a completely symmetric scenario.⁵¹ As measured from synaptic behavior, our ANL was 0.52 which is comparable to those of other reports, typically ranging 0.12–0.959 (Table S2, ESI†).^50,52 Please note that linear programming is favored because it simplifies circuit complexity.⁵³ And higher non-linear experimental results can decrease inference accuracy.⁵³

To demonstrate the neuromorphic computing performance of our memristor, we modeled a deep neural network (DNN) with 784 input neurons, 500 hidden neurons, and 10 output neurons based on our device. Further details on the simulation process are available in Note S2 (ESI†). The DNN is employed to perform image recognition tasks on the MNIST and fashion-MNIST datasets.⁵⁴ The computing structure of the DNN is described in Fig. 5a with examples of datasets. The input images are initially converted into 28 × 28 matrices with values ranging from 0 to 255. These matrices are then flattened into vectors of length 784 and fed into the DNN. The 10 output neurons correspond to 10 distinct classes, with the neuron exhibiting the highest value representing the recognized result. The DNN is initially trained on conventional hardware for 2000 epochs, attaining accuracy levels of 98.2% and 89.3% for the MNIST and fashion-MNIST datasets, respectively. Subsequently, the trained weights are translated to conductance values based on our device's conductance changing curve. To facilitate this translation, a proportional mapping scheme is employed that maps continuous weights onto the closest discrete conductance states.⁵³ Two memristors are utilized to implement positive and negative weights separately, with the maximum discrete weight set at 1 for positive memristors and −1 for negative memristors.⁵³ Given the finite number of conduction states, the learning accuracy becomes 98.0% and 88.4% for MNIST and fashion-MNIST, respectively (Fig. 5c and d). The marginal reduction (0.2% and 0.9%) in recognition accuracy validates the promise of our memristor for future applications in neural networks and neuromorphic computing.

Conclusions

We demonstrated high performance SiO₂-based memristors which can achieve a noteworthy on/off ratio as high as 1.4 × 10⁵ with long-term stability and endurance. The oxygen vacancy-driven switching mechanisms were complementarily identified through theoretical and experimental investigations. A multi-physical field coupled model based finite element simulations systematically revealed the evolution of the conduction filaments as a function of applied bias where the roughness of TE/SiO₂ interface plays a significant role. The ∼1 nm protrusion causes variations in the local electric field and hence selectively forms a conduction filament, preferably at the higher electric field locations. EIS analyses complement the theoretical switching mechanism investigation by identifying equivalent circuit components of the memristor at initial, SET, and RESET processes. Associated Nyquist plots ascertain pseudo single capacitor behavior at the initial and RESET process, and a parallel structure of a capacitor and a resistor during the SET process. As a proof-of-concept, DNN was demonstrated with the parameters of our SiO₂ memristors. The demonstrated SiO₂-based memristors featuring a notable high on/off ratio and reasonable reliability as well as low thermal budget processing may be of direct relevance to next-generation computing devices that require energy-efficient and parallel processing.

Methods

The SiO₂ switching layer was deposited from a sintered ceramic SiO₂ target in a magnetron sputtering system on heavily-doped Si wafers (<0.003–0.005 Ω cm). Before the sputtering process, the deposition chamber was pumped down to a base pressure of under 9 × 10⁻⁷ Torr. Pure Ar gas (15 sccm) was used as the sputter gas, leading to a working pressure of 1.7 × 10⁻³ Torr at an RF power of 150 W. Then, the deposited SiO₂ layer was annealed at 550 °C for 10 hours. A layer of palladium (Pd) was deposited as the top electrode (TE) on the annealed SiO₂/Si structure through a thermal evaporation system equipped with a 6 MHz oscillating quartz crystal sensor to monitor the growth rate and thickness. A shadow mask was utilized to define the shape and size of the TE during its fabrication. The thickness of the SiO₂ layer (5, 10, 20, and 30 nm) was verified by a Multi-Wavelength Ellipsometer (FilmSense FS-1) using an incident and detection angle of 65°. An FEI Themis Z TEM microscope equipped with an energy dispersive spectroscopy (EDS) was employed to examine the structures and map elemental distribution in Pd/SiO₂/P⁺⁺Si memristors. The pattern of the top electrode was verified in plan-view images by an FEI Nova NanoSEM system.

DC current–voltage (I–V) sweeping evaluations of all SiO₂-based memristors were carried out using a semiconductor parameter analyzer (Agilent 4155B) connected to a probe station in a dark shield box. Capacitance–voltage (C–V) characteristics were performed with a precision LCR meter (Agilent 4284A). Electrochemical impedance spectroscopy (EIS) investigations were conducted in an electrochemical workstation (VersaSTAT3 Princeton) by using a frequency range of 1 MHz to 1 Hz. For the pulse measurement, the Agilent 33120A function arbitrary waveform generator provided the pulse profile, which could be conveniently designed by the Agilent IntuiLink Waveform Editor. A digital storage oscilloscope (Hantek DSO4254B) was utilized to monitor the pulse voltages, and the Agilent 4155B SMU was used to record the corresponding current. Physical Modeling details for finite element analysis can be found in Note S1 (ESI†) while detailed simulation for image processing is elaborated in Note S2 in the ESI.†

Author contributions

F. Q. and Y. Z.: conceptualization, characterization for memristors’ performance, finite element analysis, draft writing. Z. G.: image processing simulation. C. K., J. P., and K. N.: TEM characterization. X. F.: assistance with electrical measurements. T. P., H. P., H. S., X. R., and S. L.: conceptualization, methodology, supervision, funding acquisition, writing, review, and editing.

Conflicts of interest

The authors declare no competing financial interest.

Acknowledgements

This work was partially supported by National Science Foundation, Award number ECCS-1931088 and CBET-2207302. S. L. and H. W. S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 23011043) by KRISS. The authors would like to thank Dr. Kejie Zhao for providing the electrochemical workstation.

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Footnotes

† Electronic supplementary information (ESI) available: CV measurements on devices with different thickness of SiO₂, retention characteristics on 5 nm SiO₂ memristor, the electric field distribution within 5 nm SiO₂ switching layer at different stages, I–V DC sweeping characteristics of different thicknesses of SiO₂ switching layer, the oxygen vacancy evolution and the electric field distribution of memristor with 10 nm SiO₂ switching layer at different stages, gradual switching behavior of the 5 nm SiO₂ memristor, physical modeling detail, and image processing detail. See DOI: https://doi.org/10.1039/d3ma01142a

‡ F. Q. and Y. Z. contributed equally to this work.

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