Comprehensive understanding of electron mobility and superior performance in sub-10 nm DG ML tetrahex-GeC₂ n-type MOSFETs

Abstract

In this study, we have investigated the electron mobility of monolayered (ML) tetrahex-GeC₂ by solving the linearized Boltzmann transport equation (BTE) with the normalized full-band relaxation time approximation (RTA) using density functional theory (DFT). Contrary to what the deformation potential theory (DPT) suggested, the ZA acoustic mode was determined to be the most restrictive for electron mobility, not the LA mode. The electron mobility at 300 K is 803 cm² (V s)⁻¹, exceeding the 400 cm² (V s)⁻¹ of MoS₂ which was calculated using the same method and measured experimentally. The ab initio quantum transport simulations were performed to assess the performance limits of sub-10 nm DG ML tetrahex-GeC₂ n-type MOSFETs, including gate lengths (L_g) of 3 nm, 5 nm, 7 nm, and 9 nm, with the underlap (UL) effect considered for the first two. For both high-performance (HP) and low-power (LP) applications, their on-state currents (I_on) can meet the requirements of similar nodes in the ITRS 2013. In particular, the I_on is more remarkable for HP applications than that of the extensively studied MoS₂. For LP applications, the I_on values at L_g of 7 and 9 nm surpass those of arsenene, known for having the largest I_on among 2D semiconductors. Subthreshold swings (SSs) as low as 69/53 mV dec⁻¹ at an L_g of 9 nm were observed for HP/LP applications, and 73 mV dec⁻¹ at an L_g of 5 nm for LP applications, indicating the excellent gate control capability. Moreover, the delay time τ and power dissipation (PDP) at L_g values of 3 nm, 5 nm, 7 nm, and 9 nm are all below the upper limits of the ITRS 2013 HP/LP proximity nodes and are comparable to or lower than those of typical 2D semiconductors. The sub-10 nm DG ML tetrahex-GeC₂ n-type MOSFETs can be down-scaled to 9 nm and 5 nm for HP and LP applications, respectively, displaying desirable I_on, delay time τ, and PDP in the ballistic limit, making them a potential choice for sub-10 nm transistors.

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Introduction

Over recent decades, silicon-based microelectronics, advancing in line with Moore's law,^1–4 has heavily utilized silicon-metal-oxide semiconductor field-effect transistors (MOSFETs). These MOSFETs, integral as switches in logic circuits, are facing challenges in the post-Moore era, particularly the ‘short-channel effect’ in sub-10 nm gate lengths. Concurrently, organic field-effect transistors (OFETs), especially pentacene-based OFETs, emerge due to their flexibility, low-cost production, and suitability for large-area electronics.^5–10 Despite their unique advantages, OFETs generally have lower carrier mobility and stability than silicon, limiting their use in high-performance devices. Thus, while OFETs present an alternate route in electronics, they do not directly solve the short-channel issues in advanced, miniaturized silicon technologies. This highlights the inherent complexity in scaling down silicon MOSFETs, where thinner channels also lead to reduced mobility owing to surface effects.¹¹

The introduction of two-dimensional (2D) semiconductors like MoS₂ and black phosphorene (BP) presents a promising solution.^2,4,12–17 Their consistent thinness effectively counters short-channel effects, and they lack surface dangling bonds. However, these 2D materials encounter specific challenges.^18,19 MoS₂-based MOSFETs, suitable for sub-10 nm channels, are limited by their low intrinsic mobility, approximately 400 cm² (V s)⁻¹, and a ∼2 eV bandgap. This results in significant Schottky barriers and contact resistance, restricting current drive and yielding low on-state currents (I_on) below 250 μA μm⁻¹.^20–22 Addressing these issues is crucial to meet the high-performance requirements outlined in the 2013 International Technology Roadmap for Semiconductors (ITRS) for the next decade.²³ BP, another promising 2D material, has high carrier mobility^24,25 and is expected to achieve exceptional performance with high I_on in sub-10 nm scales,^26–28 though air sensitivity impacts its long-term stability.^29–32 To enhance current channel materials, approaches include device modifications like vertical structures and improved gate/dielectric stacks.^33–48 Nonetheless, the pursuit of new 2D semiconductors with optimal band gaps, higher mobility, and improved air stability remains essential.^49–52

Tetrahex-GeC₂, a novel 2D germanium carbide, displays remarkable electronic and carrier transport properties. It possesses a direct band gap of around 0.89 eV, which is only 0.26 eV less than bulk silicon's band gap of 1.12 eV,⁵³ thus distinguishing the two logic states in logic switches.⁵⁴ Notably, its electron mobility, assessed at 9.5 × 10⁴ cm² (V s)⁻¹via deformation potential theory (DPT), surpasses that of well-known materials like monolayered BP and MoS₂. These characteristics, along with its high cohesive energy, stability, and low effective mass, position tetrahex-GeC₂ as a promising candidate for nanoelectronics and 2D field-effect transistors (FETs).^24,53

However, a systematic interpretation of the underlying reasons for such high carrier mobility has not been reported yet. The role of electron–phonon scattering is critical in shaping charge transport properties, necessitating an in-depth exploration of its mechanisms for enhanced understanding of charge transport in monolayered (ML) tetrahex-GeC₂. While the DPT offers a straightforward approach for calculating the intrinsic electron mobility, its focus on longitudinal acoustic phonons and the assumption of isotropic electron–phonon coupling limit its accuracy.^55–57 Efforts to incorporate optical phonons and piezoelectric effects into DPT provide a broader perspective, yet these adaptations still fall short of capturing the complete picture of electron–phonon interactions. To address these limitations, the integration of the normalized full-band relaxation time approximation (RTA) with the Boltzmann transport equation (BTE) presents a robust framework for analyzing these interactions. This approach aligns well with experimental data, as evidenced in MoS₂ studies,⁵⁸ offering not just a more precise estimation of electron mobility but also insights into the intricate processes of electron–phonon coupling. Such advancements pave the way for a more profound understanding and application of the electronic properties in 2D materials.

Our second pivotal focus interrogates the capabilities of sub-10 nm gate-length double gate (DG) ML tetrahex-GeC₂ n-type MOSFETs (NMOSFETs) operating under pristine conditions free from defects and in ballistic transport mode. This query is not merely academic; it strikes at the heart of real-world applicability: can these advanced nanostructures rise to the challenge, meeting the demanding technical requirements set forth in the ITRS 2013 edition for both high-performance (HP) and low-power (LP) applications? Beyond this, do they hold the potential to outstrip the performance of other 2D materials? Addressing these questions necessitates a systematic and comprehensive study, a challenge we readily embrace in our exploration of sub-10 nm DG ML tetrahex-GeC₂ NMOSFETs, aiming to unveil their transport properties and ascertain their standing in the next generation of nanoelectronics.

Therefore, in this study, we investigated the electron mobility of ML tetrahex-GeC₂ by solving a linearized BTE at normalized full-band RTA using density functional theory (DFT) and found that the electron mobility is 803 cm² (V s)⁻¹ at 300 K. It is higher than the value of 400 cm² (V s)⁻¹ for MoS₂ calculated in the same way and measured experimentally.⁵⁸ Moreover, the out-of-plane acoustic mode, also known as the “zigzag acoustic” mode (ZA), was found to be the most restrictive for electron mobility, not the LA mode, as suggested by the DPT.

Ab initio quantum transport simulations were carried out to evaluate the performance limits of sub-10 nm DG ML tetrahex-GeC₂ NMOSFETs, including gate length (L_g) values at 3 nm, 5 nm, 7 nm, and 9 nm, and the underlap (UL) effect is also considered for the first two. Our analysis reveals that these advanced devices exhibit desirable performance across key metrics, including I_on, subthreshold swing (SS), delay time (τ), and power dissipation (PDP). In HP applications, the I_on of these devices surpasses that of the extensively studied MoS₂, positioning itself in the same order of magnitude as Bi₂O₂Se and arsenene. For LP applications, the I_on even exceeds that of arsenene, which is known for having the largest I_on among existing 2D semiconductors in certain configurations. The SS as low as 69/53 mV dec⁻¹ at the L_g of 9 nm was observed for HP/LP applications, indicating excellent gate control capability. A small SS of 73 mV dec⁻¹ at the L_g of 5 nm with a 2 nm UL was achieved for LP applications. The low τ and PDP further emphasize their potential applications in HP computing and energy efficiency. In summary, the sub-10 nm DG ML tetrahex-GeC₂ NMOSFETs can be down-scaled to 9 nm and 5 nm for HP and LP applications, respectively, not only meeting the requirements of the ITRS 2013 edition but also surpassing existing 2D materials in multiple performance metrics, making them a potential choice for sub-10 nm transistors.

Calculation method

Intrinsic mobility calculations

When considering a homogeneous system with a time-independent electric field, no magnetic field, and a steady-state condition, the BTE can be simplified:^59–61Here, E is the electrical field strength, q is the electron charge, k and n are labelled k points and the energy band index, respectively, and f_kn is the electron distribution function. Assuming that the instantaneous one-shot collision is independent of the driving force, the collision integral can be expressed in terms of the transition rate :Due to phonon scattering, the transition rate of electrons from state |kn〉 to |k′n′〉 is obtained using Fermi's golden rule (FGR).The summation is performed using the phonon's momentum (q) and the phonon branch index (λ). is the matrix element of the electron–phonon interaction. The first/second term in the bracket describes the absorption/emission of phonons. n^λ_±q is the Bose–Einstein distribution, ω_±qλ is the frequency of phonons and ε_k′n′ (ε_kn) is the electron energy. Mobilities and are linked using the “detailed equilibrium equation”:⁶¹

Here, f⁰_kn is the Fermi distribution function of the system at equilibrium. This equation ensures at equilibrium that .

The left-hand side of the BTE of eqn (2) is approximately in linear order by changing the Fermi distribution function to an equilibrium distribution:

in which the group velocity is defined as:The generalized transport relaxation time τ_kn is defined, so the above equation is written as:^61,62

Eqn (2)–(5) are applied to (1) to obtain:

The RTA of the normalized full energy band for the linearized BTE, including the inelastic scattering process, is defined as:Here the scattering angle θ_kk′ is defined as:Based on the transport relaxation time τ_kn in eqn (9), the electron mobility at low fields⁶³where coefficient 2 illustrates the spin-degeneracy.

To solve the BTE, the QuantumATK (version R-2021.06-SP1) package⁶⁴ is utilized to calculate the band structure, phonon spectrum, and electron–phonon coupling using the DFT method. To obtain more accurate band gap values, the meta-GGA (MGGA) exchange–correlation in the Tran–Blaha MGGA-TB09 functional⁶⁵ with a c parameter of 1.09 is used, combined with a linear combination of atomic orbitals (LCAO) being employed for the electronic structures. The PseudoDojo pseudopotential is used instead of the full atomic all-electron potential,⁶⁶ and the wave function expansion is done with a high-precision numerical basis. The energy cut-off of the density grid in the real space is set to 85 Hartree, and the density of the k-point grid in the Brillouin zone is 8 × 7 × 1. The dynamical matrix under a 5 × 5 × 1 supercell is employed to calculate the phonon spectrum using the frozen phonon method.

In order to accurately calculate the transmission probability of electrons, we will focus on the electronic states near the conduction band minimum (CBM) as they are decisive for electrical transport. To balance the complexity and accuracy of the calculation, we confine our examination to the electron-acoustic coupling matrix element of the phonon modes near Γ(0,0,0) (long wavelength) and the electronic states near the CBM for the electron–phonon coupling matrix element. To ensure reliable mobility results, we examined the range and density of the k/q space as shown in Fig. S1 (ESI†), and chose a k-region of 0 to ±0.15 near the CBM, with 38 × 38 × 1 k points, and a q-region of ±0.15 near the Γ point, with 38 × 38 × 1 q points.

Device models and simulations

The performance limits of sub-10 nm ML tetrahex-GeC₂ NMOSFETs were examined using a DG two-probe model. The electron transport properties are calculated using the non-equilibrium Green's function (NEGF) combined with DFT in QuantumATK software (version R-2021.06-SP1). Sampling 161 × 4 × 1 k points in the device model for self-consistent calculations, other parameters are also the same as in the bulk. Previous studies have substantiated the assumption that electron transport is ballistic for sub-10 nm channel lengths of NMOSFETs, which is well approximated.^67–69 Thus, the drain current is calculated using the following Landauer–Buttiker formula:⁷⁰where T(E,V_ds,V_g) is the transmission probability at gate voltage V_g and source–drain voltage V_ds. f_S/f_D is the Fermi–Dirac distribution function of the source/drain electrode. μ_S/μ_D is the electrochemical potential of the source/drain electrode. The temperature is set to 300 K.

Results and discussion

Electron mobility

After obtaining the dispersion relationships of the electronic states near the CBM and phonons around the Γ point (Fig. 1(a) and (b)), the first-order partial derivative of the Hamiltonian was taken to derive the EPC matrix and the carrier mobility. Fig. 2(a) shows the phonon-limited electron mobility at room temperature (300 K) in relation to the Fermi energy level (E_F) shift. The intrinsic electron mobility corresponding to the E_F shift is 0 with full phonon scattering and is estimated to be 803 cm² (V s)⁻¹, which is greater than the electron mobilities of MoS₂ (400 cm² (V s)⁻¹)⁵⁸ and honeycomb silicene (360 cm² (V s)⁻¹)⁷¹ at the same level of calculation. By shifting the E_F above 0.3 eV, the electron mobility can be further boosted to 10³ cm² (V s)⁻¹, with a corresponding carrier concentration of 10¹³/(cm²) through electron doping (Fig. 2(b)).

Fig. 1 Computed (a) band structure and (b) phonon spectrum of ML tetrahex-GeC₂. In (b), ZA, TA and LA stand for the three acoustic branches.

Fig. 2 The relationship between the (a) electron mobility and (b) carrier concentration of ML tetrahex-GeC₂ with the E_F shift.

We further studied the electron mobility under three acoustic phonons’ scattering in the long-wave approximation (see Table S2, ESI† and Fig. 3). The ZA mode had the most significant effect on the mobility, limiting the intrinsic electron mobility to 2.8 × 10³ cm² (V s)⁻¹. The LA mode was the next most influential factor, limiting the intrinsic electron mobility to 8.5 × 10³ cm² (V s)⁻¹. This indicates that the DPT, which only considers scattering due to the LA phonon, is insufficient to predict electron mobility accurately. On the other hand, when the ZA mode scattering was eliminated, the intrinsic electron mobility could be increased to 1.33 × 10³ cm² (V s)⁻¹ (Fig. 2(a)). This suggests that the electron mobility of tetrahex-GeC₂ can be improved by suppressing the ZA mode vibrations. Therefore, we illustrate the vibrations of three acoustic modes (Fig. 4).

Fig. 3 The electron mobility of ML tetrahex-GeC₂ varies with the E_F shift resulting from scattering by the three acoustic branches ZA, TA and LA.

Fig. 4 Schematics of the vibrational modes of the three acoustic branches, (a) TA (b) LA and (c) ZA. The plane in which GeC₂ located is the X–Y plane. The gray and blue-green spheres represent the C and Ge atoms, respectively.

The ZA mode corresponds to the lattice vibration direction perpendicular to the plane on which tetrahex-GeC₂ is located (Fig. 4(c)). Therefore, in practical applications, the electron mobility can be enhanced by selecting an appropriate substrate or using a clamping material to make tetrahex-GeC₂ interact with each other, thus suppressing the ZA mode vibration.

To gain insight into why the ZA mode has the most powerful suppression effect on the electron mobility among the three acoustic modes, we plotted the correlation between the electron–phonon coupling strength (represented by the matrix element) and q(q_x, q_y) of the TA, LA and ZA modes (Fig. 5). The ZA mode has the most robust coupling to the electronic state near the CBM as shown in Fig. 5(c), indicating that the ZA mode scatters the electrons the most and thus suppresses the mobility the most.

Fig. 5 The relationship between the electron–phonon coupling matrix and q(q_x, q_y) of (a) TA, (b) LA and (c) ZA acoustic modes.

Performance of ML tetrahex-GeC₂ n-type DG MOSFETs

Fig. 6 demonstrates that the model of a sub-10 nm DG ML tetrahex-GeC₂ NMOSFET consists of heavily doped tetrahex-GeC₂ as the source, drain, and ML intrinsic tetrahex-GeC₂ as the channel. To ensure efficient carrier injection and minimize tunnelling leakage in the off-state, an optimized source and drain doping concentration (N_e) is essential. Fig. S2 (ESI†) reveals that the optimal doping concentration for the source/drain is 0.0102 e per atom. SiO₂ is used as the gate dielectric for transistors with gate lengths ranging from 3 to 10 nm. Equivalent oxide thickness (EOT) and supply voltage (V_ds) are adopted as the parameters from the ITRS 2013 edition for HP and LP applications of similar length nodes (Table 1). In the following discussion, the term ITRS is used to refer to the ITRS 2013 edition, as it is directly related to sub-10 nm gate lengths and has more rigorous standards than subsequent versions. This implies that if the transistor's performance metrics meet the standards of the ITRS 2013 edition, it can also meet the goals of IRDS 2021.⁷²

Fig. 6 Schematic structure of DG ML tetrahex-GeC₂ NMOSFETs, where L_ul, L_g and UL denote the channel length, gate length and underlap part, respectively.

Table 1 A comparison of the ballistic performance of DG ML tetrahex-GeC₂ NMOSFETs against the ITRS requirements for HP and LP transistors spanning the 2022–2028 horizon in the ITRS

	L g (nm)	L ul (nm)	EOT (nm)	I off (μA μm^−1)	SS (mV dec^−1)	I on (μA μm^−1)	I on/Ioff	C t (fF μm^−1)	τ (ps)	PDP (fJ μm^−1)
LP	3	0	4.5	—	—	—	—	—	—	—
		2	4.5	5 × 10^−5	78	150.	3.00 × 10^6	0.092	0.613	0.059
	5	0	4.5	5 × 10^−5	170	6.	1.22 × 10^5	0.269	44.039	0.172
		2	4.5	5 × 10^−5	73	537	1.07 × 10^7	0.169	0.314	0.108
	7	0	4.9	4 × 10^−5	120	1762	4.41 × 10^7	0.444	0.252	0.307
	9	0	5.5	2 × 10^−5	53	1791	8.96 × 10^7	0.518	0.289	0.378
HP	3	0	4.5	0.1	182	100	9.99 × 10^3	0.174	1.740	0.111
		2	4.5	0.1	101	1514	1.51 × 10^4	0.108	0.071	0.069
	5	0	4.5	0.1	148	2538	2.54 × 10^4	0.365	0.144	0.233
		2	4.5	0.1	80	1768	1.77 × 10^4	0.174	0.098	0.111
	7	0	4.9	0.1	138	2552	2.55 × 10^4	0.441	0.173	0.304
	9	0	5.5	0.1	69	2592	2.59 × 10^4	0.587	0.227	0.429
ITRS LP in 2028	5.9		4.1	5 × 10^−5	—	295	5.90 × 10^6	0.690	1.493	0.280
ITRS HP in 2028	5.1		4.1	0.1	—	900	9.00 × 10^3	0.600	0.423	0.240
ITRS LP in 2026	7.0		4.5	4 × 10^−5	—	337	8.42 × 10^6	0.770	1.514	0.340
ITRS HP in 2024	7.3		4.9	0.1	—	1170	1.17 × 10^4	0.770	0.451	0.360
ITRS HP in 2024	6.7		4.3	0.1	—	1100	1.10 × 10^4	0.720	0.446	0.330
ITRS LP in 2023	9.3		5.1	2 × 10^−5	—	458	2.29 × 10^7	0.950	1.474	0.480
ITRS LP in 2024	8.5		4.9	2 × 10^−5	—	395	1.98 × 10^5	0.890	1.557	0.420
ITRS HP in 2022	8.8		5.4	0.1	—	1350	1.35 × 10^4	0.870	0.463	0.450

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To maximize the performance, a symmetric UL layer is incorporated into the DG ML tetrahex-GeC₂ NMOSFET. This UL layer comprises a dielectric layer and part of the channel layer. Previous studies have demonstrated that such a structure's ballisticity (defined as the current ratio in the scattering and ballistic limits) can exceed 88% for an effective channel length of 10 nm or less.^67–69 Therefore, in this study, the gate length (L_g) was kept lower than 10 nm and the maximal L_ul was maintained (10 nm −L_g)/2.

A. On-state current. The I_on is an essential factor for logic transistors, especially in high-performance servers that require fast switching speeds. It is determined by the current on the transfer characteristic curve when the gate voltage is V_g(on) = V_g(off) + V_ds, where V_g(on/off) is the gate voltage with the current in the on/off state (I_on/I_off). According to ITRS, V_dd is set to 0.64 V, 0.69 V, and 0.73 V for L_g values of 5(3) nm, 7 nm, and 9 nm, respectively. For HP applications, I_off is fixed at 0.1 μA μm⁻¹, while for LP applications, I_off is set to 5 × 10⁵ μA μm⁻¹, 4 × 10⁵ μA μm⁻¹, and 2 × 10⁵ μA μm⁻¹ for L_g values of 5(3) nm, 7 nm, and 9 nm, respectively.

To estimate the magnitude of the I_on in the device, the current of the DG ML GeC₂ NMOSFET must first reach I_off to determine V_g(off). As illustrated in Fig. 7, all DG ML GeC₂ NMOSFETs can satisfy the HP and LP I_off requirements, except for the NMOSFET with a L_g of 3 nm with no UL, where the source leakage current is too high to meet the LP I_off requirements for LP applications. The L_g of the 3 nm NMOSFET with a L_ul of 2 nm has a steeper subthreshold region in the I–V_g curve, which enables it to meet the LP I_off requirements. This is because the UL enlarges the channel length and reduces the leakage current. Our following discussion of I_on will focus on device configurations that meet the I_off requirements.

Fig. 7 The transfer characteristics of the DG ML tetrahex-GeC₂ NMOSFETs with L_g values of (a) 3 nm (b) 5 nm (c) 7 nm and (d) 9 nm. The red and blue dashed lines represent the I_off requirement per ITRS for HP and LP devices, respectively.

The I_on of DG ML GeC₂ NMOSFETs can be determined once V_g(off) is known. To begin with, we will focus on the I_on of DG ML GeC₂ NMOSFETs without UL. As shown in Fig. 7 and Table 1, for LP applications, the I_on is 6 μA μm⁻¹, 1762 μA μm⁻¹ and 1791 μA μm⁻¹ for L_g values of 5 nm, 7 nm and 9 nm, respectively. Among them, I_on for both L_g values of 7 nm and 9 nm are 4–5 times the LP ITRS requirements for similar nodes. For HP applications, the I_on values for L_g values of 5 nm, 7 nm, and 9 nm are 2538 μA μm⁻¹, 2552 μA μm⁻¹, and 2592 μA μm⁻¹, respectively, which are more than twice the similar node requirements of ITRS for HP applications.

We then further investigated the influence of UL on the I_on. As shown in Fig. S3(a) (ESI†), for HP applications, when L_g is 3 nm, the I_on increases from 100 μA μm⁻¹ to 2538 μA μm⁻¹ with a L_ul of 2 nm, exceeding the ITRS requirement for HP applications by more than twice (900 μA μm⁻¹ for the 3/5.1 nm node). For LP applications (Fig. S3(b), ESI†), when L_g is 5 nm, the I_on increases from 6 μA μm⁻¹ to 536 μA μm⁻¹ with a L_ul of 2 nm, surpassing the ITRS requirement for LP applications by almost twice (295 μA μm⁻¹ for the 5.9 nm node).

We further compared the I_on of sub-10 nm DG ML GeC₂ NMOSFETs with the conventional 2D semiconductor NMOSFETs (Tables 1, 2 and Fig. 8), such as MoS₂, which is commonly used experimentally, and other 2D materials, including Bi₂O₂Se, InSe, arsenene, antimonene, GeSe, and silicane. These materials are desirable channel materials because of their air stability and high carrier mobilities for upcoming FETs. Moreover, 2D silicane is compatible with mature silicon-based technologies, in addition to its air stability and high carrier mobilities. We also compared GeC₂ NMOSFETs with advanced Si-based FETs, including Si nanowire FETs, Si FinFETs, and ETSOI FETs. Additionally, we examined the I_on of the GeC₂ NMOSFETs in comparison to Carbon Nanotube (CNT) FETs and Gate All Around (GAA) CNT FETs as a potential and competitive semiconductor device material in the post-Moore's Law Era.

Table 2 For HP applications, several key device metrics for the upper limits of the ballistic performance in sub-10 nm DG ML NMOSFETs of Bi₂O₂Se,⁷³ MoS₂,⁷³ InSe,⁷⁴ arsenene,^75,76 antimonene,^75,76 GeSe (armchair)²⁸ and silicane⁷⁷ as well as other sub-10 nm gate-length technologies^4,78–83

HP		L g (nm)	L ul (nm)	I on (μA μm^−1)	PDP (fJ μm^−1)	τ (ps)
n-type ML Bi2O2Se		8.8	0	3380	0.249	0.102
		6.7	0	2126	0.18	0.126
		5	2	2067	0.123	0.093
		3	3	996	0.061	0.093
n-type ML MoS2		9	0	230	0.172	3.509
		5	2	473.34	0.195	1.287
		3	2	519.48	0.126	0.126
n-type ML InSe		7	0	1497	0.096	0.09
		5	0	1538	0.078	0.075
		3	2	1468	0.039	0.048
n-type ML arsenene		10	0	2912	0.372	0.135
		8.5	0	2941	0.216	0.096
		6.4	0	2536	0.189	0.081
	DFT-NEGF	5	0	655	0.159	0.177
			2	2030	0.096	0.051
n-type ML antimonene		5	0	614	—	—
			2	728	—	—
n-type ML GeSe (armchair)		5	4	483	0.073	0.237
		4	4	494	0.056	0.177
		3	4	492	0.043	0.137
n-type ML silicane		5	4	1374	0.037	0.042
		3	4	527	0.016	0.047
GGA CNT		5	1	1703	0.072	0.078
		3	2	1347	0.051	0.042
Si nanowire		10	—	522	0.345	0.66
		5	—	115	0.165	1.44
Si Fin		10	—	446	0.546	1.02
	Experiment	5	—	269	0.432	1.605
ETSOI		8	—	340	0.948	1.86
CNT FET		9	0	630	0.552	0.174
		5	—	1412	0.138	0.078

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Fig. 8 A comparison of the I_on of (a) HP and (b) LP application concerning the gate length L_g for the optimal DG ML tetrahex-GeC₂, Bi₂O₂Se, antimonene, GeSe (armchair), silicane, MoS₂, InSe and arsenene NMOSFETs, based on the ab initio quantum transport simulations.

For LP applications, ML GeC₂ NMOSFETs have the largest I_on among the listed devices at 5 nm ≤ L_g ≤ 9 nm nodes. As L_g increases from 5 nm to 7 nm, the I_on of the ML GeC₂ NMOSFETs rises drastically to 1762 μA μm⁻¹, surpassing those of InSe and arsenene by more than four and three times, respectively. For HP applications, the I_on magnitude of ML GeC₂ NMOSFETs is 2–3 × 10³ μA μm⁻¹ at 5 nm ≤ L_g ≤ 9 nm nodes, which is 1–2 times higher than the I_on requirement for similar nodes in ITRS HP, and much higher than 500 μA μm⁻¹ of the most studied MoS₂. It is also noteworthy that the I_on values of the ML GeC₂ NMOSFETs are comparable to those of ML Arsenic and Bi₂O₂Se, which have the highest ionic content of the listed materials. Additionally, the I_on of the ML GeC₂ NMOSFETs is greater than those of the advanced silicon-based FETs, including Si nanowires, Si Fin, ETSOI, and CNT FETs at comparable nodes.

B. Gate control. In addition to I_on, SS is a significant factor for evaluating device performance, showing its ability to manipulate the subthreshold domain's gate voltage. SS is determined using the following formula:where I_d is the source–drain current, and a smaller SS indicates a better gating capability and usually a larger I_on current. At room temperature, 60 mV dec⁻¹ is the Boltzmann limit, which is the fundamental thermal limit of SS in NMOSFETs.⁸⁴ The SS can be determined by the steepest point of the transfer characteristic curve at V_g when the current consists of tunneling and thermionic components (I_d = I_tunnel + I_therm):⁶⁷When r_tunnel = 0, the current is thermionic and SS is equal to SS_therm with a fundamental limit of 60 mV dec⁻¹. However, when 0 < r_tunnel <1, the I_tunnel must be considered, causing SS to be less than 60 mV dec⁻¹. As shown in Fig. 9 and Table 1, for the HP application, the SS values of the 3 nm and 5 nm DG ML GeC₂ NMOSFETs with a L_ul of 2 nm reduce to 78 mV dec⁻¹ and 73 mV dec⁻¹, respectively. While the 9 nm one without UL has an SS value of 69 mV dec⁻¹. These values are close to the desired value of 60 mV dec⁻¹. As previously mentioned, the UL widens the barrier and effective channel length, thus reducing the short-channel effect, steepening the slope of the transfer curve, and lowering the SS values. For LP applications, the 9 nm DG ML GeC₂ NMOSFET has the lowest SS value of 53 mV dec⁻¹ among the GeC₂ NMOSFETs, which is below the fundamental limit of 60 mV dec⁻¹ and also lower than the 60 mV dec⁻¹ value of 9 nm DG ML Bi₂O₂Se.⁷³

Fig. 9 SS as a function of gate length L_g for DG ML GeC₂ NMOSFETs with and without UL. The black dashed lines indicate the Boltzmann limit of 60 mV dec⁻¹ for SS at room temperature.

To understand why SS can be taken below 60 mV dec⁻¹ in LP applications, we have calculated the spectral currents and local density of states (LDOS) for the three V_g values of −0.4 V, −0.1 V, and 0.2 V at a L_g of 9 nm with a step change of 0.2 V (Fig. 10) The SS at −0.4 V is near its minimum value, while the SS at 0.2 V is much higher than 60 mV dec⁻¹, and the SS at −0.1 V falls in between. As shown in Fig. 10, the I_tunnel current is a major component of the total current when V_g = −0.4 V, which is nearly 50%, thus 0 < r_tunnel < 1. At V_g = 0.2 V, almost all of the current is I_therm and the r_tunnel is almost zero. The tunneling potential and I_tunnel are related using the following formula:⁸⁵

where ϕ_B and w are the height and width of the potential barrier, respectively. As the potential width w remains constant, the I_tunnel is mainly determined by the potential barrier height ϕ_B. When V_g is changed from −0.4 V to −0.1 V, ϕ_B decreases by 0.256 eV, whereas when V_g is varied from −0.1 V to 0.2 V, the decrease in ϕ_B is only 0.032 eV. This indicates that when V_g is −0.4 V, the rate of change of the potential barrier is high, thus resulting in a large rate of change of I_tunnel. This means that the SS_tunnel is low enough to meet the requirement of SS_tunnel < SS_therm.

Fig. 10 Spatially resolved LDOS and spectral currents of the 9 nm DG ML GeC₂ NMOSFET at V_g of (a) −0.4 V, (b) −0.1 V and (c) 0.2 V, respectively. The electrochemical potentials of the source and drain are denoted as ε_L and ε_R, respectively, while ϕ_B is the energy barrier for electrons at the CBM transporting from the drain to the source.

Transconductance g_m is a key indicator of device performance, indicating the gate control capability in the superthreshold region, and g_m is calculated as follows:⁸⁶

A large g_m implies better gate control and a higher I_on. As shown in Fig. 11, for HP/LP applications, 3 nm, 5 nm, 7 nm and 9 nm DG ML GeC₂ NMOSFETs have g_m of 4.51–13.16 mS μm⁻¹, which is similar to the 7–12 mS μm⁻¹ of Bi₂O₂Se NMOSFETs.⁵² It should be noted that when a 2 nm UL is used, the g_m will be reduced in the superthreshold region.

Fig. 11 The g_m of DG ML GeC₂ NMOSFETs with and without ULs as a function of the gate length L_g in the HP and LP applications.

C. Intrinsic delay time and power consumption. The switching speed is an important quality factor for digital circuits, usually measured by the intrinsic delay time τ. A lower τ implies faster switching speeds. It is calculated by applying the following equation:⁸⁶where V_ds is the source–drain voltage, and the ITRS standard states that the total gate capacitance C_t is three times the intrinsic channel capacitance, that is C_t = 3 C_g. C_g is expressed as:^4,86,87Q is the total channel charge. Table 1, Fig. S4 and S5 (ESI†) detail the performance metrics gate capacitance (C_t), delay times (τ) and the power dissipation per unit width (PDP) of DG ML GeC₂ NMOSFETs C_t ranges from 0.092 to 0.518/0.108 to 0.587 fF μm⁻¹ for HP/LP applications, respectively, aligning with ITRS standards and indicating optimal interface capacitance. τ values range from 0.07 to 0.23 ps/0.25 to 0.61 ps (except for L_g = 3 nm with the UL configuration) for HP/LP applications, which are significantly below the ITRS upper limits of 0.69–0.95 ps and 0.60–0.87 ps, respectively, demonstrating high switching speeds. In Tables 2, 3 and Fig. S6 (ESI†), we compare τ of DG ML GeC₂ NMOSFETs with other DG ML NMOSFETs. For HP applications, GeC₂ shows a significantly lower τ than MoS₂ and is comparable to Bi₂O₂Se, InSe, Arsenene, silicane, and GeSe. For LP applications, GeC₂'s τ is notably smaller than MoS₂'s, aligning closely with InSe and Arsenene. The PDP (PDP = C_tV_ds²) for these FETs ranges from 0.059 to 0.306/0.069 to 0.428 fJ μm⁻¹ for LP/HP applications, lower than the ITRS standard upper limits. Furthermore, as Tables 2, 3 and Fig. S7 (ESI†) show that the PDP of DG ML GeC₂ NMOSFETs is comparable to those of Bi₂O₂Se, MoS₂, InSe, and arsenene NMOSFETs. These performances suggest that DG ML GeC₂ NMOSFETs are competitive with other 2D materials, offering both low delay time and low power consumption.

Table 3 For LP applications, several key device metrics for the ballistic performance upper limits of the sub-10 nm DG ML NMOSFETs of Bi₂O₂Se,⁷³ MoS₂,⁷³ InSe,⁷⁴ arsenene,^75,76 antimonene^75,76 and GeSe (armchair)²⁸

LP		L g (nm)	L ul (nm)	I on (μA μm^−1)	PDP (fJ μm^−1)	τ (ps)
n-type ML Bi2O2Se	DFT+NEGF	9.3	0	10	0.408	57.5
		7.0	0	3.8 × 10^−3	0.340	1.4 × 10^5
		5.0	2	4.1 × 10^−3	0.258	9.8 × 10^4
n-type ML MoS2		5	3	324.05	0.093	0.552
		3	2	133.09	0.078	2.337
n-type ML InSe		7	0	401	0.078	0.339
		5	2	424	0.039	0.210
		3	3	69	0.03	0.852
n-type ML arsenene		10	0	1750	0.411	0.225
		8.5	0	1325	0.15	0.213
		6.4	0	560	0.096	0.267
		5	0	152	0.156	0.759
			2	341	0.069	0.303
n-type ML antimonene		5	0	42.8	—	—
			2	482	—	—
n-type ML GeSe (zigzag)		5	4	274	0.055	0.320
		4	4	161	0.05	0.480
		3	4	6.7	0.047	10.99
n-type ML silicane		5	4	438	0.021	0.073
		3	4	467	0.016	0.054

---

Conclusions

Our research revealed that ML tetrahex-GeC₂ is a potential channel material for sub-10 nm NMOSFETs due to its high electron mobility and superior electrical performance when compared to other 2D semiconductors. Using the linearized BTE with normalized full-band RTA and DFT, we calculated the electron mobility of ML tetrahex-GeC₂ to be 803 cm² (V s)⁻¹ at 300 K, which is much higher than the electron mobility of MoS₂, which was assessed to be 400 cm² (V s)⁻¹ using the same method and measured experimentally. Contrary to the DPT's suggestion, the ZA acoustic mode was determined to be the most restrictive for the electron mobility, not the LA phonon. Ab initio quantum transport simulations were used to assess the performance of sub-10 nm DG ML tetrahex-GeC₂ NMOSFETs with L_g values of 3 nm, 5 nm, 7 nm, and 9 nm. The UL effect was considered for the first two lengths. The study found that these NMOSFETs can meet the requirements of the ITRS for both HP and LP applications. Particularly for HP, the I_on is comparable to those of Bi₂O₂Se and arsenene and better than that of MoS₂. For LP, I_on surpasses that of arsenene at L_g values of 7 nm and 9 nm. The SS demonstrates excellent gate control capability, with values as low as 69/53 mV dec⁻¹ for HP/LP at L_g values of 9 nm and 73 mV dec⁻¹ at the L_g of 5 nm for LP. Delay times τ for all L_g are within ITRS limits and are comparable to other notable materials like InSe, arsenene, Bi₂O₂Se, and silicane. The power dissipation PDP at L_g also remains below the upper limits of ITRS, and the performance for HP and LP applications is comparable with that of materials like Bi₂O₂Se, MoS₂, arsenene, InSe, and GeSe. Overall, this study shows the promising potential of sub-10 nm DG ML tetrahex-GeC₂ NMOSFETs in both HP and LP applications.

Data availability statements

All data that support the findings of this study are included within the article (and in the ESI†).

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

Calculations were carried out in the High-Performance Computing Laboratory of Changzhou University and at the Hefei Advanced Computing Center. Literature analysis is performed using the Stork software (https://www.storkapp.me).

Notes and references

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Footnote

† Electronic supplementary information (ESI) available: All abbreviations and symbols appearing in the text (Table S1). The electron mobility calculated with respect to (a) the k-space range around the CBM, (b) the number of k-points, (c) the q-space range around the Γ point, and (d) the number of q-points (Fig. S1); the electron mobility under three acoustic phonons’ scattering in the long-wave approximation (Table S2); the transfer characteristics of the DG ML tetrahex-GeC₂ NMOSFETs with an L_g of 5 nm at electron doping concentrations (N_e) of 0.0051 e per atom, 0.0102 e per atom, and 0.0204 e per atom (Fig. S2). The I_on for HP and LP application of the sub-10 nm DG ML tetrahex-GeC₂ NMOSFETs as a function of the gate length L_g (Fig. S3). The intrinsic delay time τ as a function of the gate length L_g in DG ML GeC₂ NMOSFETs (Fig. S4). The PDP in DG ML GeC₂ NMOSFETs (Fig. S5). The intrinsic delay time τ as a function of the gate length L_g in DG ML GeC₂ NMOSFETs (Fig. S6). Comparison of the PDP of (a) HP application and (b) LP application with respect to the gate length L_g for the optimal DG ML tetrahex-GeC₂, Bi₂O₂Se, antimonene, GeSe (armchair), silicane, MoS₂, InSe and Arsenene NMOSFETs (Fig. S7). See DOI: https://doi.org/10.1039/d3cp05327j

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