Junghoon
Yang‡
a,
HyunWoo
Park‡
a,
Baul
Kim
b,
Yong-Hoon
Cho
*b and
Sang-Hee Ko
Park
*a
aDepartment of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea. E-mail: shkp@kaist.ac.kr
bDepartment of Physics and KI for the NanoCentury, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea. E-mail: yhc@kaist.ac.kr
First published on 27th June 2022
We demonstrate a reliable monolithic process to fabricate micro-light-emitting diodes (μLEDs) driven by highly stable dual-gate structured amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) arrays. In contrast to the conventional μLED integration technologies that require the mass transfer of LEDs, our unique monolithic fabrication of oxide TFTs on the GaN epitaxial layer can be applied for accurate integration compared to the method of mounting discrete μLEDs on a backplane individually. To evaluate the applicability of the method at the wafer level, we introduced an atomic-layer-deposited Al2O3 insulator film and a denser oxide semiconductor in a dual-gate structured TFT. The induction of controlled hydrogen diffusion from the gate insulator into the active layer at low temperatures led to the good performance of the dual-gate bottom-contact (DGBC) a-IGZO TFTs under positive bias temperature stress (PBTS), negative bias illumination stress (NBIS), and negative bias temperature illumination stress (NBTIS). Monolithic integration of such μLEDs and DGBC a-IGZO TFT arrays was achieved using an organic interlayer dielectric at a low temperature below 230 °C. This simple process exhibits excellent TFT manufacturability (stable Von = 0.78 V), stability (ΔVon, PBTS: 0.03 V, NBIS: −1.85 V, and NBTIS: −3.27 V), uniformity, and reproducibility (less than 4% difference in Von). It shows promise for the mass production of μLED displays for flexible and/or ultra-high-resolution displays for augmented and virtual reality and biomedical applications.
Among the various TFT backplanes, low-temperature polycrystalline silicon (LTPS) TFTs have been used in driving high-resolution μLEDs. Recently, Kim et al. developed remarkably bright active-matrix μLEDs using the LTPS TFT backplane.17 A solder bump material was employed for bonding the LTPS backplane to the μLED array. However, this process may cause pressure damage and stress within the μLEDs, which results in a fracture.18 Others have successfully developed a 12.1 inch 169 ppi full-color μLED display by transferring μLEDs to the LTPS TFT backplane.19 Despite their careful integration, LTPS TFTs have inherent drawbacks in terms of power consumption and high costs.20,21 In contrast, amorphous oxide semiconductor TFTs with high mobility, stability, and uniformity can also drive μLEDs with a high pixel density.22,23 Recently, Sun et al. developed a 4 inch full-color μLED display based on indium gallium zinc oxide (IGZO) TFTs.24 The mass transfer was used to integrate more than 170000 flip-chip RGB μLEDs on the IGZO TFT backplane. However, the transfer of LEDs is associated with yield issues, and the mass transfer is not yet commercially viable, particularly for a high-resolution display with a small pixel pitch. Additionally, a lower yield during transfer significantly affects the performance of the μLED display. Therefore, it is necessary to integrate the TFT array monolithically into the μLED array.
However, this limits the process temperature for the oxide TFT array because the planarization of the μLED array is achieved by a photo-patternable organic polymer. Therefore, oxide TFT arrays should be fabricated on top of the μLED array at a low temperature in order to secure the properties of the planarization material. In general, the defects in the oxide semiconductor and/or the interface between the active layer and the gate insulator (GI) can be minimized by semiconductor densification and defect passivation during the annealing process over 300 °C.25–28 Moreover, the instability of oxide TFTs under electrical bias, light, and temperature is a critical hurdle against the commercialization of current driven displays such as μLEDs. Based on this viewpoint, it is essential to develop a highly reliable oxide TFT on a μLED array at low temperatures for monolithic integration.
Herein, we describe the first monolithic fabrication of amorphous (a)-IGZO TFTs on a GaN-based μLED array. Our fabrication method could be achieved by introducing an a-IGZO channel with a high film density and atomic-layer-deposited dielectric layers in a dual-gate TFT structure to eliminate the charge trapping defects within the active bulk and/or the interface between the active layer and GI. In addition, the opaque bottom gate of our dual-gate TFT can block the light of top-emission μLEDs, securing the light stability of a-IGZO TFTs during the operation. Through this process, we obtained highly stable a-IGZO TFTs under positive bias temperature stress (PBTS), negative bias illumination stress (NBIS), and negative bias temperature illumination stress (NBTIS) environments. We demonstrated the excellent stability of low-temperature a-IGZO TFTs and its correlation with defects through various thin-film analyses. On the basis of these characteristics, it has been verified that a multigate transistor is also capable of performing reliable logic and synopsis operations by controlling the gate voltage.29 This unique monolithic fabrication method of the oxide TFT array provides the groundwork for fabricating large-area, high-resolution, and highly stable μLED displays at low cost.
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Fig. 1 A schematic image of a monolithic dual-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) and materials for each layer. |
Subsequently, we investigated the effect of the active layer/insulator interface on electrical properties. Generally, it is crucial to control the defects within the active layer itself and the interface traps between the active layer and GI for the excellent reliability of oxide TFTs.36,37 We fabricated TGBC TFTs with stack structures similar to those of self-aligned TFTs, which are advantageous for large-sized and high-resolution displays.38 Additionally, we applied the ALD-Al2O3 insulator film to both PLs and GIs because of its high quality even when deposited at a low temperature.39,40 The details of the fabrication method of TGBC TFTs are described in the ESI.† To identify the optimized characteristics of TFTs in terms of Von, mobility, and stability, we fabricated TGBC a-IGZO TFTs by applying two different Al2O3 deposition methods [T-ALD and plasma-enhanced ALD (PE-ALD)] to the PL and GI. Initially, we fabricated each pair of TGBC TFTs to determine the suitable deposition method for the monolithic TFT fabrication. All four samples were annealed in vacuo at 230 °C for 2 h.
Fig. 2(a–d) show the transfer curves of a-IGZO TGBC TFTs at drain voltages of 0.1 and 10 V prepared using (a) T-ALD/T-ALD, (b) PE-ALD/T-ALD, (c) T-ALD/PE-ALD, and (d) PE-ALD/PE-ALD for PL/GI deposition. We used a thin PL (first GI) to protect the active a-IGZO layer because the 1:
1
:
2.5 ratio of the a-IGZO film is vulnerable to the acid during the etching process.41Fig. 2(e) illustrates that the hysteresis of each TFT [(a–d)] is 0.25, 5.75, 0.75, and 16.5 V, and the linear mobilities are 20.31, 4.47, 25.31, and 0.97 cm2 V−1 s−1, respectively. When PE-ALD PLs were used, the hysteresis was higher and the linear mobility was lower than those of TFTs adopting T-ALD PLs. While the PE-ALD process suppressed the generation of the shallow donor of oxygen vacancies in the active layer, it yielded charge trapping centers in both the active layer and the interface between the active layer and the GI compared with T-ALD.42 These differences are ascribed to two different oxidants: water and oxygen plasma. Oxygen plasma collisions create Oi-related states, which act as electron acceptor-like traps, thereby decreasing the electron mobility and increasing the hysteresis by capturing free electrons in the a-IGZO active layer and/or the interface between the active layer and GI.43,44 The transfer characteristics of TFTs using the PE-ALD method represented a higher hysteresis compared to the T-ALD method. Furthermore, the Al2O3 film deposited by PEALD did not contain enough H to be diffused from the active layer into the GI. This can leave the charge trapping centers generated by oxygen plasma incompletely passivated, yielding hysteresis [Fig. 2(b–d)]. Conversely, the device that applied the T-ALD-Al2O3 insulator film to both the GI and PL showed the best electrical performance by suppressing the formation of charge trapping centers at the active/insulator interface [Fig. 2(a)].45 Therefore, we concluded that using a T-ALD-Al2O3 insulator film is preferable for fabricating highly stable oxide TFTs at low temperatures.
The delicate control of the deposition temperature of GI is a crucial factor in securing the high stability of the metal–oxide transistor.46 For more detailed optimization, we manufactured another TGBC a-IGZO TFT by changing the deposition temperature of GI to 200 °C. Hence, we fabricated a second device (device B, PL: 150 °C and GI: 200 °C) wherein the turn-on voltage was shifted by 1.14 V after the PBTS measurements, which was larger than the shift of the turn-on voltage of device A (0.35 V) [Fig. 3(a)]. According to the secondary-ion mass spectrometry (SIMS) analysis, the amounts of hydrogen and hydroxyl at the PL/GI interface were lower in device B than those in device A [Fig. 3(d and e)]. In general, ALD at a higher growth temperature lowers the amount of residual hydrogen in the films due to the complete removal of the hydroxyl groups during the surface reaction.46 However, the amount of hydrogen in the active layer/PL interface was similar for devices A and B. Because ALD-Al2O3 is an excellent hydrogen barrier,47 the temperature for the GI deposition on the top of the PL does not affect the TFT instability directly. However, in contrast to the structure of thin films for SIMS analysis, in which a-IGZO was completely covered with the Al2O3 PL, the contact between the GI of the TFT and the side edge of the exposed a-IGZO was noticeable despite the presence of the PL. Therefore, hydrogen can diffuse toward the active layer/GI interface via these contact areas to affect the reliability. These careful analyses confirmed that the increased hydrogen levels within the PL and GI were associated with improved PBTS stability. Therefore, we selected the structure of device A with good PBTS stability for fabricating monolithic oxide TFTs on the μLED array.
Before fabricating the monolithic μLEDs, we investigated the electrical properties of the a-IGZO TGBC TFTs of device A under various environments (Fig. S3, ESI†). Although the subthreshold swing, turn-on voltage, uniformity, and hysteresis values were excellent, the output characteristics showed that the drain current was not saturated at a high drain voltage. As the current saturation characteristics of TFTs have important effects on driving the μLEDs with constant luminance,48 the driving TFTs must have a saturation drain current at a specific drain voltage. In addition, the turn-on-voltage shift was −7.07 V during the NBIS stability measurements over 10000 s at −1 MV cm−1 and 0.5 mW cm−2 white light stress. Because the NBIS measurement environment corresponds to the major operation state of the μLED display,49 these unfavorable NBIS characteristics should also be addressed. Generally, the deterioration in NBIS stability originates from hydrogen impurities or ionized oxygen vacancies in metal–oxide semiconductors.47 In addition, the subgap density-of-states caused by the metal–hydrogen bonds or non-bridging oxygen hole centers can degrade the stability of NBIS.49,50 In our results, the NBTIS characteristics were poor compared to those of NBIS due to the trapping of the ionized oxygen vacancies into the defects of Al–OH or Si–OH in the gate insulator by light and thermal stress.51 Hence, to overcome these drawbacks, we inserted opaque light-blocking layers (Mo bottom gate) in the dual-gate structure.52
Fig. 4(a–d) illustrates the results of a DGBC a-IGZO TFT without applying any bottom-gate voltage, while Fig. 4(e–h) shows the corresponding results in the presence of a ground bottom-gate voltage. As shown in Fig. 4, various improved electrical properties were obtained simultaneously after a ground voltage was applied to the bottom gate. First, the ground voltage of the bottom gate rendered the turn-on voltage of the DGBC TFTs consistent regardless of the applied drain voltage [Fig. 4(a and e)]. Second, the saturated drain current was achieved, as identified from the output curves [Fig. 4(b and f)]. Third, the enhanced PBTS characteristics were also obtained; the turn-on-voltage shift during PBTS decreased from 1.16 V to 0.10 V [Fig. 4(c and g)]. These phenomena could be explained by the schematics in Fig. 4(d and h). The Von shift is caused by the electron accumulation or depletion after application of the bottom gate voltage (VBG), in which a negative VBG generates a positive shift and a positive VBG induces a negative shift [Fig. S4, ESI†].53 This shift can also be affected by introducing impurities serving as carriers, such as hydrogen. However, T-ALD Al2O3 used as the buffer oxide plays as an effective barrier, preventing impurities from entering the active interface layer. Therefore, the impact of these impurities can be effectively reduced.47 In the absence of electrical voltage with the bottom gate, the electric field caused by the drain voltage was transferred to that bottom gate. Thus, a backchannel in the a-IGZO active layer was induced close to the bottom gate. This induced backchannel can shift the turn-on voltage in a negative direction as the drain voltage increases. Furthermore, because the backchannel current can be increased as the drain voltage increases, it is difficult to gain drain saturation current characteristics in an output curve. Simultaneously, from the viewpoint of electrical stability, this backchannel surface serves as a charge trapping site at the active layer/BGI interface, thereby deteriorating the stability of PBTS.54 In contrast, when the ground voltage is applied to the bottom gate, the problems mentioned above are solved as the channel is formed only in the a-IGZO region close to TGI [Fig. 4(d and h)]. Indeed, the DGBC TFTs exhibited outstanding electrical properties, including low hysteresis, hard-saturation characteristics, and good PBTS stability, when a ground voltage was applied.
The PBTS stability of DGBC a-IGZO TFTs was measured over 10000 s at 60 °C and 1 MV cm−1 according to the BGI deposition temperatures (150 °C, 200 °C, and 300 °C) to clarify the effect of the deposition temperature of the BGI on the electrical reliability (Fig. S5, ESI†). The amount of hydrogen in the GI can improve the PBTS stability by diffusing to the a-IGZO/GI interface. Similarly, the amount of hydrogen in the BGI positively influences the improvement of PBTS stability, supported by the SIMS data (Fig. S5, ESI†). As the deposition temperature of the BGI decreased, more amount of hydrogen was detected in the channel. Consequently, the BGI deposited at low temperatures contained more hydrogen, thereby enhancing the PBTS stability. These results suggest that our BGI films deposited at low temperatures are suitable for fabricating highly stable DGBC TFTs. Thus, high-performance DGBC TFTs can be fabricated using the Al2O3 BGI deposited at 150 °C.
To monolithically integrate the optimized DGBC TFTs on the μLED array, a thick photo-patternable insulating layer is required to planarize the pixelated μLEDs. Therefore, an organic ILD (a negative photoresist, DW-10) was introduced, which was spin-coated and patterned via conventional photolithography. Because the ILD layer can withstand temperatures up to 230 °C, the μLEDs and oxide TFTs can be sufficiently integrated at this low temperature via monolithic fabrication. In order to prevent the diffusion of hydrogen and water vapor from ILD, an extra layer of T-ALD Al2O3 buffer oxide was applied.47,55 Additional experiments were also conducted to explore the extent to which the ILD will affect the TFT performance; we deliberately omitted the ILD in the DGBC TFT structure.
Fig. S6 (ESI†) shows the TFT transfer, output curves, and stability (PBTS, NBIS, and NBTIS) of DGBC a-IGZO TFTs without the ILD layer; Fig. 5 illustrates the corresponding data for the device with the ILD layer. Comparing both results, the ILD did not degrade the TFT performance owing to the excellent barrier properties exhibited by the Al2O3 buffer layer.47 In addition, Fig. S7–S11 (ESI†) depict the uniformity of device performance within a batch and between batches. The performance of devices was found to be highly consistent among testing samples from batch to batch regardless of the device location on the substrate. These results indicate that the monolithic fabrication reported in this article shows great reproducibility and reliability. Finally, we integrated DGBC TFT arrays on μLEDs via monolithic fabrication. Fig. 6(a and b) show the subpixel layouts of the μLED and TFT arrays and the FIB-SEM images of the sub-pixel surface, respectively. Remarkably, the device fabrication proceeded as designed. In contrast to the existing inorganic ILD materials, which may contain numerous voids at low temperatures, our organic ILD (DW-10) processed by spin coating provides several merits such as rapid processability, inexpensive production cost, and no requirement for additional planarization.
Fig. 6(c) illustrates an operational image of the μLED driven by DGBC TFT arrays. The scan line was swept from −15 to 20 V to ensure the proper performance of the TFT array; the data line, VDD, and VGround were 3.5, 5, and 0 V, respectively. As shown in Fig. 6(c), the phrase “KAIST 70 ppi” can be visualized, indicating that our unique methodology can achieve adequate monolithic fabrication of highly stable oxide TFTs on μLEDs under low temperature process conditions, compared to other previous achievements (Table 1). The thickness of the organic ILD on the μLEDs and unetched n-GaN was approximately 1.11 and 2.00 μm, respectively (Fig. S12, ESI†). This difference is considered reasonable as the μLED layer thickness is approximately 900 nm.
Novelty | Driving devices | Integration method | LED | LED/driving circuit fabrication substrate | TFT structure | Bonding material | TFT process temperature | Year/ref. |
---|---|---|---|---|---|---|---|---|
Active-matrix (AM) driving: 8 × 8 | PMOS | Flip-chip | GaN-μLED | Sapphire/silicon | — | Solder bump | — | 2009/12 |
High-brightness (106 cd m−2) | CMOS | Flip-chip | GaN-μLED | Sapphire/silicon | — | Bump-bonded (Au) | — | 2015/9 |
High-brightness (40![]() |
LTPS TFT | Flip-chip | GaN-μLED | Sapphire/glass | Conventional coplanar | Mo–Au layer | ∼450 °C | 2018/17 |
2D materials (transparent conducting film/channel) | Graphene FET | Monolithic with the use of the graphene transfer method | GaN-μLED | Sapphire | Bottom-gate bottom-contact | No information | No information | 2019/11 |
Large scale (12.1 inches), full-color | LTPS TFT | Mass transfer | μLED with color conversion materials | Glass | No information | No information | ∼450 °C | 2019/19 |
Large scale (4 inches), full-color | a-IGZO TFT | Mass transfer | μLED | Glass | Conventional coplanar | Solder bump | No information | 2020/24 |
Real-monolithic, highly-stable TFT (also AM driving) | a-IGZO TFT | Monolithic | GaN-μLED | Sapphire | Dual-gate | Organic inter-layer dielectric | Below 230 °C | This work |
Footnotes |
† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d2tc01905a |
‡ These authors contributed equally. |
This journal is © The Royal Society of Chemistry 2022 |