Open Access Article
This Open Access Article is licensed under a Creative Commons Attribution-Non Commercial 3.0 Unported Licence

Dual-gated mono–bilayer graphene junctions

Mingde Du *a, Luojun Du a, Nan Wei b, Wei Liu b, Xueyin Bai a and Zhipei Sun ac
aDepartment of Electronics and Nanoengineering, Aalto University, Espoo FI-02150, Finland. E-mail: mingde.du@aalto.fi
bDepartment of Applied Physics, School of Science, Aalto University, Espoo FI-00076, Finland
cQTF Centre of Excellence, Department of Applied Physics, Aalto University, Espoo FI-00076, Finland

Received 1st July 2020 , Accepted 30th September 2020

First published on 28th October 2020


Abstract

A lateral junction with an atomically sharp interface is extensively studied in fundamental research and plays a key role in the development of electronics, photonics and optoelectronics. Here, we demonstrate an electrically tunable lateral junction at atomically sharp interfaces between dual-gated mono- and bilayer graphene. The transport properties of the mono–bilayer graphene interface are systematically investigated with IdsVds curves and transfer curves, which are measured with bias voltage Vds applied in opposite directions across the asymmetric mono–bilayer interface. Nearly 30% difference between the output IdsVds curves of graphene channels measured at opposite Vds directions is observed. Furthermore, the measured transfer curves confirm that the conductance difference of graphene channels greatly depends on the doping level, which is determined by dual-gating. The Vds direction dependent conductance difference indicates the existence of a gate tunable junction in the mono–bilayer graphene channel, due to different band structures of monolayer graphene with zero bandgap and bilayer graphene with a bandgap opened by dual-gating. Simulation of the IdsVds curves based on a new numerical model validates the gate tunable junction at the mono–bilayer graphene interface from another point of view. The dual-gated mono–bilayer graphene junction and new protocol for IdsVds curve simulation pave a possible way for functional applications of graphene in next-generation electronics.


Introduction

Two dimensional (2D) materials, such as graphene,1 transition metal dichalcogenides (TMDCs)2 and black phosphorus (BP),3 have been extensively investigated due to their unique physical properties. Until now, plenty of remarkable electronic and optoelectronic properties have been demonstrated in 2D materials,4–6 such as ultrahigh carrier mobility of 200[thin space (1/6-em)]000 cm2 V−1 s−1 and reduced noise levels in suspended graphene,7,8 high current on/off ratio of 1 × 108 in monolayer MoS2 transistors2 and ambipolar transport in BP transistors,9 as well as an anisotropic photoresponse and chiral light emission in BP and WS2 based devices.10,11 Of particular importance, the electronic structures and physical properties of 2D materials strongly depend on the number of layers, and functional devices can be built based on this principle.12–15 For example, mono- and bilayer graphene possess massless Dirac-like energy band and nearly parabolic dispersion, respectively.6 The strongly distinct band structures of mono- and bilayer graphene make it possible to construct a lateral junction with atomically sharp interface.16–20 Furthermore, bilayer graphene under dual-gate modulation acquires an opened bandgap as large as 200 meV.21,22 Consequently, ambipolar transport and current on/off ratio larger than 104 are obtained in dual-gated bilayer graphene.23,24

Here, we investigate the interface between dual-gated mono- and bilayer graphene, with two types of top gate electrodes deposited above the graphene channels, covering only bilayer graphene (local top gate, LTG, Fig. 1a) or the whole graphene channel (global top gate, GTG, Fig. 1b). Transfer curves and IdsVds curves of the graphene devices are systematically measured with bias voltage Vds applied in opposite directions along the length of the channel. In addition, IdsVds curves of the devices are simulated based on a new numerical model with measured transfer curves as the only input. The results of both measurements and numerical simulation indicate that an electronic junction is successfully built at the mono–bilayer graphene interface, and this junction is considerably enhanced when the doping level of graphene is close to zero. The gate tunable mono–bilayer graphene junction is a promising candidate for the practical applications of graphene.


image file: d0na00547a-f1.tif
Fig. 1 Structure of mono–bilayer graphene junctions. (a and b) Architectures of dual-gated mono–bilayer graphene junction devices with local (a) and global (b) top gate electrodes. (c) Alignment between the Fermi level EF of monolayer (1L) and bilayer (2L) graphene when the doping level is close to zero. (d) Alignment between EF of mono- and bilayer graphene under heavy doping. A bandgap Eg is opened in bilayer graphene in the presence of top and bottom electrical displacement field DT and DB. (e) Optical microscope image of a typical mono–bilayer graphene flake. (f) RGS mapping of the flake in (e). The two areas with RGS of ∼0.06 and ∼0.12 are mono- and bilayer graphene, respectively.

Results and discussion

Architectures of the two different mono–bilayer graphene devices are demonstrated in Fig. 1a and b. The heavily doped silicon substrate works as the back gate electrode, where back gate voltage VBG is applied to modulate both mono- and bilayer graphene in the channels. Top gate electrodes with two different coverings are assigned to the devices, to modulate the graphene channels with top gate voltage VTG. The top gate electrode locally modulates bilayer graphene in the LTG device, while it globally modulates the entire graphene channel of the GTG device. In the presence of VBG and VTG, the induced bottom and top electrical displacement field DB and DT play a double role. Their difference DBDT determines net doping of mono- and bilayer graphene, and (DB + DT)/2 gives rise to bandgap opening in bilayer graphene.21,23 Therefore, a heterojunction is expected to be built between gapless monolayer graphene and bilayer graphene with an opened bandgap.

Conductance of the dual-gated mono–bilayer graphene is expected to highly depend on the Fermi level, as well as the opened bandgap in bilayer graphene. Here, we define a new parameter “effective gate voltage” (VBG-eff and VTG-eff correspond to back and top gate, respectively), that means, the voltage drop between gate electrodes and a point in the graphene channels. For example, when bias voltage Vds is applied on the drain electrode and the source electrode is grounded, the “effective top gate” VTG-eff in the channel ranges from VTGVds at the drain to VTG − 0 at the source. VTG-eff can be approximated uniform in the graphene channel when Vds is remarkably smaller than VTG, whereas it significantly changes along the length of the channel when Vds is comparable with VTG. As illustrated in Fig. S1, when Vds is applied on the electrode connected to monolayer graphene and the electrode connected to bilayer graphene is grounded, VTG-eff in the monolayer section is lower than that in the bilayer section, and this configuration is called the “Mb” mode. Otherwise, in the opposite case when the Vds is applied on the electrode connected to bilayer graphene, VTG-eff in the monolayer section is higher than that in the bilayer section, and this configuration is called the “Bm” mode. Since VTG-eff directly influences the doping level and further the conductance of graphene, the difference between VTG-eff in Mb and Bm modes results in different conductance of the graphene channel. Meanwhile, the change of VTG-eff results in different bandgap opened in bilayer graphene, which contributes to the conductance change of the graphene channel as well. As illustrated in Fig. 1c, when the net doping of graphene determined by DBDT is close to zero, the channel conductance can be readily tuned by a small shift of gate voltage. However, when the net doping of graphene is quite heavy (Fig. 1d), the channel conductance tends to saturate and is almost independent of gate voltage. Therefore, the IdsVds curves measured with Vds in opposite directions are expected to considerably differ from each other when the gate voltages approach the charge neutrality point (CNP).

In order to validate the principle design, mono–bilayer graphene flakes are carefully selected after mechanical exfoliation, followed by device fabrication. The optical microscope image of a typical graphene flake is shown in Fig. 1e, and its thickness is characterized by two methods. Based on the Raman spectrum shown in Fig. S2, mono- and bilayer graphene areas in this flake can be identified according to the ratio of 2D/G and Lorentzian fitting of 2D peaks.25 Additionally, the thickness of graphene could be confirmed by means of the relative green shift (RGS) based on optical microscope images.26–28Fig. 1f demonstrates RGS results of this typical graphene flake. The two areas with RGS values of ∼0.06 and ∼0.12 are mono- and bilayer graphene. The agreement between the results of Raman and RGS proves the reliability of RGS based graphene thickness identification in our experiments. Details of Raman and RGS based characterization are explained in the Experimental section. In the following sections, the thickness of the two graphene flakes shown in Fig. S3a and b is characterized using the RGS method. Based on the RGS results in Fig. S3c and d, both of the two flakes are composed of distinct mono- and bilayer graphene areas. Next, LTG and GTG dual-gated graphene devices are fabricated with the two flakes through a standard microfabrication process as illustrated in Fig. S4 and described in the Experimental section, and optical microscope images of the fabrication process are shown in Fig. S5.

Transport properties of the graphene junction devices are firstly investigated using IdsVds curves measured in Mb and Bm modes. Fig. 2a–c demonstrate IdsVds curves of the LTG device measured at various gate voltages, showing that the Ids of Mb measurements is different from that of Bm measurements. The significant difference between Ids of Mb and Bm measurements is a characteristic of the electronic junction in the mono–bilayer graphene channel, because the Ids of uniform channel measured in Mb and Bm modes should be the same. It is apparent that this Ids difference can be greatly modulated by VTG and VBG, similar to the modulation of graphene conductance in transfer curves. In addition, IdsVds curves of the GTG device measured at various gate voltages are demonstrated in Fig. 2d–f, where less difference between Ids of Mb and Bm measurements is found. In order to quantitatively compare the IdsVds curves of Mb and Bm measurements, the ratio of Ids measured in Mb and Bm modes (Mb/Bm Ids ratio) is calculated, and the results of LTG and GTG devices are shown in Fig. 2g and h, respectively. For both LTG and GTG devices, the Mb/Bm Ids ratio maintains ∼1.0 when Vds < 0.5 V, meaning that the mono–bilayer graphene works just like a uniform material. Nevertheless, this ratio greatly fluctuates around 1.0 when Vds > 1 V, indicating that an effective electronic junction is built at the mono–bilayer graphene interface. The maximum ratio is achieved at decreased VTG (−3 V, −4 V, and −5 V for the LTG device and 2 V, 0 V, and −2 V for the GTG device) when VBG is increased, as indicated by the white arrows in Fig. 2g and h. The Mb/Bm Ids ratio can be as high as roughly 1.3, in other words, the difference between Ids of Mb and Bm measurements is around 30%. The reason behind the gate tunable Mb/Bm Ids ratio could be explained by the transfer curves shown in the following section.


image file: d0na00547a-f2.tif
Fig. 2 I dsVds curves of mono–bilayer graphene junction devices. (a–c) IdsVds curves of the LTG device measured at VBG = −100 V, −70 V and −40 V. (d–f) IdsVds curves of the GTG device measured at VBG = 0 V, 50 V and 100 V. (g) Mb/Bm Ids ratio calculated with the data of the LTG device in (a–c). (h) Mb/Bm Ids ratio calculated with the data of the GTG device in (d–f). The maximum Mb/Bm Ids ratios, as indicated with white arrows, are obtained at decreased VTG when VBG is increased.

Fig. 3a and b show the transfer curves of LTG and GTG devices measured in the Mb mode. For both LTG and GTG devices, VTG at charge neutrality points (VTG-CNP) is shifted approaching negative when VBG is increased from −100 V to 100 V with 10 V steps, indicating that the doping level of graphene is jointly tuned by both VTG and VBG. As shown in Fig. 3a, channel resistance Rds at charge neutrality points (Rds-CNP) of the LTG device has a minimum value of 3.27 kΩ at VBG = 70 V, whereas the Rds-CNP of the GTG device monotonically decreases from 21.45 kΩ to 9.48 kΩ as VBG is increased. VTG-CNP values in the transfer curves of Fig. 3a and b are extracted and plotted in Fig. 3c, showing that VBG and VTG-CNP have a roughly linear relationship similar to the published results of dual-gated graphene devices.21,29 The transfer curves measured in the Bm mode and corresponding VTG-CNP, as shown in Fig. S6, exhibit little difference from the results in Fig. 3a–c, because the Vds of 0.1 V in transfer curves measurements leads to little difference between VTG-eff in Mb and Bm modes. VTG values for the maximum Mb/Bm Ids ratio indicated with white arrows in Fig. 2g and h are present as red in Fig. 3c. In particular, VTG-CNP of the GTG device at VBG = 100 V, 50 V and 0 V are almost the same as VTG where maximum Mb/Bm Ids ratios in the GTG device are achieved. The similar VBG dependence of VTG-CNP and VTG at the maximum Mb/Bm Ids ratios suggests that the junction between dual-gated mono- and bilayer graphene heavily depends on the overall doping of graphene determined by DB and DT. As shown in Fig. 3d, for both the LTG and GTG devices, the maximum Mb/Bm Ids ratio is increased when Rds-CNP is decreased. Since the decreased Rds-CNP mainly results from the decreased bandgap of bilayer graphene, it is reasonable to say that the gate tunable bandgap opened in bilayer graphene contributes to the generation of this directional junction as well.


image file: d0na00547a-f3.tif
Fig. 3 Transfer curves of mono–bilayer graphene junction devices measured in the Mb mode. (a and b) Transfer curves of LTG (a) and GTG (b) graphene junction devices measured at various VBG. The VBG ranges from −100 V to 100 V with 10 V steps in the measurements. (c) VTG at charge neutrality point (VTG-CNP) of the transfer curves in (a) and (b). The red markers indicate where maximum Mb/Bm Ids ratios are obtained, as shown in Fig. 1(g) and (h). (d) Dependence of Rds at charge neutrality point (Rds-CNP) in the transfer curves and maximum Mb/Bm Ids ratios in IdsVds curves on gate voltages.

As further proof of the relation between the mono–bilayer graphene junction and gate voltages, a novel numerical model for simulating IdsVds curves based on measured transfer curves is proposed. IdsVds curves of graphene devices at high electric field when Vds ≫ 0.1 V have been extensively studied based on both experimental measurements and theoretical simulation.30,31 Results of the various models can perfectly explain and quantitatively fit the measured IdsVds curves. Nevertheless, there are multiple parameters (such as gate voltages at CNP, capacitance of dielectric layers, drift velocity of carriers, etc.) in these models that need to be measured or estimated initially, increasing a certain degree of difficulty and complexity. For easing the simulation process, a new numerical model is proposed to simulate output IdsVds curves with measured transfer curves as the only input, without any additional parameters needed to be measured or estimated. In the new model, every point in the IdsVds curves is determined using the formula: Ids = Vds/Rds, where Rds is simulated channel resistance based on the measured transfer curves. Taking the measurement of the LTG device at VBG = −100 V as an example (Fig. 4a), the low bias voltage Vds = 0.1 V in transfer curve measurements has little effect on VTG-eff, therefore VTG-eff is assumed to be equal to VTG at every point in the graphene channel. The measured transfer curve describes a function: Rds = fR(VTG), as illustrated in Fig. 4b. Since the steps of VTG sweeping are quite small (0.28 V for LTG device measurements and 0.24 V for GTG device measurements), the curve between two measured points can be assumed to be linear. As illustrated in Fig. S7, the corresponding Rds for an arbitrary top gate V0 can be calculated with the formula:image file: d0na00547a-t1.tif, where V1 is the lower VTG point neighboring V0 in the transfer curve and ΔVTG is the sweeping step of VTG; details of the derivation of this formula are explained in Fig. S7. When top gate voltage VT0 and source–drain bias voltage Vd0 are applied on the device, the electric potential in graphene channel changes from 0 V at the source (S) electrode to Vd0 at the drain (D) electrode as illustrated in Fig. 4c. Initially, the distribution of electric potential in the channel is assumed to be linear. Namely, if the positions of the source and drain are defined as x = 0 and x = L, the electric potential at position x along the channel length is x/L × Vd0 (Fig. 4c). As a result, VTG-eff at position x in the graphene channel is VT0x/L × Vd0. Therefore, VTG-eff at different positions in the graphene channel ranges from VT0Vd0 to VT0, and total Rds of the channel can be calculated with the transfer curve in the range of VT0Vd0 to VT0 in Fig. 4b. To calculate total Rds, the whole graphene channel is divided into 100 sections with an identical length of L × 1/100 (Fig. 4d). Effective top gate VTG-eff of the n-th section at xn = L × n/100 is VT0xn/L × Vd0 = VT0n/100 × Vd0, and as a result, resistance of this section is Rn = fR(VT0n/100 × Vd0) × 1/100. Finally, resistance of the whole channel is calculated as Rds = ∑Rn = 1/100 × ∑ fR(VT0n/100 × Vd0), and the Ids at bias voltage Vd0 in IdsVds curve is Id0 = Vd0/Rds. The IdsVds curves of the GTG device can be simulated in a similar manner, with its own transfer curves as input.


image file: d0na00547a-f4.tif
Fig. 4 Schematic of the model for simulating Rds. (a) Nearly uniform distribution of electric potential in the graphene channel when Vds = 0.1 V is applied for transfer curves measurements. (b) Rds of graphene channel is assumed to be a function fR of VTG: Rds = fR(VTG), which is described by the transfer curves. Total Rds of the graphene channel measured at top gate voltage VT0 and source–drain bias voltage Vd0 can be calculated based on the curve in the colored range. (c) When top gate voltage VT0 and bias voltage Vd0 are applied on a graphene device, VTG-eff at different positions in the graphene channel are assumed to linearly change from VT0Vd0 at drain (D) electrode to VT0 at source (S) electrode. (d) The whole graphene channel is divided into 100 sections along its length, and the resistance R(xn) of a section at xn is defined as 1/100 of fR(VTG-eff(xn)), VTG-eff(xn) is the effective top gate at xn.

To assess the simulation model, simulated IdsVds curves of LTG and GTG devices are compared with respect to the measured results. Fig. 5a–d present the simulated (Sim) IdsVds curves of LTG and GTG devices at the gate voltages in Fig. 2c and f, as well as the measured (Mea) results demonstrated for straightforward comparison. Apparently, the simulation accuracy seems quite acceptable at most of the (VTG, Vds) combinations, while the difference between simulated and measured IdsVds curves is enlarged at specific (VTG, Vds) combinations. This rule can be quantitatively understood with the ratio of simulated and measured Ids (Ids Sim/Mea ratio) shown in Fig. 5e–h, where the white dashed lines are defined by VTGVds = VTG-CNP. The Ids Sim/Mea ratio fluctuates between 0.9 and 1.1 at (Vds, VTG) combinations far from the white dashed lines, in other words, the simulation error is less than 10% when the graphene is heavily doped by dual-gating. Therefore, the dual-gated mono–bilayer graphene works like a uniform material as assumed in the simulation model, and this result could be interpreted with the transfer curves in Fig. 2a and b, indicating that Rds tends to be independent of VTG, when VTG is far from CNPs. In contrast, the Ids Sim/Mea ratio at (Vds, VTG) combinations close to the white lines can be lower than 0.4. In other words, the simulation error is larger than 60% when the doping level of dual-gated graphene is close to zero, where Rds values of the devices are substantially sensitive to the shift of VTG according to the curves in Fig. 3a and b. The Ids Sim/Mea ratios of LTG and GTG devices under other conditions shown in Fig. S8 also confirm the dependence of simulation error on VTGVds. Since the graphene channel is assumed to be uniform in the simulation model, the considerable simulation error indicates that the graphene channel does not work as a uniform material, in other words, there is a junction built at the dual-gated mono–bilayer graphene interface. Accordingly, it is reasonable to say that the dual-gated mono–bilayer graphene works like a uniform channel at heavy doping, while like a heterojunction when the doping is close to zero. The gate dependent Mb/Bm Ids ratios and Sim/Mea Ids ratios suggest that a gate tunable electronic junction is successfully built in dual-gated mono–bilayer graphene, and the junction tends to be remarkable when the dual-gating induced doping is close to zero.


image file: d0na00547a-f5.tif
Fig. 5 Comparison between simulated and measured IdsVds curves. (a–d) Measured (Mea) IdsVds curves shown in Fig. 2 and the simulated (Sim) results based on transfer curves in Fig. 3 and S6.VBG of LTG and GTG devices are −40 V and 100 V. (e–h) Ratio of Ids Sim/Mea calculated with the data in (a–d). The red areas with Sim/Mea ≈ 1 correspond to high accuracy Rds simulation, while the blue areas with Sim/Mea ≪ 1 present low simulation accuracy, because the simulated Ids is much smaller than the measured counterpart. The white dashed lines correspond to VTGVds equals to VTG-CNP in Fig. 3 and S6.

Conclusion

In conclusion, directional electronic transport across a dual-gated mono–bilayer graphene interface is systematically investigated, and a new protocol for IdsVds curve simulation is proposed. The measured IdsVds curves demonstrate that the mono–bilayer graphene has different conductance under bias voltage Vds in opposite directions (Mb and Bm modes), indicating that an electronic junction is built at the atomically sharp mono–bilayer graphene interface. Additionally, the gate dependent Mb/Bm Ids ratio and IdsVds curve simulation indicate that this electronic junction is gate tunable, and the junction could be enhanced when the doping level of graphene is close to zero. Overall, the electrical measurements and numerical simulation prove the existence of a gate tunable junction at the dual-gated mono–bilayer graphene interface. Besides, the proposed simulation model explains IdsVds curves at a high electric field in a novel way and simplifies the prediction of output IdsVds curves with measured transfer curves. In the future, the mono–bilayer graphene junction can be enhanced by enlarging the bandgap opening of bilayer graphene with novel device structures,23,24 thus the junction would be more functional and valuable. These results indicate that dual-gated mono–bilayer graphene junctions are promising candidates for functional electronics in the future.

Experimental section

Preparation and characterization of graphene flakes

Graphene flakes are obtained by scotch tape based mechanical exfoliation of highly oriented pyrolytic graphite (2D semiconductors), and transferred to a cleaned Si wafer with a 280 nm thick SiO2 top layer. The thickness of graphene flakes is critical in this project, so that they are carefully characterized by two methods before device fabrication. The first method is based on the color contrast of the optical microscope (Olympus BX60) images. Green channel G0 in the RGB value of pixels in the optical images is extracted with a custom MATLAB script, and RGS is defined as RGS = (G0Gs)/Gs, where Gs is the averaged green value of bare Si/SiO2 areas.26–28 The areas of mono- and bilayer graphene should have RGS values of ∼0.06 and ∼0.12, respectively. The second method is the Raman spectrum. Graphene flakes are characterized using a Raman spectrometer (Horiba LabRAM HR) with a 514 nm excitation laser. According to the ratio of 2D/G and Lorentz fitting of 2D peaks, areas of mono- and bilayer graphene can be identified.25 Consistency between the results of RGS and Raman characterization indicates that RGS characterization based on our equipment is reliable for identifying the graphene thickness.

Device fabrication

The graphene devices are fabricated through the process flow illustrated in Fig. S4. Firstly, source and drain electrodes of 5 nm/100 nm Ti/Au are deposited through standard electron beam lithography (EBL, Vistec EBPG 5000), electron beam evaporation (MASA IM-9912) and lift-off process. Graphene areas between the source and drain electrodes are further patterned to a regular shape with EBL and reactive ion etching (RIE, Oxford Instruments PlasmaLab 80 Plus), to avoid the influence of interface states.16 The residues of EBL resist after RIE is removed with acetone, followed by high vacuum annealing (AML – AWB wafer bonding machine) at 200 °C for 2 hours. Right after annealing, the devices are transferred to evaporation equipment and a 2 nm thick Al layer is deposited on graphene. Subsequently, the Al layer is oxidized on a 130 °C hotplate in air for 3 min to form a Al2O3 seeding layer.29 Above the Al2O3 layer, a 20 nm thick HfO2 layer is grown by atomic layer deposition (ALD, Beneq TFS-500) at 200 °C, with TDMAH and water used as hafnium and oxidant sources. Finally, top gate electrodes are deposited through a process same to that of source and drain electrodes. The fabricated devices are connected to a printed circuit board for electrical measurements by wire bonding (Delvotec 53XX). Optical microscope images of the fabrication process are demonstrated in Fig. S5, showing that source and drain electrodes are arranged to be parallel with the interface between mono- and bilayer graphene.

Electrical measurements

All the electrical measurements in this article are carried out with a semiconductor device parameter analyzer (Agilent B1500A) under ambient conditions. The IdsVds curves are measured by sweeping the bias voltage Vds at various combinations of VTG and VBG, and transfer curves are measured by sweeping the top gate voltage at various back gate voltages. All the measurements are conducted at Vds in opposite directions (Mb and Bm modes) along the channel length.

Numerical simulation

Values of simulated Rds and Ids are calculated with a custom MATLAB script based on the measured transfer curves.

Conflicts of interest

The authors declare no competing financial interest.

Acknowledgements

We acknowledge the provision of facilities by Aalto University at the OtaNano – Micronova Nanofabrication Centre and the OtaNano – Low Temperature Laboratory, and the funding from the Academy of Finland (276376, 295777, 312297, and 314810), Academy of Finland Flagship Programme (320167, PREIN), the European Union's Horizon 2020 research and innovation program (820423,S2QUIP), and ERC (834742).

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Footnote

Electronic supplementary information (ESI) available. See DOI: 10.1039/d0na00547a

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