Dual-gate low-voltage transparent electric-double-layer thin-film transistors with a top gate for threshold voltage modulation

Abstract

Dual gate (DG) low-voltage transparent electric-double-layer (EDL) thin-film transistors (TFTs) with microporous-SiO₂ for both top and bottom dielectrics have been fabricated, both dielectrics were deposited by plasma-enhanced chemical vapor deposition (PECVD) at room temperature. The threshold voltage of such devices can be modulated from −0.13 to 0.5 V by the top gate (TG), which switches the device from depletion-mode to enhancement-mode. High performance with a current on/off ratio (∼2.1 × 10⁶), subthreshold swing (76 mV per decade), operating voltage (1.0 V), and field-effect mobility (∼2.6 cm² V⁻¹ s⁻¹) are obtained. Such DG TFTs are promising for ion-sensitive field-effect transistors sensor applications with low-power consumptions.

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Introduction

In recent years, dual-gate (DG) thin-film transistors (TFTs) with both a top-gate (TG) and a bottom-gate (BG) in the same device structure have been studied by more and more scientists,^1–5 as the configuration offers increased control of tuning the threshold voltage (V_th) of TFTs. Proper V_th can ensure low power consumption and appropriate operation-mode,^6,7 so DG TFTs are promising for biological/chemical sensor applications and fabrication of complicate circuits.^8,9 Tuning threshold voltage by varying thickness has been reported by Lee et al.,¹⁰ however, the TFTs with a thick body operating in depletion-mode suffer from enlargement of the subthreshold swing and the leakage current.

In this letter, DG a-IGZO electric-double-layer (EDL) TFTs that can adjust the threshold voltage in both positive and negative directions with a TG have been fabricated on glass substrates at room temperature. By changing the voltage biases of BG, the threshold voltage can be significantly moved from −0.13 to 0.5 V, so such DG TFTs can operate in both depletion-mode and enhancement-mode. Besides, as compared with the standard single gate devices (STD devices), this DG TFT with a TG shows a lower leakage current and an almost unchanged subthreshold swing. Such transparent devices also exhibit a field-effect mobility of ∼2.6 cm² V⁻¹ s⁻¹, high on/off ratio of ∼2.13 × 10⁶, low subthreshold swing of 76 mV per decade at a low operating voltage of 1.0 V. These results demonstrate potential applications in low power and high performance transparent electronics. The switching stability of such DG TFTs with a top gate is also discussed.

Experimental

The entire process of device fabrication was performed at room temperature. First, a 2 μm-thick SiO₂ electrolyte film was deposited by plasma-enhanced chemical vapor deposition (PECVD) on transparent conducting ITO glass substrates using SiH₄ and O₂ mixture as reactive gases. Second, a 40 nm-thick IGZO active channel was deposited by RF magnetron sputtering using a power of 100 W and a working pressure of 0.5 Pa in argon. Third, 2 μm-thick SiO₂ electrolyte film was deposited by plasma-enhanced chemical vapor deposition (PECVD) using a SiH₄ and O₂ mixture as reactive gases as top dielectric layer. At last, the fabrication of the TFT arrays was completed by RF sputtering of 200 nm-thick highly conducting ITO source/drain and top-gate electrodes through a nickel shadow mask. The channel length and width are 80 and 1000 μm, respectively. For comparison, the standard single gate devices were also fabricated under the same condition. Optical analysis is performed by ultraviolet spectrophotometer (Lambda 950). Electrical characterizations of both STD and DG TFTs were performed by a semiconductor parameter analyzer (Keithley 4200 SCS).

Results and discussion

Fig. 1a shows the schematic diagram of the fabricated dual-gate low-voltage transparent EDL TFT with the driving bottom gate and the control top-gate. The optical transmission spectra of as-fabricated TFT arrays on glass substrates (the thickness of the glass substrate is 1.5 mm) is shown in Fig. 1b, the TFT arrays on glass substrates show an optical transmittance of over 80%. The inset in Fig. 1b shows a photograph of a transparent TFT array chip placed over some background text. We can see the letter through the TFT chip, indicating the TFT arrays are fully transparent to visible light.

Fig. 1 (a) Structure of the dual-gate TFT with the driving bottom gate and the control top-gate. (b) Optical transmission spectra of such TFT arrays on glass substrates. Inset: an optical image of the TFT arrays placed on background text.

As shown in Fig. 2a, like other microporous-SiO₂ in the previous work reported by our groups,¹¹ these TG and BG dielectrics of such DG TFTs also show huge specific capacitance of ∼4 μF cm⁻² at 20 Hz, which leads to a low operating voltage of 1.0 V. Fig. 2b shows the leakage current of the STD and DG TFTs. The leakage current of STD TFTs was ∼1 nA, however, the leakage current of DG TFTs was less than 0.2 nA, which was much smaller than that of solid polymer electrolytes or ionic liquids.^12,13 Despite the nanopores existed in double gate dielectrics, the leakage current is five orders of magnitude smaller than the channel current, which guarantees the device performance will not be affected by the leakage current.

Fig. 2 (a) Specific gate capacitance of the TG and BG dielectrics of such DG TFTs. (b) Leakage current of the STD and DG TFTs.

The initial electric characteristics of such device are estimated as the conventional BG TFTs. The electron field-effect mobility (μ_sat) in the saturation regime is calculated using the relationship I_ds = (WC_bg/2L)μ_sat(V_bg − V_th)², where L = 80 μm and W = 1000 μm are the channel length and width, respectively. The field-effect mobility is calculated to be ∼2.6 cm² V⁻¹ s⁻¹ at V_ds = 1.0 V, V_bg = 1.0 V. The corresponding carrier density of the IGZO channel layer is estimated to be 3.5 × 10¹³ cm⁻² by N = C_bg (V_c − V_on)/e. C_bg = 4.0 μF cm⁻² is the bottom gate specific capacitance at 20 Hz. The V_c = 1.0 V is the bottom gate voltage bias for mobility estimation. V_on = −0.4 V is the turn-on voltage of the device without a top gate bias. Fig. 3a shows the transfer characteristics of the DG TFTs in the saturation regime (V_ds = 1.0 V) with top gate voltage biases in the range from 2.0 V to −2.0 V. All transfer curves were sweeping from negative to positive with a negative bias stress time of 10 s and a sweep rate of 50 mV s⁻¹. The hysteresis window is less than 0.05 V upon sweeping forward and backward without obvious bias stress effect. Thus, we only plotted the result of forward sweeps. When V_tg is swept from 2.0 V to −2.0 V, the transfer curves systematically shift from left to right. Fig. 3b shows the (I_ds)^1/2–V_bg transfer curves with different V_tg. The threshold voltage (V_th), indicated by the intercepts lines with the V_bg axis, moves from a negative value of −0.13 V to a positive value of 0.5 V. These results indicate that an effectively electrostatic coupling is realized between the top gate and the IGZO channel. By the way, subthreshold swing of ∼76 mV per decade and current on/off ratio of ∼2.1 × 10⁶ are almost constant at various voltage biases of top gate.

Fig. 3 (a) The transfer characteristics of the dual-gate TFTs at different top-gate voltage biases. (b) (I_ds)^1/2–V_bg curves of the same device.

Fig. 4a and b show the output characteristics of transparent dual-gate TFTs with different voltage bias of top gate. Linear behaviours of I_ds at low V_ds are observed, indicating that good ohmic contact between the IGZO channel layer and ITO source/drain electrodes were realized. When V_tg was changed from 2.0 V to −2.0 V, depletion-mode was gradually changed to enhancement-mode. So dual-gate configuration provides more flexibility in device operation.

Fig. 4 Output characteristic of the dual-gate TFTs operated at enhancement mode (a) when V_tg = −1.0 V, at depletion mode (b) when V_tg = 1.0 V.

The extracted V_th and subthreshold swing (S) are presented in Fig. 5a as a function of the V_tg for DG TFTs. The asymmetric behaviour of V_th shift is due to the changeable C_{bg-dielectric} and C_{tg-dielectric} at different (positive and negative) V_tg. When V_tg ≥ 0 V, all ITO electrodes are highly conducting, and the capacitance values of C_{bg-dielectric} (C_bd) and C_{tg-dielectric} (C_td) are equivalent to the EDL capacitance of SiO₂-based electrolyte. When V_tg < 0 V, C_bd and C_td will become smaller due to the IGZO film depletion effect induced by the negative V_tg. According to the equation: ΔV_th = ΔV_tgC_td/[C_td + (C_bd + C_td)], a larger V_th shift can be obtained when V_tg < 0 V. These results indicates that the V_th is very sensitive to the changes in the surface potential of the top gate dielectric region,¹⁴ so such DG TFTs are very promising for ion-sensitive field-effect transistors sensor applications. Simultaneously, the S has a weak dependence on the top gate bias, which indicates the value of S was almost unaffected by the V_tg. Such DG TFTs were continuously switched between the ON- and OFF-states in dynamic stress tests (periodic square-wave pulses of V_bg = −0.5 to −1.0 V, V_tg = 0 V, and V_ds = 1.0 V), as shown in Fig. 5b. A drain-current on/off ratio of larger than 10⁵ was maintained, and no obvious drain current decrease was observed. This result suggests very good switching stability of the DG TFTs with a top gate.

Fig. 5 (a) The threshold voltage and subthreshold swing of the dual gate TFTs at different V_tg. (b) The switching stability driven by square-wave pulses with a period of 1 Hz.

Conclusions

In conclusion, dual-gate low-voltage transparent EDL TFTs gated by PECVD-deposited microporous-SiO₂ were fabricated with a top gate. Carrier density of the channel, V_th and operation mode of the devices can be tuned by the top gate. The V_th of such device can be systematically tuned from −0.13 V to 0.5 V by using a top-gate bias ranging from 2.0 V to −2.0 V. The combination of the controllability of V_th, room temperature process, low-voltage operation of the transparent dual-gate TFTs are very promising for ion-sensitive field-effect transistors sensor applications.

Author contributions

Thin-film transistor and device performance was fabricated and characterized by W. D. The manuscript was prepared by W. D. and Y. T. W. D. examined and commented on the manuscript. The project was guided by W. D.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This project was supported by Doctoral Science Foundation of Hunan Normal University (0531120).

Notes and references

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