Polarity-controllable MoS₂ transistor for adjustable complementary logic inverter applications

Abstract

In this work, we introduce a MoS₂-based field effect transistor that can alternately operate either as a p-type or an n-type semiconductor in the same device. The proposed device is built with an adjustable threshold voltage (V_th), which can be varied by adding a layer of plasma-oxidized dielectric at the top gate structure. This facilitates a surplus of oxygen due to the relatively thin grown dielectric layer and the creation of negative charges in that layer instead of the usual ones of positive polarization in the bottom dielectric layer. Consequently, the V_th shifts and the top gate structure switches from the typical n-type to p-type while the n-type behaviour remains in the application of the bottom-gate voltages. The V_th can be tuned further by applying a gate pulse input at the top gate. Accordingly, we have demonstrated complementary logic inverters with adjustable device characteristics that are controllable by the polarity of charges induced in the device's oxide layer. This is a big step towards the concurrent implementation of both n-type and p-type characteristics in a single device.

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New concepts

The cost of production has always been an important consideration in manufacturing semiconductor devices and circuits. In this study, the MoS₂-based field effect transistor has been exhibited with the selective operation of either p-type or n-type characteristics in the same device. The V_th for device characteristics can be slightly adjusted further by applying a gate pulse input. Accordingly, complementary logic inverters with adjustable device characteristics have been demonstrated. Compared to the existing research, our device could save almost twice the process time and price of an individual device. This concept is useful and valuable for the future fabrication of advanced devices. We believe that these discoveries will not just lower the cost of production but will also revolutionize future complementary metal-oxide–semiconductor technology.

Monolayer transition-metal dichalcogenides (TMDs) have recently received immense research interest due to their outstanding electrical, mechanical, and optical properties for electronic device applications.^1–6 Their unique features are ideal for the development of ultrathin, lightweight, flexible, and extremely rugged devices that can operate on arbitrary surfaces.^7–9 Moreover, TMDs a have large on/off ratio and a relatively small sub-threshold swing, which makes them one of the most suitable options for logic-circuit applications^10–12 such as a complementary metal-oxide–semiconductor (CMOS) inverter.

CMOS inverters, commonly used in digital logic circuits, are also employed in analog applications, such as amplifier stages¹³ and comparators.^14,15 One of the comparator's main applications is the analog-to-digital converter (ADC) in which performance is evaluated based on two factors: power dissipation and speed. Flash ADC is the fastest ADC ever built so far; but despite its remarkable speed, it still exhibits large power consumption due to multiple comparators used to complete the conversion. A common way of solving this issue is to use a Threshold Inverter Quantization (TIQ) comparator,^14,15 which has low power consumption due to the absence of a resistor array typically used in other comparator designs to generate the reference voltage. Note that the reference voltage of TIQ depends on the threshold voltage (V_th) of its CMOS inverter and that the inverter's gate width and length determines the value of this V_th. Therefore, if the inverter's V_th is tunable, then there is no need to design comparators with different gate dimensions. As a result, the ADC design process will be greatly simplified and the cost of production will be reduced accordingly.

Moreover, the ability to tune V_th is very important in finding out the device's optimal power consumption and performance¹⁶ but this seems hard to employ in atomically-thin TMD-based devices.¹⁷ In conventional CMOS technology, the V_th can be controlled by tuning the channel region doping level; however, general ion implantation is not suitable for TMDs because the technique can cause fatal damage to its crystal structure.¹⁸ A more feasible method to control the V_th of the TMD-based field effect transistors (FETs) was reported and it is by changing the dielectric layer on top of the channel.^19–21 This change in the V_th is induced by the variation of the interface charges in the dielectric layer. One may also trigger off either a p-type or an n-type behaviour on the device depending on what type of process is used to grow the dielectric material.

A complementary logic inverter, which has both p- and n-type constituent transistors, is required not just for comparators but for most circuits in general. However, the difference in parameters between the PMOS and NMOS necessitates almost twice the processing time of an individual device. This can be resolved by building a single transistor that shows both p- and n-type behaviour. Interestingly, when SiO₂ is grown by a thermal oxidation process on the channel, the positive charge state is dominant in the oxide layer,^22–25 which may lead to an n-type behaviour with MoS₂ channels. Meanwhile, when SiO₂ is grown by a plasma oxidation process, which is a method that has a low deposition rate leading to relatively thin grown layers, a surplus of oxygen is induced in the dielectric material. This time, the negative charge state is more stable²⁶ in the oxide layer that may result in a p-type behaviour with MoS₂ channels. A similar idea about polarity change induced by dielectric materials MgO in black phosphorus has been reported.^27,28 It is possible to employ the two aforementioned dielectric layer types as gate oxides on its back and top gate structures respectively, a MoS₂ FET device can exhibit either an NMOS or a PMOS behaviour accordingly. Pair this with an adjustable V_th feature and the number of comparators in a circuit as well as the cost of production can be significantly reduced. In this paper, we have demonstrated a polarity-controllable MoS₂-based field effect transistor that operates alternately as a PMOS (by its top gate) or an NMOS (by its back gate) and is built with an adjustable threshold voltage. The polarity of charges induced in the device's oxide layers controls the characteristics of the device, resulting in either a p-type or an n-type behaviour at its gate structures, thus the term polarity-controllable. We expect that our proposed device can usher in more practical and breakthrough applications in future CMOS technology.

In this study, a double gate V-shaped MoS₂ field effect transistor with 12 nm length (L) and 100 nm width (W) was fabricated as illustrated in Fig. 1(a). Notice the two gates that are located at the top (top gate) and at the bottom (back gate) of the device. The optical microscope image of the actual device with the top gate, as well as an inset showing its scanning electron microscope image of the MoS₂ grown along with the electrodes without the top gate, are displayed in Fig. 1(b). Details about the fabrication of the MoS₂ device are reported in our previous work.²⁹ The material characterization such as Raman, photoluminescence spectrum and transmission electron microscope images are displayed in Fig. S1 (ESI†), indicating that the uniformity is smooth with a thickness around 5 nm in a multilayer formation. In order to identify the influence of the dielectric layer to the device characteristics, two kinds of samples were built – the proposed device and a reference device. The reference device (Fig. 1(c)) has its MoS₂ sheet capped with a 10 nm HfO₂ dielectric layer as the top gate. On the other hand, the proposed device (Fig. 1(d)) has a 5 nm SiO₂ layer grown using a plasma oxidation process on the MoS₂ sheet before getting capped by a 10 nm HfO₂ top gate layer. The SiO₂ near the back gate of both kinds of samples is developed using the thermal oxidation process.

Fig. 1 The schematic diagram and characterization of the double gate MoS₂ field effect transistor structure. (a) The schematic plot of the double gate MoS₂ field effect transistor in which the yellow ribbons are the MoS₂ layers grown in between two poly-Si electrodes (black-shaded areas); and top gate metals are deposited using TaN/TiN. (b) The top view of the optical micrograph of the double gate device. The inset shows the corresponding scanning electron microscope image of the bottom gate device (before fabricating the top gate structure). (c) and (d) are the cross-sectional images of the transmission electron microscope images showing the thickness of the MoS₂ and the dielectric layers in the reference and proposed device, respectively.

The measurement setup is shown in Fig. 2(a) and the transfer curve in the back gate device before fabricating the top gate structure is shown in Fig. 2(b). The mobility of the back gate MoS₂ FET is estimated to be about 1.2 × 10⁻² cm² V⁻¹ s⁻¹. After fabricating the top gate structure, both the proposed and the reference devices exhibit an n-type behaviour when the gate voltage was applied on the back gate (back gate operation). However, the proposed device, which has a plasma-oxidized SiO₂ dielectric layer in between MoS₂ and HfO₂, showed a p-type behaviour when the gate voltage was applied on the top gate (top gate operation). This is in contrast with the reference device, which still exhibits an n-type behaviour regardless of which gate is used in the measurement. This phenomenon in the proposed device can distinguishingly be seen in Fig. 2(c) and (d), in which the related mobilities are separately calculated to be 1.05 × 10⁻⁵ cm² V⁻¹ s⁻¹ and 3.2 × 10⁻² cm² V⁻¹ s⁻¹, along with the other important features of bias voltage dependence presented in Fig. S2 (ESI†). Therefore, the proposed device can alternately operate as an n-type, by using its back gate, or a p-type, by using its top gate as a gate terminal. This can also be observed in its transfer curves (Fig. 2(e)), in which the related mobilities are respectively calculated to be 6.4 × 10⁻³ cm² V⁻¹ s⁻¹ by back gate operation and 3.89 × 10⁻³ cm² V⁻¹ s⁻¹ by top gate operation. Similar behaviour in another device is shown in Fig. S3 (ESI†) and the general leakage current during the measurement in the proposed devices is a few pA as also shown in Fig. S4 (ESI†). It is noted that the mobility and current density are dramatically decreased as one compares between before and after directly depositing HfO₂ on MoS₂ (Fig. 2(b) and (c)). With the information on the transfer curves in the operation of the back gate before and after top gate process, as shown in Fig. S5 (ESI†), we can eliminate contact contribution and conclude that the low current level and low mobility are mainly caused by the damage of directly depositing dielectric materials on top of MoS₂ by plasma collision.

Fig. 2 Electrical characterization of double gate MoS₂ field effect transistor. (a) The measurement setup. (b) The transfer characteristics of the device's (b) back gate structure at V_d = 2.1 V (before fabricating the top gate structure) as well as its top gate structure, (c) without SiO₂ and (d) with the SiO₂ layer, are shown. (e) The device top gate with the SiO₂ layer shows transfer characteristics with both PMOS and NMOS behavior.

This behaviour – having two opposite characteristics – may be due to the difference in the dielectric oxide charges of the proposed device's top gate and the back gate structure. At no gate bias conditions in the reference device, the HfO₂ dielectric layer has positive oxide charges that would induce a band down-bending (Fig. 3(a)). This down-bending would reduce the effective Schottky barrier between the contact metal electrode and MoS₂, thus electrons are transported easily across the metal and conduction band through a thermal-assisted tunneling process (Fig. 3(b)).^20,30 On the other hand, at no gate bias condition in the proposed device, the negative oxide charges formed in the plasma SiO₂ dielectric layer caused the energy band in the MoS₂ interface to bend up (Fig. 3(c)). This led to a decrease in the electron current since the effective Schottky barrier height for electrons was enlarged; and, at the same time, it caused an increase in the hole current, due to a reduction of the effective Schottky barrier height for holes. As a result, the Fermi level of MoS₂ was effectively decreased (Fig. 3(d)). Note that once the effective Schottky barrier heights for electrons and holes become comparable at zero gate bias, the device is more likely to behave as an ambipolar transistor.²⁰ In addition, one may notice that the proposed device's transfer characteristics demonstrate a better performance compared to the reference device due probably to the insertion of the thin SiO₂ dielectric layer to prevent damage from directly depositing HfO₂ on top of MoS₂.

Fig. 3 Vertical and horizontal schematic energy band diagrams of the double gate MoS₂ field effect transistor. (a) and (b) indicate the effect of capping the MoS₂ with only an HfO₂ dielectric layer, while (c) and (d) indicate the effect of capping it with both HfO₂ and SiO₂ dielectric layers. The band diagrams show the effective Schottky barrier heights for electrons/holes at the contact edges.

The proposed device's mechanism is supported by the corresponding theoretical calculations. The following assumptions were set: MoS₂ doping concentration, N_d, equal to 10¹¹ cm^−2 31,32 and band gap energy, E_g, equivalent to 1.4 eV;³³ work function, ϕ′, of TaN and Si equal to 4.5 eV³⁴ and 4.25 eV³³ respectively; electron affinity, χ′, in the SiO₂–MoS₂ interfaces having values of 3.7 eV³³ accordingly; permittivity, ε, of MoS₂, SiO₂, and HfO₂ recorded as 11ε₀,³⁵ 3.9ε₀,³⁶ and 23ε₀³⁷ respectively; and the intrinsic concentration, n_i equal to 10¹⁰ cm⁻².³⁸ The details of the corresponding calculations for each value are shown in the ESI.†

In general, when a positive bias is applied onto the gate terminal of the device, the work function difference, ϕ_ms, between the metal and the semiconductor, and the threshold voltage, V_th, are given by the equations

ϕ_ms = ϕ_m′ − (χ′ + E_g/2e + ϕ_B) (1)

and

V_th = (|Q_SD(max)′| − Q_SS′)(t_ox/ε_ox) + ϕ_ms + 2ϕ_B (2)

respectively. Here, ϕ_m′ is the modified work function of the metal; χ′ is the modified electron affinity of the semiconductor; Q_SS′, is the trapped oxide charges in the dielectric layer and in its interface with the semiconductor; t_ox and ε_ox are the thickness, and dielectric constant of the oxide layer, respectively; and ϕ_B is the semiconductor potential. In the presence of two dielectric layers, such as our top gate structure, V_th can be expressed as

V_th = (|Q_SD′(max)|(t_ox1/ε_ox1 +t_ox2/ε_ox2) − Q_SS1′(t_ox1/ε_ox1) − Q_SS2′ (t_ox2/ε_ox2)) + ϕ_ms + 2ϕ_B (3)

with Q_SS1′, t_ox1 and ε_ox1 referring to the 1st dielectric layer and Q_SS2′, t_ox2, ε_ox2 for the 2nd dielectric layer. In contrast, when a negative bias is applied, the following equations take place

ϕ_ms = ϕ_m′ − (χ′ + E_g/2e − ϕ_B) (4)

and

V_th = (−|Q_SD′(max)| − Q_SS′)(t_ox/ε_ox) + ϕ_ms − 2ϕ_B (5)

V_th = (−|Q_SD′(max)|(t_ox1/ε_ox1 + t_ox2/ε_ox2) − Q_SS1′(t_ox1/ε_ox1) − Q_SS2′(t_ox2/ε_ox2)) + ϕ_ms − 2ϕ_B (6)

The semiconductor potential, ϕ_B, can be described by the relation:

ϕ_B = V_tln(N_d/n_i) (7)

where V_t is the thermal voltage. Knowing the value of ϕ_B, the maximum inversion width (X_dT) is calculated below.³⁹where T is the semiconductor thickness. We can calculate the 2D material maximum width of the depletion region, X_dT, which is about 1.62 × 10⁻⁵ cm in our case. The charge in the depletion region at strong inversion, |Q_SD′(max)|, can then be determined using the formula

|Q_SD′(max)| = eN_dX_dT (9)

which gives us a value of 6.48 × 10⁻⁷ C cm⁻². These values will be useful in the succeeding calculations.

During the back gate operation, applying a positive gate bias gives a ϕ_ms that is equal to −0.209 eV and a measured V_th of 6.4 V (Fig. 2(e)). Using eqn (2), the corresponding trapped oxide charges Q_SS′ is calculated to be around −9.87 × 10⁻⁸ C cm⁻². Meanwhile, applying a negative bias, still on the back gate of the device, gives a ϕ_ms that is equal to −0.091 eV. Here, considering the ambipolar characteristics of the device and in order to make the theoretical predictions closer to our experimental results, we assume a V_th of −8 V. As a result, the Q_SS′ is found to be around 2.48 × 10⁻⁷ C cm⁻². Basically, Q_SS′ is composed of bias-dependent border traps-induced charges (Q_V) which border traps related descriptions are shown in Fig. S6 (ESI†) and bias-independent oxide charges (Q_S) which includes fixed oxide charges, mobile ionic charges, and oxide trapped charges to name a few. Due to the bias-dependence of Q_V, the relationship of Q_SS′ with Q_S and Q_V can be expressed using two different equations depending on the polarity of the applied gate bias, using these equations,

By solving the simultaneous equations above, Q_V is found to be about 7.49 × 10⁻⁸ C cm⁻², while Q_S is about 3.46 × 10⁻⁷ C cm⁻².

For the top gate operation, we also considered the influence of border traps in calculating the top gate dielectric layers’ charges accordingly. We assumed the quantities V_V = Q_V1(t_ox1/ε_ox1) + Q_V2(t_ox2/ε_ox2) and V_S = Q_S1(t_ox1/ε_ox1) + Q_S2(t_ox2/ε_ox2), in which V_V is the bias-dependent voltage shift in V_th and V_S is the bias-independent voltage shift in V_th. Here, V_V and V_S are both contributed to by the top gate structure's HfO₂ (Q_V1 and Q_S1) and SiO₂ (Q_V2 and Q_S2) dielectric layers. When a positive bias is applied, ϕ_ms is 0.041 eV and, for the same reason as in the back gate operation, V_th was assumed to be 8 V; this gives a total voltage offset contribution V_total of 6.591 V in the HfO₂–SiO₂ layer. Meanwhile, in the negative bias condition, ϕ_ms is 0.159 eV while the measured V_th is −4.8 V (Fig. 2(e)), which gives a V_total of −3.697 V in the HfO₂–SiO₂ layer. Using the equations below:

By solving the simultaneous equations above, we get V_V at 5.144 V and V_S equal to −1.447 V.

At no bias condition, bias-dependent Q_V and V_V are both equal to zero. Hence, the theoretical prediction implies that, for the proposed device in such conditions, the induced oxide charges at the top gate dielectric layers is negative (Q_SS′ = Q_S) since V_S is a negative sign; while the induced oxide charges at the back gate dielectric layer are positive (Q_SS′ = Q_S). Thus, the theory supports the mechanism that was discussed earlier (Fig. 3(c) and (d)). It is also important to note that, although the results from previous studies prove that HfO₂ as the capping layer would induce positive oxide charges,^40–42 the combination of HfO₂ and plasma SiO₂ still has a net negative charge. We could then infer that the negative induced charges in the plasma SiO₂ layer are much greater in magnitude than the positive induced charges in HfO₂. Based on the above discussion, both n-type and p-type characteristics appeared in a single device are manifestly illustrated. Accordingly, we can alternatively obtain them by operating in either the back gate or top gate through the control of the charges in which the V_th can be adjusted.

Meanwhile, from hereon we will demonstrate what the proposed device can offer for logic circuit implementations such as a CMOS inverter. In order to show our device for CMOS inverter applications, we added a separate back gate structure in another chip, which is the same with the back gate structure of the proposed device, to assist in the completion. This is necessary since our dual gate device does not have an isolation design between its two gates, which results in mixing of bias signals if both gate operations are performed at the same time in the same device. The corresponding CMOS inverter using both the top gate and the back gate structures is built as shown in Fig. 4(a). The CMOS inverter's voltage transfer characteristic (VTC) as a function of drain voltage V_DD (Fig. 4(b)) clearly shows that the device guarantees either a HIGH or a LOW output voltage in the negative and positive input voltage range, respectively, provided that a given threshold value is exceeded. Moreover, as expected, the I_d–V_g characteristics of both the top gate and the back gate structure at V_d = 1.1 V exhibit p-type and n-type characteristics, respectively (Fig. 4(c)). Another set of results for the same setup is presented in Fig. S7 (ESI†). With these results, we can say that, given effective isolation between its two gates, the device has the potential to operate both as a PMOS and an NMOS that could help in cutting down the number of transistors in the digital circuit.

Fig. 4 Electrical characterization of MoS₂ CMOS inverter device. (a) The schematic diagram showing the measurement setup using both top gate and back gate MoS₂ devices that forms a CMOS inverter. (b) The voltage transfer characteristics of the CMOS inverter as a function of V_DD. (c) The corresponding I_d–V_g characteristic of the top gate and the back gate structure at V_d = 1.1 V.

We now analyze the effect of applying a gate voltage pulse at various durations (T_GS) to the electrical characteristics of the proposed device. The I_d–V_g characteristics of its top gate structure as a function of T_GS is shown in Fig. 5(a) with the corresponding V_th values shown in Table 1. Also, the V_thversus T_GS graph of the device is presented in Fig. 5(b). Here, it is observed that when T_GS lengthens, the drain current is enhanced and V_th increases. These are attributed to the long-lifetime deep electrons trapped at the MoS₂/dielectric interface, formed due to the input pulses, which induced holes in the MoS₂ channel.⁴³ The longer the T_GS, the more electrons get trapped and more holes are induced in the MoS₂ channel. These observations can be quantitatively described using the following current and threshold voltage formula:

I_d = J_n × W = |QμE| × W (10)

V_th = (−|Q_SD′(max)| − Q_SS′)(t_ox/ε_ox) + ϕ_ms − 2ϕ_B (11)

where J_n is the current density, W is the width of the channel, Q is the charge per unit area at the inversion layer, and E is the electric intensity. An increase in the number of holes corresponds to an increase in charge, Q, that leads to an enhancement of the drain current as suggested in eqn (10). Consequently, an increase in the number of electrons trapped at the MoS₂/dielectric interface results in a more negative Q_SS′. Therefore, referring to eqn (11), the V_th will also increase. These are all consistent with our experimental results presented in Fig. 5. The same results from a similar device are also shown in Fig. S8 and Table S1 (ESI†). However, this behaviour is sensitive to the environment or charges, such as static electricity from probing and also it is not obvious in the back gate structure probably because the top gate dielectric layers are thin enough to easily cause changes in their electrical features, in contrast to the back gate dielectric layers. These clearly show the capability of the device to easily adjust its electrical properties, such as its V_th, with an application of an external pulse, which is useful for several applications. For instance, for the CMOS inverters, we have demonstrated that applying a gate pulse on the top gate structure of the device does not only change its V_th but also improves its gain. As mentioned, a change in V_th was observed after applying a −8 V pulse at T_GS = 5 s and V_d = 2.1 V into the top gate shown in Fig. 6(a). This leads to an increase in the gain by 2.4 (Fig. 6(b)). Another similar device shows the same result, which is presented in Fig. S9 (ESI†). In order to get the ideal switching voltage and ensure the inverter fully voltage matched, the dimension for two devices (p-type and n-type) should be the same in the future design.

Fig. 5 Electrical characterization of the double gate MoS₂ field effect transistor at different values of gate voltage pulse duration (T_GS) in a fixed −8 V gate voltage pulse. (a) The I_d–V_g characteristics of the top gate structure as a function of T_GS. (b) The current density and V_th tendency at different values of T_GS where it is observed that the longer the T_GS, the greater the value of the current density and V_th.

Table 1 The corresponding current density at a fixed gate voltage of −6 V and V_th values in a fixed gate voltage pulse of −8 V at various duration times while the gate voltage sweeps from −8 V to 8 V

Pulse duration	Pristine	1s	4s	7s
Current density (A) at −6 V	4.6 × 10^−6	5.6 × 10^−6	7.48 × 10^−6	9.82 × 10^−6
Threshold voltage (Vth)	−3.4 V	−3.05 V	−2.55 V	−1.65

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Fig. 6 Electrical characterization of the MoS₂ CMOS inverter with an adjustable behavior. (a) The voltage transfer characteristics of the inverter at V_d = 2.1 V. The red and blue curves represent the measurements before and after applying a −8 V gate voltage pulse at T_GS = 5 s, respectively. In the right inset is the circuit diagram of the inverter. (b) Gain characteristics of the inverter at V_d = 2.1 V showing a maxima gain value of about from 4 to 6.2, after applying the same gate voltage pulse as in (a).

Conclusions

We have fabricated two kinds of dual gate field effect transistors. Our proposed device showcases the importance of the oxide charges of the dielectric layer to the devices’ electrical characteristics. The result we have found is that the proposed device can alternately exhibit either an n-type or a p-type behaviour. The outcome of our findings suggests that the device can function as a CMOS inverter, and by applying a gate pulse input to the top gate, it demonstrates the attributes of its threshold voltage shift and gain enhancement. Given the effective isolation mechanism, the proposed device can both operate as a PMOS and an NMOS. Moreover, due to the adjustability of its threshold voltage, the number of comparators required to operate for ADC could be reduced, hence essentially lowering the cost of various digital circuit applications. Based on the result of our experiments, it can also serve as a foundation for further research regarding practical applications.

Methods/experimental

Device fabrication

A 30 nm bottom gate SiO₂ dielectric layer was grown by thermal oxidation on a Si substrate, then, on top of it, a 200 nm poly was deposited using Low Pressure Chemical Vapor Deposition (LPCVD) at 600 °C. After plasma dry etching, a 12 nm gate length (L_G) was defined by e-beam lithography. Ar gas was used to carry Sulfur and MoO₃ in a hot furnace to react and deposit MoS₂ onto the surface of a V-shaped Source/Drain substrate at 755 °C by a chemical vapor deposition (CVD) process, which could provide outstanding channel coverage. The key to controlling the MoS₂ on the channel position is to pre-pattern two electrodes with the separation of below 1 micrometer, which could probably provide a lower surface energy for MoS₂ nucleation. After MoS₂ deposition, the first (reference) sample was capped with a 10 nm HfO₂ as the top gate dielectric layer, while the second (proposed) one was covered with a 5 nm SiO₂ by a plasma oxidation process followed by a 10 nm HfO₂ as top gate dielectric materials. Finally, TaN/TiN (High-K Metal Gate) were deposited on top of the dielectric material/s by plasma-enhanced atomic layer deposition (PEALD).

Electrical characterization of devices

All the electrical properties of the fabricated devices were measured using a semiconductor parameter analyzer (Keithley 4200) at room temperature.

Conflicts of interest

The authors declare no competing financial interests.

Acknowledgements

This work were supported by the Ministry of Science and Technology, Taiwan under contract No. MOST 105-2112-M-003-016-MY3, 108-2112-M-003-010-MY3 and 108-2221-E-492-013 and was in part supported by the National Nano Device Laboratories.

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Footnote

† Electronic supplementary information (ESI) available. See DOI: 10.1039/c9nh00275h

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