Open Access Article

This Open Access Article is licensed under a Creative Commons Attribution-Non Commercial 3.0 Unported Licence

Stephan
Menzel
*^{a},
Moritz
von Witzleben
^{b},
Viktor
Havel
^{b} and
Ulrich
Böttger
^{b}
^{a}Forschungszentrum Jülich, Peter Grünberg Institut (PGI-7), 52425 Jülich, Germany. E-mail: st.menzel@fz-juelich.de
^{b}RWTH Aachen University, Institut für Werkstoffe der Elektrotechnik (IWE 2), 52074 Aachen, Germany

Received
6th June 2018
, Accepted 23rd July 2018

First published on 24th August 2018

In contrast to classical charge-based memories, the binary information in redox-based resistive switching devices is decoded by a change of the atomic configuration rather than changing the amount of stored electrons. This offers in principle a higher scaling potential as ions are not prone to tunneling and the information is not lost by tunneling. The switching speed, however, is potentially smaller since the ionic mass is much higher than the electron mass. In this work, the ultimate switching speed limit of redox-based resistive switching devices is discussed. Based on a theoretical analysis of the underlying physical processes, it is derived that the switching speed is limited by the phonon frequency. This limit is identical when considering the acceleration of the underlying processes by local Joule heating or by high electric fields. Electro-thermal simulations show that a small filamentary volume can be heated up in picoseconds. Likewise, the characteristic charging time of a nanocrossbar device can be even below ps. In principle, temperature and voltage can be brought fast enough to the device to reach the ultimate switching limit. In addition, the experimental route and the challenges towards reaching the ultimate switching speed limit are discussed. So far, the experimental switching speed is limited by the measurement setup.

Resistive switching in the low nanosecond regime has been frequently demonstrated.^{5–13} Studies showing switching in the sub-nanosecond regime, however, are rare. In 2011, Torrezan et al. demonstrated that the set and reset switching of Ta_{2}O_{5}-based VCM devices is faster than 120 ps.^{14} Other groups observed set and reset switching times below 500 ps.^{15–17} Switching below 100 ps was shown for a Pt/SiO_{2}-based device^{18} and the record switching speed of <85 ps was achieved for a nitride-based resistive switch.^{19} In all of these studies, however, it was concluded that the switching speed was still limited by the measurement setup.

In this work, the ultimate switching speed limit of redox-based resistive switching devices is discussed. First, a theoretical limit based on the underlying atomic processes under high electric field and temperature will be derived. It will be further discussed to what extent the theoretical limit is influenced by the speed of Joule heating and the speed of charging the device. Besides the theoretical discussion, an experimental route towards reaching the ultimate switching speed limit will be presented.

In order to derive the ultimate switching speed limit from theory, one needs to consider the mathematical rate equations for the three processes. The electro-crystallisation rate is given by

(1) |

(2) |

In eqn (2), c is the concentration of the moving ionic defects, a is mean hopping distance, f is the attempt frequency, ΔW_{hop} is the hopping barrier, and E is the electric field. The electron (charge)-transfer processes determining the speed of the redox processes at the metal/insulator interfaces can be described by the Butler–Volmer equation:

(3) |

Eqn (1)–(3) exhibit a very similar form. All the processes obey an Arrhenius-type law and depend nonlinearly on the applied electric potential (electric field). For high electric fields the sinh term can be approximated with an exponential function, which results in the more generalized relation for the process rate

(4) |

In the following, we will assume that the ion hopping process will determine the ultimate switching speed. As all processes have the same functional form, this assumption does not lead to a loss of generality. From a physical perspective this is a very likely scenario as the ionic defects need to travel some distance (so many hops are involved), but the other processes only involve a single transition at an interface.

Using eqn (2), the relation J_{hop} = cev as well as assuming high electric fields, the drift velocity v results in

(5) |

It is clear that the drift velocity will get maximal if the temperature goes to infinity, that is,

(6) |

With respect to the electric field, the drift velocity will be maximized if the activation energy ΔW is lowered as much as possible by the electric field. From a physical point of view, a barrier lower than zero is not possible. In fact, the formulation in eqn (5) is incorrect for very high electric fields as has been discussed by Genreith-Schriever et al.^{37} The authors considered a sinusoidal potential landscape where the minima give the stable sites for the hopping ionic defects. By application of an external field E the energy landscape eψ(x) is tilted according to

eψ(x) = ΔW_{hop}sin(2πx/a) − eEx. | (7) |

The effective hopping barrier can be simply derived from evaluating the potential difference between a local minima and its neighbouring local maximum. Plotting the energy landscapes for different electric fields clearly shows that the barrier in the direction of the electric field is lowered, whereas it is increased in the reverse direction (see Fig. 1a). For very high electric fields the maxima and minima vanish and eventually the energy landscape approaches eψ(x) = −eEx. Thus, at very high electric fields the acceleration would not become exponential anymore. Fig. 1b shows the difference from calculating the effective hopping barrier as in eqn (5) or by extracting it from the energy landscape in Fig. 1a. The standard approach according to eqn (5) clearly overestimates the barrier lowering for high electric fields and would even predict negative hopping barriers at very high electric fields. Such a negative barrier will appear at even lower electric fields if a field-acceleration factor is used as proposed in ref. 38. First of all, this field-enhancement factor is not consistent with the derivation of the ionic hopping process based on the inner energy landscape.^{37,39–42} The more severe issue is that the exponential law is maintained even for negative barriers, which lead to drift velocities higher than the speed of light at moderate applied fields, e.g. for the parameters used in ref. 43 and 44. This issue is illustrated in Fig. 1c, which shows the drift velocity calculated according to eqn (5) (red solid line) and using the effective hopping barrier extracted from the energy landscape (blue solid line). In the negative barrier regime the calculated drift velocity exceeds the speed of light, i.e. c_{0} ≈ 3 × 10^{8} m s^{−1}. The difference between the two approaches appears at electric fields relevant for scaled redox-based resistive switching memories: typically, a few volts are applied to a few nanometre thick active switching layers. If Joule heating is considered, the difference between the two approaches becomes less dramatic. In this case, the increase in drift velocity is dominated by Joule heating (dashed lines). In addition, the quotient in the exponential function becomes smaller for increasing temperature, which leads to a saturation of the drift velocity at high electric fields.

Fig. 1 (a) Energy landscape calculated using eqn (7) for different applied electric fields. The effective barrier height and the corresponding drift velocity calculated according to Mott–Gurney (blue lines) and Genreith-Schriever (red lines) are shown in (b) and (c), respectively. In (c) the drift velocity is illustrated for assuming only electric field acceleration at T_{0} = 300 K (solid lines) and for including additional Joule heating effects (dashed lines). The temperatures resulting from Joule heating are calculated using T = T_{0} + R_{th}V^{2}/R assuming an ohmic resistance. The parameters used are a = 0.25 nm, ΔW_{hop} = 2 eV, z = 2, f = 1 THz, R = 100 kΩ, and R_{th} = 1.6 MW K^{−1}. The electric field is supposed to drop over 1 nm. |

In ref. 37 it was further demonstrated that the ionic crystal becomes unstable at such high electric fields and all constituting ions start to move. It should be noted that this result is independent of the form of the interatomic energy landscape as the amplitude will be always given by eΔW_{hop}. The consideration of the potential landscape under high electric fields underpins the assumption that the minimum possible effective migration barrier is zero. Hence, the maximum drift velocity under the limit of high electric fields is given by

(8) |

To conclude, independent of the means of process acceleration, the theoretical analysis yields the same maximum drift velocity. Finally, the ultimate switching speed is given by the phonon frequency. For typical values of f ≈ 1–10 THz and considering that a single event is sufficient to result in a resistance change, a lower limit of the switching time of about a picosecond is expected.

To reach this limit, however, the temperature and/or the electric field are supposed to be applied with the same speed. In the following we will discuss if this condition can be fulfilled.

The geometry of the ReRAM cell, which resembles a typical lab-scale device, is shown in Fig. 2a. It consists of a 100 nm thick Si 1 μm^{2} substrate layer, followed by a 100 nm thick SiO_{2} layer and a crossbar structure on top. The top and bottom electrodes are 10 nm thick and 50 nm wide resulting in a junction of 50 × 50 nm^{2}. The two electrodes are separated by a 5 nm-thick switching layer, which is a quite reasonable thickness of a state-of-the-art device. In the middle of the junction a cylindrical filament with a diameter of 10 nm is assumed. This value is in agreement with different spectro-microscopic observations of filaments in resistive switching devices.^{24,35,45,46} To calculate the temperature distribution in this structure, the transient heat equation,

(9) |

−∇J = ∇σ∇φ = 0, | (10) |

σ = σ_{0}/(1 + α_{th}(T − T_{0})). | (11) |

Fig. 2 (a) Simulation geometry and boundary conditions for solving eqn (9) and (10). The active oxide switching region at the junction of the two electrodes has only a thickness of 5 nm. The bottom electrode is embedded in the oxide layer covering the whole substrate. The dashed line indicates the boundary conditions at the bottom of the Si substrate. For all boundaries not labelled, Neumann boundary conditions were chosen, i.e., the heat flux and the normal current flow are set to zero. A typical temperature distribution is shown in colour. The oxide material parameters for this simulation are k_{th} = 1 W m^{−1} K^{−1}, C_{p} = 500 J kg^{−1} K^{−1}, and ρ_{m} = 5000 kg m^{−3}. The simulated characteristic heating times are shown as a function of the heat capacity and the mass density for different thermal conductivities, i.e., in (b) k_{th} = {0.2, 0.4, 0.6, 0.8, 1} W m^{−1} K^{−1} and in (c) k_{th} = {2, 4, 6, 8, 10} W m^{−1} K^{−1}. |

In eqn (11)σ_{0} is the electric conductivity at the reference temperature T_{0} and α_{th} is the first order temperature coefficient. The thermal conductivity of the metal electrodes is connected to the electronic conductivity via the Wiedemann–Franz law

k_{th} = σLT, | (12) |

Pt (top electrode) | Ti (bottom electrode) | Oxide | SiO_{2} |
Si | |
---|---|---|---|---|---|

Electric conductivity σ | 4.76 × 10^{6} S m^{−1} |
1.26 × 10^{6} S m^{−1} |
1 × 10^{3} S m^{−1} (filament) |
1 × 10^{−16} S m^{−1} |
1 × 10^{−6} S m^{−1} |

1 × 10^{−10} S m^{−1} (matrix) |
|||||

Thermal conductivity k_{th} |
Eqn (12) | Eqn (12) | Variable | 1.2 W m^{−1} K^{−1} |
4 W m^{−1} K^{−1} |

Heat capacity C_{p} |
133 J kg^{−1} K^{−1} |
522 J kg^{−1} K^{−1} |
Variable | 1000 J kg^{−1} K^{−1} |
100 J kg^{−1} K^{−1} |

Mass density ρ_{m} |
21450 kg m^{−3} |
4506 kg m^{−3} |
Variable | 2196 kg m^{−3} |
1000 kg m^{−3} |

Temperature coefficient α_{th} |
1.39 × 10^{−3} K^{−1} |
1.13 × 10^{−3} K^{−1} |
— | — | — |

From the simulation results we extracted the time evolution of the maximum temperature in the filament during the applied pulse. Based on this data we determined the characteristic heating time constant τ_{th} that is required to achieve 63% of the static maximum temperature. The final maximum temperature during the transient simulation at t = 50 ns deviates less than 0.25% from the static one, which was determined by an additional static electro-thermal simulation at 2 V. In Fig. 2b and c the characteristic heating time is plotted as a function of the variable parameters C_{p}, ρ_{m}, and k_{th}. Each coloured surface represents the results for the thermal conductivity specified in the figure legends. Two trends can be observed: The thermal time constant increases more or less linearly with the increase of the heat capacity of the oxide material and for increasing mass densities. This result is consistent with the theory of heat conduction, which predicts a linear relation τ_{th} ∝ C_{p}ρ_{m}.^{47} The dependence between the thermal time constant and the thermal conductivity is a lot more complicated. The relation of the thermal conductivity of the oxide material and the surrounding materials will influence the heated volume, which is another crucial factor for determining the thermal time constant.^{47} In our case it seems that the thermal time constant decreases up to a thermal conductivity of 1 W m^{−1} K^{−1} and then increases again. How strong this effect is, however, depends also on the value of the two other parameters. Overall, the characteristic heating time stays well below 120 ps, which means heating will take place on the order of tens of picoseconds or even less. Of course, a sufficiently high temperature is required to accelerate the processes driving the resistive switching. The extra thermal time constant, however, is independent of the applied voltage. So, to achieve a high temperature, the applied voltage can be increased leading to higher temperatures during the heating phase. This is of most importance for oxides with a high thermal conductivity. In our simulations, the steady state temperature is lowest for these oxides.

Joule heating is based on the scattering of electrons at phonons. Only by these events can the electron and the phonon temperature be balanced. To reach the thermal equilibrium a couple of collisions between the energy carriers is required, which should result in an equilibration time of the order of the phonon frequency.^{48} Therefore, the ultimate switching speed limit and the limit of Joule heating are in the same range. Joule heating in the low picosecond range has been experimentally demonstrated in photoconductive switch electrodes.^{49} The latter result supports the claim of sufficiently fast Joule heating in order to reach the ultimate switching speed limit.

(13) |

(14) |

R_{dev} = t_{ox}/(σ_{fil}A) = t_{ox}/(σ_{fil}πr^{2}). | (15) |

In eqn (13) it is assumed that the length of the top/bottom electrode (TE/BE) is ten times the width of the electrode. The values for the conductivities are given in Table 1 assuming T = 300 K.

By solving the differential equation describing the equivalent circuit diagram in Fig. 3a, a time-dependent expression for the device voltage results:

(16) |

The characteristic RC-time τ of this circuit is

(17) |

Under the assumption R_{dev} ≫ R_{el}, eqn (17) simplifies to τ = R_{el}C_{dev}. This means that the characteristic time constant is not limited by the filament resistance itself but rather by the electrode resistance in series.

Fig. 3c shows the calculated device capacitance and characteristic time constant in dependence of the line width w. As shown in eqn (14), R_{el} does not depend on w and therefore only C_{dev} depends on w. Consequently, τ and C_{dev} have the same dependence on w. As expected, larger dimensions lead to higher device capacitances and, therefore, to longer charging times. Both the device capacitance and the characteristic time constant depend linearly on the dielectric constant of the active material. This is also illustrated in Fig. 3c. For very small structures, theoretical charging times of less than 1 ps can be achieved.

Based on these analytical analyses we can draw the following conclusion. For a scaled crossbar device, the characteristic time constant is small enough to enable the reaching of the intrinsic switching speed limit. To this end, the voltage needs to be brought to the device without any delay due to the measurement setup. It is clear that any capacitance in parallel to the device capacitance or any inductance in series would lead to an increase of the characteristic time constant. An additional problem arises in the sub-nanosecond regime. In this regime, high frequency effects need to be taken into account due to the wavelength being comparable to the dimension of the physical circuits.

Two specific experimental challenges have to be faced. Firstly, the applied pulses to the device need very short rise and fall times and must have a relatively high amplitude (>1 V), too. Commercial solutions that are able to generate such short pulses usually have amplitudes below 1 V and are only available as pattern generators with relatively high repetition rates. For probing the switching event, however, this is not favourable. Torrezan et al. solved this issue by an experimental setup that includes a commercial pattern generator, an additional amplifier and a switch that separates one pulse from the generated pattern.^{14} The fastest switching time of a ReRAM device has been measured with this setup and amounts to 85 ps.^{19} The second challenge is to design the experiment in a way that the generated signal is preserved until it reaches the ReRAM device. Therefore, every component in the setup has to be chosen carefully and requires a high bandwidth. To provide proper impedance matching at the contact between the sample and the high frequency probes, coplanar waveguides are usually used, in which the ReRAM device is embedded (see Fig. 4). It consists of two ground conductors and the middle signal conductor. Its characteristic impedance can be designed by the dimensions of the line width and the spacing. Usually it is set to 50 Ω as this is the characteristic impedance of all other components in the setup. To provide ideal signal preservation, this transmission line needs to be terminated by 50 Ω in order to minimize effects of parasitic capacitances and inductances. The resistance of a ReRAM device, however, is usually much higher and therefore those capacitive effects still have to be considered. To illustrate this measurement technique, an exemplary measurement is provided in the following.

The setup used in this paper is similar to the one presented by Torrezan et al.^{14} The device (Pt/Ta_{2}O_{5}/Ta) is embedded in a coplanar waveguide structure with a characteristic impedance of 50 Ω. The overlap of top and bottom electrodes amounts to 20 × 30 μm^{2}. As explained above, this results in a significant capacitance of the ReRAM device and, therefore, in long charging times. An optical microscope picture of this structure is shown in Fig. 4a and the cross-sections perpendicular and along the middle electrode are depicted in Fig. 4b. Additional information about the manufacturing can be found in the figure caption.

An exemplary measurement result is shown in Fig. 5.^{17} Before the application of the pulse the device was programmed into the HRS of about 1 kΩ. Then, a short pulse with an amplitude of −10.8 V was applied and the current was measured with a real-time oscilloscope. The measured current is shown in Fig. 5a and consists in parts of a capacitive current and the current through the device. The full width at half maximum (FWHM) of the pulse is about 350 ps. Subsequently, an I–V sweep was carried out (see Fig. 5b). It started in a low resistive state and, thereby, proves that the ReRAM device was successfully set to the LRS during the application of the 350 ps pulse. If longer pulses with smaller amplitude are applied, resolving the switching event at a nanosecond time scale becomes possible. Fig. 5c shows an example of a 10 ns pulse with an amplitude of −1.8 V. After a significant capacitive current at the beginning of the pulse, the device switched to the LRS. In this example, the switching event occurred after about 5 ns and can be seen in a second current increase. A typical set event would be a quite abrupt switching event (at least if the current in the HRS is not too high). Here, the parasitic capacitances mask the intrinsic device behaviour. To extract more information from the current transients in the sub-nanosecond regime, the parasitic capacitances need to be lowered. In addition, the charging of the device limits the switching speed. In the experiment, the slow charging can be overcompensated by simply applying voltage pulses with higher magnitude than actually required. In the end, the maximum voltage that can be supplied by the pulse generator limits this approach and thus the switching speed.

Fig. 5 Selected measurements from ref. 17. (a) The current response of an electrical voltage pulse with an amplitude of −10.8 V. Its FWHM amounts to 350 ps. The subsequent I–V sweep is shown in (b). As it starts in the LRS, the ReRAM device must have set during the application of the 350 ps pulse. In (c) the current response of a 10 ns voltage pulse with an amplitude of −1.8 V is shown. It is possible to resolve the set event after about 5 ns. |

(18) |

The constant K will include the distance the ions have to travel (cf.ref. 21), but also the ion concentration c (cf.eqn (2)). The local temperature depends on the dissipated electrical power P_{el} and is approximated by

T = T_{0} + R_{th}P_{el} = T_{0} + R_{th}I(V)V. | (19) |

In eqn (19), T_{0} is the ambient temperature and R_{th} is the effective thermal resistance of the specific device configuration. It includes the heat dissipation via the electrodes and the oxide matrix as well as the geometry of the heated volume.^{50} Based on eqn (18) and (19), design rules for developing ultrafast ReRAMs can be deduced already. To evaluate the voltage–time dilemma, the figure of merit NL is introduced, according to

(20) |

This figure of merit describes the ratio between the switching time at a read voltage V_{r} and the switching time at the write voltage V_{wr}. It is straightforward to define likewise the local temperatures T_{r} and T_{wr} and the active electric fields E_{r} and E_{wr} at the read and write voltage, respectively.

First, let us consider a ReRAM device, the operation of which is only accelerated by the electric field without any Joule heating. This condition applies to ECM cells due to their low operation currents and to area-dependent switching VCM systems. In the latter case, the current density is too low to induce any significant Joule heating. ECM devices show a filamentary switching operation, but the switching currents are typically quite low and the electrode materials involved (Ag or Cu) are excellent heat conductors, effectively dissipating the heat.^{51} To achieve fast switching in these devices, the ionic mobility at room temperature should be as high as possible. Analysing eqn (18) gives two viable routes. The more obvious one is to reduce the thickness of the oxide layer. In this way, the ions have to move a shorter distance, thus reducing the constant K. Even more important is the fact that the electric field E will increase, which gives rise to an exponential decrease of the switching time. Another advantage of reducing the oxide thickness is the potential reduction of the switching energy, as lower voltages need to be applied to achieve the same switching speed. Higher electric fields can also be generated by fabrication. It is clear that the local electric field is enhanced at sharp edges.^{52} Deliberately introducing such sharply-edged structures will thus enable faster switching devices. The reduction of the oxide thickness is, however, limited. Below 2 nm significant electron tunnelling current from one electrode to the other should set in, which reduces the resistance ratio R_{HRS}/R_{LRS}. Further, increasing the electric field will also enhance the switching speed at read voltages. The figure of merit NL will stay more or less constant if the oxide thickness is reduced. So, there is a trade-off between fast switching speed and device retention.

The second option to accelerate the switching speed is to increase the ionic current density driving the switching process by increasing the ion concentration (compare the discussion of the switching kinetics of ECM devices in ref. 20). For ECM devices, it has been shown that the choice of the counter electrode material effectively influences the speed of the redox reactions at the active metal/insulator-interface, and thus the injected amount of the active ionic species.^{33,53,54} In addition, mechanical stress might influence the ionic mobility to some extent. Again, the increased ionic mobility will come with the expense of a faster switching at the read voltage. As the ionic mobility will influence mainly K, the figure of merit NL will keep constant. Again, there is a trade-off between fast switching speed and data retention. A way out of this dilemma would be if read and write operations are limited by different physical processes. Thus, the switching speed of read and write operations can be tuned separately. For different ECM devices it has been shown that the switching speed is determined by a nucleation reaction or electron-transfer reactions at lower voltage, but by the ionic drift at higher voltages.^{20,27,34} Redox reactions at the metal/oxide interfaces also play a role in VCM devices,^{55–57} but up to now it is not clear how they influence the switching speed in different voltage regimes.

For filamentary VCM systems, it was shown that local Joule heating will finally determine the switching speed at write voltages and is the origin of the nonlinear switching kinetics.^{20–22} Higher local temperatures will lead to faster switching speed. According to eqn (19), the value of the effective thermal resistance is the design parameter of choice. To increase this parameter, the device design should be optimized with respect to its thermal properties. First of all, an oxide with a low thermal conductivity could be chosen. This will increase the heating efficiency of the device and reduce the lateral heat loss via the oxide layer. In addition, a lateral heat barrier could be introduced. A material with a lower thermal conductivity than the switching oxide, surrounding the active switching volume in a kind of via structure, will lead to a lateral heat confinement. Additional heating layers could be introduced into the device stack. These layers should exhibit a low thermal conductivity, but a high electronic conductivity to avoid parasitic voltage drops across these layers. One candidate material would be amorphous carbon (a-C), which has been used to optimize PCM devices. Another option is to use a bilayer structure consisting of the active switching material and a well conducting sub-stoichiometric oxide layer. If the conductivity is not too high, the heat conduction of these sub-stoichiometric oxide layers will still be governed by phonons and a low thermal conductivity results. The increased effective thermal resistance will also influence the heating at read voltages, but less effectively. The main reason is that the dissipated electric power depends nonlinearly on the applied voltage. The nonlinearity of the I–V curve can even be exploited for optimization of NL. A very high nonlinearity will lead to an increased nonlinearity of the switching kinetics.^{20} Please note that a selector in series to the resistive switching cell will result in a similar effect. In an optimal case, there is no temperature increase at the read voltage, but due to an optimized thermal device design a high temperature is obtained at the write voltage.

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