Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications

Abstract

In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure. Optimization of the device is done for low power applications. Heterojunction engineering is done to optimize the position of the Si:SiGe junction. Subsequently, band gap engineering is incorporated using variations in doping, gate work function, the mole fraction of SiGe and the dielectric constant. Comparison of the optimized, heterostructured silicon channel using numerical simulations indicates that I_ON increases from 0.12 to 15 μA μm⁻¹, I_ON/I_OFF increases from 4 × 10⁶ to 3 × 10⁹, and the subthreshold slope decreases from 80 to 43 mV dec⁻¹ for a 22 nm channel with a supply voltage of 0.7 V.

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I. Introduction

The presence of two junctions in a metal oxide semiconductor field effect transistor (MOSFET) causes size constraint and so constrains its use in future applications. New perspectives towards Lilienfeld’s first transistor architecture¹ resulted in the successful fabrication of a device which does not have any metallurgical junctions thus solving the problem of constraint in the geometry.^2–8 Junctionless FETs (JLFETs) could be used in applications such as SRAM, DRAM and flash memory devices.^9–11 However, the OFF state current is significant in JLFETs with a less significant improvement in the subthreshold swing, which prevents their use in vast applications. On the contrary, Tunnel Field Effect Transistors (TFETs) are excellent for low power applications with very low leakage and a low subthreshold slope.^12,13 However, their low I_ON prevented further high speed applications. There are various alternatives like germanium channels,¹⁴ III–V material channels¹⁵ and strained silicon channels. However, the OFF state drain side tunnelling is significant, causing a low current and ON–OFF current ratio in low band gap germanium, III–V materials have dielectric related issues and strained silicon has fabrication concerns.

Recently, Junctionless Tunnel Field Effect Transistors (JLTFETs) have shown good ON state currents and low subthreshold slopes with the combined benefits of JLFETs, which give a high I_ON, and TFETs, which give a low subthreshold slope.^16–20 In this paper, we further improved the characteristics with the use of a Si:SiGe heterojunction for the Low Standby Power technology (LSTP) standards²¹ of the International Technology Roadmap for Semiconductors (ITRS) with ease of fabrication. High band gap (1.11 eV) Si is placed in the drain side which generates weaker tunnelling in the OFF state, while low band gap (0.67 eV) Ge strengthens band-to-band tunnelling in the ON state. Moreover, a Si and SiGe heterojunction is widely accepted and it has one of the most workable processes in heterostructures. We performed heterojunction engineering to find the optimized position of the heterojunction. Following this, the characteristics are analysed with respect to variations in doping, work function, the mole fraction of Si_1−xGe_x and the dielectric constant. Drastic improvements are found with the optimized heterostructure compared with a Si-JLTFET. Finally, parasitic capacitances and the unity gain frequency of the device are extracted.

II. Device and simulation conditions

A. Device structure

A Hetero-Junctionless Tunnel Field Effect Transistor (H-JLTFET) does not contain any doping junctions as the channel is uniformly n-type doped. Therefore, it is a potential solution for the problem of random dopant fluctuations. The H-JLTFET is structured using a dual n⁺ polysilicon control gate and a dual p⁺ polysilicon auxiliary gate at the source side. The work function difference between the control gate and the channel causes an intrinsic region using the charge plasma concept, while the p⁺ region is caused by the auxiliary gate and the channel work function difference, resulting in the creation of p⁺:i:n⁺ regions. H-JLTFETs work on band-to-band tunnelling to implement a higher I_ON and device with a lower subthreshold slope. Steeper energy bands have to be created with propinquity of bands in the tunnelling region with higher band overlap. Use of a heterojunction of Si at the drain side and SiGe at the source side satisfies the above conditions. The structure of the Si:SiGe H-JLTFET is shown in Fig. 1 with a heterojunction position, x_j, at 34 nm. The electron and hole concentration profile of the Si:SiGe H-JLTFET is depicted in Fig. 2 as a function of distance along the x-direction in the ON state. The intrinsic region band energy shifts downward by applying sufficient positive gate voltage. This leads to p⁺:n⁺:n⁺ regions from the p⁺:i:n⁺ regions and hence makes sufficient conditions for tunnelling. The device works on a flat band when the device is in the ON state causing almost zero resistance, while the device is depleted of carriers in the OFF state, giving no current. The OFF state carrier concentration profile of the proposed structure is shown in Fig. 3. Process attempts at the Si:Si_1−xGe_x interface resulted in significant progress and indicated it as the most suited potential candidate in heteroengineering.^22–24 A Si_1−xGe_x source layer could be smoothly fabricated for x = 0.15 to x = 0.30. Higher mole fractions of Ge may lead to defect formation at the channel interface. Also, vertical heterostructures could be a viable solution for the fabrication of this device as vertical structures have resulted in the successful fabrication of many devices.^23–29 We have used HfO₂ as a gate dielectric. It could be fabricated using atomic layer deposition (ALD), and through ALD, surface oxides are largely eliminated.

Fig. 1 The structure of a Si:SiGe Hetero-Junctionless Tunnel Field Effect Transistor (H-JLTFET) with a heterojunction position, x_j, at 34 nm.

Fig. 2 The electron and hole concentration profile of the Si:SiGe H-JLTFET as a function of distance along the x-direction in the ON state (V_DS = 0.7 V, V_GS = 0.7 V) with preset parameters.

Fig. 3 The electron and hole concentration profile of the Si:SiGe H-JLTFET as a function of distance along the x-direction in the OFF state (V_DS = 0.7 V, V_GS = 0 V) with preset parameters.

B. Simulation setup

Simulations are done in a SILVACO ATLAS 2D Device Simulator, using the band-to-band tunnelling (BBT)³⁰ model for including the effect of tunnelling. In the BBT model, we used non-local models which are independent of an electric field at individual mesh points and the tunnelling current depends on the band structure along the cross section taken through the device.³¹ As the channel is heavily doped, the Band Gap Narrowing (BGN) model has been added.³¹ Other models include Shockley–Read–Hall (SRH) to model traps or defects,^31,32 and Schenk’s Trap Assisted Tunnelling (TAT) model to account for electron tunnelling through the band gap via trap states³². The Quantum Confinement (QC) model for the interface trap effect and quantum confinement effect^31,33 is also considered. Heavy doping and a thin oxide are enough for the creation of a potential well in the channel during inversion and therefore quantum confinement must be incorporated. The preset parameters used for device simulation of the H-JLTFET as in Fig. 1 are tabulated in Table 1.

Table 1 Preset parameters for device simulation of the H-JLTFET

Parameter	Value
Source/channel/drain doping (ND) (uniformly doped)	1 × 10^19 cm^−3 (unless otherwise specified)
Effective oxide thickness (TOX)	2 nm
Control gate work function (ΦG)	4.2 eV (unless otherwise specified)
Auxiliary gate work function (ΦS)	5.3 eV
Gate length (Lg)	22 nm
Heterojunction position (xj)	34 nm (unless otherwise specified)
Channel thickness (Tch)	5 nm
Supply voltage (VDD)	0.7 V
Permittivity of dielectric material (εd)	25 (unless otherwise specified)
Spacers (low-k)	3.9
Mole fraction of Si1−xGex (x)	0.5 (unless otherwise specified)

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III. Optimization of the H-JLTFET

Fig. 4 plots the I_ON and I_OFF with respect to the heterojunction position, x_j. As the supply voltage is very low, the ON and some part of the OFF state tunnelling occurs in the source region, contrary to TFETs where the OFF state tunnelling mainly occurs in the drain side. Therefore, variation in x_j across the channel depicts a smaller variation in the ON and OFF currents until the source region is covered by SiGe. Similarly, the values of and subthreshold slope are finer with the presence of SiGe at the source side, whereas they drop drastically in the presence of a larger band gap silicon material at the source side. This is illustrated in Fig. 5. Two structures can be preferred from the view of fabrication: first, Si:SiGe with a heterojunction position, x_j, at 34 nm (i.e. in situ SiGe source). There is no interaction of SiGe with the gate dielectric and the lesser region contains germanium which brings costs down. The second is a homogeneous Si_1−xGe_x JLTFET structure which does not have any heterojunctions. It works with the problem of gate insulator fabrication. Moreover, the number of steps and the power budget in the process could be reduced because of the absence of heterojunctions. However, a Si_1−xGe_x H-JLTFET exhibits less improvement in device performance when the structural parameters are optimized. Furthermore, heterostructured Si:SiGe has higher suppressed tunnelling between the drain and channel than a homogeneous SiGe device which brings very low leakage.

Fig. 4 ON and OFF state currents with respect to the position of the heterojunction, x_j, of a Si:SiGe H-JLTFET with V_DD = 0.7 V, Φ_G = 4.2 eV, ε_d = 25, x = 0.5 and N_D = 10¹⁹ cm⁻³.

Fig. 5 and subthreshold slope with respect to the position of the heterojunction, x_j, of a Si:SiGe H-JLTFET with V_DD = 0.7 V, Φ_G = 4.2 eV, ε_d = 25, x = 0.5 and N_D = 10¹⁹ cm⁻³.

Variation in the concentration of dopant causes a change in the work function of a semiconductor and hence the energy band diagram of the device. The highest is obtained at a channel doping, N_D, of 10¹⁵ cm⁻³ as shown in Fig. 6. Interestingly, with a low process budget and low temperature process, the intrinsic channel results in the highest ON and OFF state current ratio. However, at a very high doping of 10¹⁹ cm⁻³, energy band overlap increases causing a higher I_ON and I_OFF and subsequently, a lower . Reduction in the work function of the gate brings more electrons near the surface. This results in more band overlap bringing a higher I_ON and I_OFF, and a gate work function, Φ_G, of 4.2 eV yields the highest . The ON current and with respect to the work function of the control gate material is shown in Fig. 7.

Fig. 6 ON current and ON and OFF current ratio versus channel doping with V_DD = 0.7 V, Φ_G = 4.2 eV, ε_d = 25, x_j = 34 nm and x = 0.5 for a Si:SiGe H-JLTFET.

Fig. 7 ON current and ON and OFF current ratio versus work function of the control gate material with V_DD = 0.7 V, N_D = 10¹⁵ cm⁻³, ε_d = 25, x_j = 34 nm and x = 0.5 for a Si:SiGe H-JLTFET.

One can increase current through increasing the overlap region of the bands. This can be done through a higher mole fraction, x, of germanium in the source side of Si_1−xGe_x which produces a lower band gap near the source side and gives a higher drain current as shown in Fig. 8. However, fabrication of a transistor with a mole fraction, x, higher than 0.5 carries the issue of strain.

Fig. 8 Drain current versus gate voltage for a varying mole fraction, x, of Si_1−xGe_x with V_DD = 0.7 V, N_D = 10¹⁵ cm⁻³, Φ_G = 4.2 eV, ε_d = 25 and x_j = 34 nm for a Si:SiGe H-JLTFET.

Substantial research has been done on dielectric materials for optimizing current.^34,35 Drain current is measured for four dielectrics, namely SiO₂(3.9), Si₃N₄(7), HfO₂(25) and TiO₂(80),^36,37 as shown in Fig. 9. Increasing permittivity increases the ON state current and decreases the OFF state current as gate control proliferates because of the permittivity of the dielectric. Consequently, rises along with a significant improvement in the subthreshold slope. I_ON and for TiO₂ are 125 μA μm⁻¹ and 9 × 10⁹ respectively. There is a more than 5 × 10⁴ times improvement in I_ON for TiO₂ with respect to SiO₂.

Fig. 9 Drain current versus gate voltage for varying permittivity with V_DD = 0.7 V, N_D = 10¹⁵ cm⁻³, Φ_G = 4.2 eV, x_j = 34 nm and x = 0.5 for a Si:SiGe H-JLTFET.

IV. Results and discussion

Through variations of various device parameters, we found that Φ_G = 4.2 eV, ε_d = 25, x = 0.5, x_j = 34 nm and N_D = 10¹⁵ cm⁻³ resulted in an optimized device performance. However, a value of x above 0.3 can create a feasibility constraint of the process. Therefore, until x = 0.3, we can get performance improvement along with an insignificant improvement in cost as we have removed doping junctions from the structure. The transfer characteristic of the proposed device is compared with that of a Si JLTFET and Si_0.5Ge_0.5 JLTFET in Fig. 10. Clearly, the Si:SiGe channel has a much better transfer characteristic than Si and SiGe channels for low power applications. The Si JLTFET has lower currents than the SiGe JLTFET due to the reduced band gap of Si_0.5Ge_0.5. The ON state energy band diagram indicates that there is reduced tunnelling near the source for the silicon channel in comparison to the Si:SiGe channel, and thus a lower drain current follows. This is elaborated in Fig. 11. Comparison of the device characteristics is done in Table 2. It is evident from the table that heterostructured and high-k dielectric materials improve the JLTFET performance drastically. The Si:Si_0.5Ge_0.5 H-JLTFET with TiO₂ as a gate dielectric provides the best results with a subthreshold slope as low as 23 mV dec⁻¹. The subthreshold slope is calculated with the following formula:where I_t is taken as 10⁻⁷ A μm⁻¹, V_t is the voltage at the point where the current crosses 10⁻⁷ A μm⁻¹, and V_ref is the voltage at the reference point. Clearly, from Table 2 we can conclude that the H-JLTFET surpasses the benchmark of ITRS’ LSTP for 22 nm technology and supplies a voltage of 0.7 V.

Fig. 10 Variation of drain current with gate voltage at V_DD = 0.7 V, N_D = 10¹⁵ cm⁻³, Φ_G = 4.2 eV, x_j = 34 nm, x = 0.5 and ε_d = 25 for the SiGe JLTFET, Si:SiGe H-JLTFET and Si JLTFET.

Fig. 11 ON state energy band diagram showing reduced tunnelling near the source for the Si JLTFET in comparison to the Si:SiGe H-JLTFET at V_DD = 0.7 V, N_D = 10¹⁵ cm⁻³, Φ_G = 4.2 eV, x_j = 34 nm, x = 0.5 and ε_d = 25.

Table 2 Characteristics of JLTFETS and H-JLTFETS

	Si JLTFET (HfO2, εd = 25)	SiGe JLTFET (HfO2, εd = 25)	Si:Si0.5Ge0.5 H-JLTFET (HfO2, εd = 25)	Si:Si0.5Ge0.5 H-JLTFET (TiO2, εd = 80)
ION (μA μm^−1)	0.12	29.72	15.66	125.27
IOFF (A μm^−1)	2.6 × 10^−14	5.8 × 10^−12	5.1 × 10^−15	1.35 × 10^−14
	4 × 10^6	5 × 10^6	3 × 10^9	9 × 10^9
SS (avg.) (mV dec^−1)	80	59	43	23

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Capacitance between the gate and source (C_GS), gate and drain (C_GD), gate and auxiliary gate (C_GG1), drain and source (C_DS) and drain and auxiliary gate (C_DG1) as a function of gate voltage at a drain voltage of 0.7 V are extracted and plotted in Fig. 12. Here, ‘G1’ represents the auxiliary gate. All the capacitances are extracted for the small signal of 0.01 V and a frequency of 1 MHz. The device approaches a linear region with V_GS; thus C_GD grows while C_GS decreases. Due to the carrier concentration profile as in Fig. 2, C_GD is higher than C_GS. Computation results in a maximum unity gain frequency, f_T, of 4 × 10⁹ at the supply voltage. Unity gain frequency, f_T, is compiled as a function of the gate voltage at V_DS = 0.7 V in Fig. 13.

Fig. 12 Variation of capacitances, C_GD, C_DS, C_GS, C_DG1 and C_GG1, with gate voltage at V_DS = 0.7 V for the Si:SiGe H-JLTFET with ac freq. = 1 MHz, small signal = 0.01 V, N_D = 10¹⁵ cm⁻³, Φ_G = 4.2 eV, x_j = 34 nm, x = 0.5 and ε_d = 25.

Fig. 13 Unity gain frequency, f_T, as a function of the gate voltage at V_DS = 0.7 V for the Si:SiGe H-JLTFET with ac freq. = 1 MHz, small signal = 0.01 V, N_D = 10¹⁵ cm⁻³, Φ_G = 4.2 eV, x_j = 34 nm, x = 0.5 and ε_d = 25.

V. Conclusion

We can conclude that the H-JLTFET exhibits tremendous characteristics for the 22 nm Low Standby Power technology (LSTP) standards of the International Technology Roadmap for Semiconductors (ITRS) with ease of fabrication, as channel doping and the dielectric oxide thickness were kept at 10¹⁵ and 2 nm respectively. For a 22 nm channel, a very low leakage current of ∼10⁻¹⁵ A μm⁻¹ and an ON and OFF state current ratio of the order of 10⁹ at a V_DD of 0.7 V and a dielectric constant of 25 are achieved. Furthermore, the performance improves with a very high-k dielectric, and TiO₂ and the H-JLTFET easily surpass all standards of the LSTP. Comparing this device data with recently developed structures, the H-JLTFET is far ahead in terms of performance. Because of these exceptional characteristics for very small geometries at a low voltage, the H-JLTFET is a promising solution for low power applications.

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