Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor

Abstract

In this paper, the analog performance of a Si double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been studied and improvised using a ternary III–V semiconductor compound, indium aluminium arsenide. The analog performance parameters are extracted using device simulations and also compared with the Si JLTFET. We show that III–V JLTFET delivers much better performance parameters, in comparison to Si JLTFET, which includes transconductance generation efficiency (G_m/I_D), intrinsic gain (G_mR_o) and unity gain frequency (f_T) along with various gate capacitances.

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I. Introduction

The typical Metal Oxide Semiconductor Field Effect Transistor (MOSFET), owing to its structure, is confronted with severe fabrication issues in the sub-20 nm channel regime. This is due to the fact that, while doping, procuring such an acute gradient profile becomes difficult.¹ The complication of fabricating a device retaining p–n junctions was eliminated by the Junctionless Field Effect Transistor (JLFET), the transistors having a uniformly doped channel with no p–n junction in the drain–channel–source path. Along with the simplified process flow, JLFET also offers a better Short Channel Effect (SCE) performance.^2–5 In the past few years, JLFETs have managed to achieve decent analog performance parameters,^6,7 however, the sub-threshold slope (>60 mV per decade) is still inadequate. The Tunnel Field Effect Transistor (TFET) offers a lower sub-threshold slope but again has fabrication issues beyond 32 nm nodes, the reason being the presence of the physical p–i–n junction.^8–11 The assets of JLFET along with TFET were realized in Junctionless Tunnel Field Effect Transistors (JLTFET).¹² JLTFET has a uniformly doped channel as in JLFET; however, the TFET action is enforced using the metal work function. JLTFETs have managed to obtain excellent characteristics (high I_ON, very low I_OFF and a low sub-threshold slope).^13,14

Si JLTFETs deliver decent characteristics; nonetheless, the fixed band gap energy of Si does not offer enough flexibility. On the contrary, ternary III–V semiconductors allow band gap modulation i.e. band gap energy variation with respect to the mole fraction of the elemental compound. InAlAs offers a wide range of band gap energies depending on the Al mole fraction. In this paper, In_1−xAl_xAs is employed as the channel with Al mole fraction of 0.46, which is the optimized value to obtain the best dc parameters such as I_ON of ∼0.2 mA and I_ON/I_OFF ratio of ∼10¹³.

In this work, analog performance parameters for In_0.54Al_0.46As JLTFET, i.e., drain current (I_D), transconductance (G_m), output conductance (G_d), early voltage (V_A), transconductance generation efficiency (G_m/I_D), output resistance (R_o), intrinsic gain (G_mR_o) along with various capacitances particularly, gate to drain capacitance (C_gd), gate to source capacitance (C_gs) and inter-gate capacitance (C_gg1) have been evaluated through device simulations and then compared with that of Si JLTFET.

II. Device structure and operation

A double gate junctionless tunnel field effect transistor is shown in Fig. 1 along with the dimensions. The channel length of the simulated device is 20 nm. The width of the device is 1 μm. The channel region is heavily doped n-type In_0.54Al_0.46As with a doping concentration of 1 × 10¹⁹ cm⁻³. The device under simulations has a gate oxide thickness of 2 nm, source–drain region length of 20 nm, spacer length of 2 nm and the channel thickness of 5 nm. The function of the spacer is to isolate the two gates i.e. control gate (CG) and P-gate (PG). The work functions of CG and PG are chosen so as to convert the region underneath them to an intrinsic and a p-type region respectively. In this work, a constant work function of 5.93 eV and 4.3 eV is used for PG and CG respectively. The work function of 5.93 eV and 4.3 eV corresponds to metal platinum (Pt) and titanium (Ti) respectively.¹⁵ Thereby, a uniform N⁺ region is transformed to N⁺–I–P⁺ (drain–channel–source) without any physical doping. Input voltages are applied to the control gate (CG) only and the P-gate (PG) is held at zero bias for all regions of operation. HfO₂ is used as a high-k dielectric in this work (Table 1).¹⁶

Fig. 1 Schematic representation of a double gate JL-TFET along with the dimensions in 2D. Width of the device is 1 μm.

Table 1 Parameters for device simulation of JLFET

Parameter	Value
Source/channel/drain doping	1 × 10^19 cm^−3
Effective oxide thickness (TOX)	2 nm
Control gate work function	5.93 eV
P-gate work function	4.3 eV
Gate length (Lg)	20 nm
Silicon thickness (Tsi)	5 nm
Supply voltage (VDD)	1 V
Permittivity of gate dielectric (HfO2)	25

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Fig. 2(a) illustrates the energy band diagram of the device in the OFF state (V_DS = 1 V, V_GS = 0 V). It may be noted that, at the source–channel junction, In_0.54Al_0.46As JLTFET provides a higher tunnelling width compared to the Si JLTFET. Since the probability of tunnelling and therefore the tunnelling current is inversely proportional to the tunnelling width, In_0.54Al_0.46As provides a much lower OFF state current. In the ON state (V_DS = 1 V, V_GS = 1 V), the channel energy is lowered owing to the application of 1 V at the control gate, as shown in Fig. 2(b). This causes lowering of the tunnelling barrier at the source–channel junction and the electrons can now tunnel through from the valance band of the source to the conduction band of the channel, which results in a large drain current.

Fig. 2 Energy band diagram of the simulated device with Si and In_0.54Al_0.46As as the channel material in (a) OFF state (b) ON state.

Silvaco Atlas, version 5.15.32.R, a 2D device simulator, is used for performing simulations. The models used include a nonlocal band-to-band tunnelling (BTBT) model which accounts for lateral tunnelling.¹⁷ The BTBT model, based on the electric field, calculates the generation–recombination rate and also foresees the spatial variation of energy bands to account for tunnelling. The Shockley–Read–Hall (SRH) model is included¹⁷ to consider high impurity concentration in the channel. It takes into account the phonon transitions that occur in the presence of traps or defects. In heavily doped devices, shrinkage of the band gap occurs, for which the Band Gap Narrowing (BGN) model is incorporated. The Quantum Confinement (QC) model given by Hansch,^17,18 handles the quantum confinement effect and interface trap effect. Quantum confinement arises due to the formation of a potential well in the channel as a result of heavy doping and thin gate oxide. The Trap Assisted Tunnelling (TAT) model given by Schenk,^17,19 is also included to account for the electrons tunnelling through the band gap via traps.

III. Results and discussion

Fig. 3 depicts the drain current and the transconductance as a function of gate voltage for both In_0.54Al_0.46As and Si as the channel. It is clear that In_0.54Al_0.46As provides a high ON state current (∼0.2 mA) and a negligible OFF state current (∼10⁻¹⁶ A) in comparison to Si. This is due to the fact that In_0.54Al_0.46As has a lower energy band gap compared to Si, which results in lowering of the tunnelling barrier in the ON state. Also, In_0.54Al_0.46As JLTFET provides higher transconductance (0.057 mS) compared to Si JLTFET (0.029 mS) at a gate voltage of 1 V.

Fig. 3 Drain current (I_D) and transconductance (G_m) as a function of gate voltage for In_0.54Al_0.46As and Si JLTFET.

Fig. 4 shows drain conductance as a function of drain voltage for two different gate voltages of 0.2 V and 1 V. The drain conductance obtained for a gate voltage of 0.2 V resembles the conventional curve. However, for higher values of gate voltage, the characteristics deviate from the usual, the reason being that if the gate voltage is high, the drain control decreases for lower values of drain voltages. As a result, with drain voltage, the drain current increases non-linearly, which leads to an initial increase in drain conductance. Also, it is noted that the peak is shifted to the left as the gate voltage is reduced.

Fig. 4 Drain conductance (G_D) as a function of drain voltage for two fixed gate voltages i.e. 0.2 V and 1 V.

Fig. 5 shows early voltage (V_A) and transconductance generation efficiency (G_m/I_D) as a function of gate voltage. The preferred III–V semiconductor provides a higher early voltage compared to Si. At a gate voltage of 0.1 V, In_0.54Al_0.46As gives an early voltage of up to 70 V while it is only 17 V for Si. Transconductance generation efficiency estimates how sound the device is in converting the dc current (I_D) to an ac parameter (G_m) and is strongly related to the analog performance of a device.²⁰ The Si JLTFET, however, provides higher G_m/I_D (∼64 V⁻¹) at a gate voltage of 0.1 V but In_0.54Al_0.46As JLTFET also manages to deliver a reasonable figure of 55 V⁻¹.

Fig. 5 Early voltage (V_A) and transconductance generation efficiency (G_m/I_D) as a function of gate voltage for In_0.54Al_0.46As and Si JLTFET.

Fig. 6 depicts the output resistance and intrinsic gain for varying gate voltage. In_0.54Al_0.46As JLTFET gives a higher output resistance; at a gate voltage of 0.1 V it gives an output resistance of 1.2 × 10¹² ohm whereas Si JLTFET gives 10¹¹ ohm. There is a sharp drop in the output resistance in the case of In_0.54Al_0.46As, the reason being that the output resistance for a given gate voltage is inversely related to the drain current at that voltage. It may be noted in Fig. 3 that, for low gate voltages, In_0.54Al_0.46As shows a stinging increase in drain current, which results in a sharp drop in output resistance in a In_0.54Al_0.46As JLTFET in comparison to the Si JLTFET. So, the chosen III–V material is advantageous as the intrinsic gain is directly related to the output resistance. Fig. 6 also demonstrates an intrinsic gain for both the channel materials as a function of gate voltage. Intrinsic gain of the device is the product of output resistance and the transconductance offered by the device i.e. G_mR_o. In_0.54Al_0.46As JLTFET delivers the maximum intrinsic gain of 84 while Si JLTFET offers its maximum value of 65 at a gate voltage of 0.1 V. It may be noted that In_0.54Al_0.46As JLTFET offers reasonable gain (>20) for a fine range of gate voltage (up to 0.7 V).

Fig. 6 Output resistance (R_o) and intrinsic gain (G_mR_o) as a function of gate voltage for In_0.54Al_0.46As and Si JLTFET.

Fig. 7 shows gate-to-source capacitance as a function of gate voltage. In_0.54Al_0.46As JLTFET provides lower (about 4 times) gate-to-source capacitance than Si JLTFET. Also, the preferred III–V compound offers lower gate-to-drain capacitance in comparison to Si as shown in Fig. 8.

Fig. 7 Gate-to-source capacitance as a function of gate voltage for both the channel materials.

Fig. 8 Gate-to-drain capacitance as a function of gate voltage for both the channel materials.

Fig. 9 shows the inter-gate capacitance i.e. capacitance between control gate and P-gate. Here, In_0.54Al_0.46As exhibits a bit higher capacitance owing to the fact that the charge flow in this case is more critical function of gate voltage, as the region beneath the spacer assists tunnelling and also In_0.54Al_0.46As offers a smaller energy band gap as compared to Si.

Fig. 9 Inter-gate capacitance offered by the two channel materials as a function of gate voltage.

Fig. 10 shows the unity gain frequency (f_T) as a function of gate voltage. In_0.54Al_0.46As delivers about an order of magnitude higher f_T than Si. Unity gain frequency is given by the following expression.

Fig. 10 Unity gain frequency f_T, as a function of gate voltage in linear and log scale for In_0.54Al_0.46As and Si as the channel material.

IV. Conclusion

In this work, the analog performance of a Si DG JLTFET has been estimated and improvised by using a ternary III–V semiconductor compound (In_0.54Al_0.46As) as the channel. The simulated device offers decent analog performance parameters like fine transconductance, high output resistance, high intrinsic gain, low intrinsic capacitances and reasonable unity gain frequency, which makes it a prominent device for analog applications.

References

1. S. Gundapaneni, M. Bajaj, R. K. Pandey, K. V. R. M. Murali, S. Ganguly and A. Kottantharayil, Effect of Band-to-Band Tunneling on Junctionless Transistors, IEEE Trans. Electron Devices, 2012, 59(4), 1023–1029.
2. J. E. Lilienfeld, Method and apparatus for controlling electric current, US Pat. 1 745 175, 22 October 1925.
3. J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy and R. Murphy, Nanowire transistors without junctions, Nat. Nanotechnol., 2010, 5(3), 225–229.
4. H. Lou, L. Zhang, Y. Zhu, X. Lin, S. Yang, J. He and M. Chan, A Junctionless Nanowire Transistor with a Dual-Material Gate, IEEE Trans. Electron Devices, 2012, 59(7), 1829.
5. S. Gundapaneni, S. Ganguly and A. Kottantharayil, Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling, IEEE Electron Device Lett., 2011, 32(3), 261.
6. R. T. Doria, M. A. Pavanello, R. D. Trevisoli, M. de Souza, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti and J.-P. Colinge, Junctionless Multiple-Gate Transistors for Analog Applications, IEEE Trans. Electron Devices, 2011, 58(8), 2511–2519.
7. R. K. Baruah and R. P. Paily, Analog Performance of Bulk Planar Junctionless Transistor (BPJLT), Computing Communication & Networking Technologies (ICCCNT), 2012, Third International Conference,  DOI:10.1109/ICCCNT.2012.6395875.
8. K. Boucart and A. M. Ionescu, Double-Gate Tunnel FET With High-K Gate Dielectric, IEEE Trans. Electron Devices, 2007, 54(7), 1725–1733.
9. K. Boucart and A. M. Ionescu, Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric, Solid-State Electron., 2007, 51(11–12), 1500–1507.
10. H. G. Virani, R. Bhadra Rao Adari and A. Kottantharayil, Dual-k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs, IEEE Trans. Electron Devices, 2010, 57(10), 2410.
11. B. K. Mamilla, R. Mishra, S. Nair and B. Ghosh, A III-V Group Tunnel FETs with Good Switching Characteristics and their Circuit Performance, International Journal of Electronics Communication and Computer Technology, 2011, 1(2), 26.
12. B. Ghosh and M. W. Akram, Junctionless Tunnel Field Effect Transistor, IEEE Electron Device Lett., 2013, 34(5), 584.
13. P. Bal, M. W. Akram, P. Mondal and B. Ghosh, Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET), J. Comput. Electron., 2013, 12, 782.
14. B. Ghosh, P. Bal and P. Mondal, A junctionless tunnel field effect transistor with low subthreshold slope”, J. Comput. Electron., 2013, 12, 428.
15. D. R. Lide, CRC Handbook on Chemistry and Physics, 89th edn, Taylor & Francis, London, UK, 2008, pp. 12–114.
16. J. Robertson, High dielectric constant oxides, Eur. Phys. J.: Appl. Phys., 2004, 28(3), 265–291.
17. Documentation available at http://www.silvaco.com.
18. W. Hansch, Th. Vogelsang, R. Kirchner and M. Orlowski, Carrier Transport Near the Si/SiO₂ Interface of a MOSFET, Solid-State Electron., 1989, 32(10), 839–849.
19. A. Schenk, A model for the field and temperature dependence of SRH lifetimes in Silicon, Solid-State Electron., 1992, 35(11), 1585–1596.
20. F. Silveira, D. Flandre and P. G. A. Jespers, A G_m/I_D based Methodology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of a Silicon-on-Insulator micropower OTA, IEEE J. Solid-State Circuits, 1996, 31(9), 1314–1319.

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