Low-frequency noise in multilayer MoS₂ field-effect transistors: the effect of high-k passivation

Abstract

Diagnosing of the interface quality and the interactions between insulators and semiconductors is significant to achieve the high performance of nanodevices. Herein, low-frequency noise (LFN) in mechanically exfoliated multilayer molybdenum disulfide (MoS₂) (∼11.3 nm-thick) field-effect transistors with back-gate control was characterized with and without an Al₂O₃ high-k passivation layer. The carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface nicely described the noise behavior in the strong accumulation regime both with and without the Al₂O₃ passivation layer. The interface trap density at the MoS₂–SiO₂ interface was extracted from the LFN analysis, and estimated to be N_it ∼ 10¹⁰ eV⁻¹ cm⁻² without and with the passivation layer. This suggested that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model implying the bulk conduction was found to describe the drain current fluctuations in the subthreshold regime, which is rarely observed in other nanodevices, attributed to those extremely thin channel sizes. In the case of the thick-MoS₂ (∼40 nm-thick) without the passivation, the HMF model was clearly observed all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS₂. With the Al₂O₃ passivation layer, the change in the noise behavior was explained from the point of formation of the additional top channel in the MoS₂ because of the fixed charges in the Al₂O₃. The interface trap density from the additional CNF model was N_it = 1.8 × 10¹² eV⁻¹ cm⁻² at the MoS₂–Al₂O₃ interface.

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Introduction

Two-dimensional (2-D) nanostructures have attracted considerable interest because of their unique properties and the easiness in fabricating the complex structures compared with three- or one-dimensional nanostructures. Among those 2-D nanostructures, graphene has drawn particular interest in recent years owing to extremely large charge carrier mobility.¹ However, because of the absence of a band gap, device operation suitable for logic applications is not straightforward.^2–4 Layered transition-metal dichalcogenides (TMDs) such as MoS₂ have finite band gaps, and so are more appropriate for logic devices.⁵

An electron mobility of 217 cm² V⁻¹ s⁻¹ has been reported in monolayer MoS₂ passivated with a high-k dielectric.⁶ This is a substantial improvement over the value of 3 cm² V⁻¹ s⁻¹ that was reported previously.⁷ The large mobility of monolayer MoS₂ may be an overestimate due to the wrong choice of the gate capacitance used in the dual-gate measurement system.^8,9 Significant mobility improvement due to the effect of the high-k dielectrics on the MoS₂ may not be as large as the initial report suggested; however, further works are required to explain the effects of the high-k dielectric on the charge carrier mobility, as well as the device characteristics of MoS₂ transistors.⁹

Multilayer MoS₂ has a comparable band gap (E_g = 1.2 eV) to that of silicon (where E_g = 1.1 eV), and a lower band gap than monolayer MoS₂ (where E_g = 1.8 eV). There is therefore greater potential for multilayer MoS₂ applications in wide spectral response photodetectors compared with monolayer MoS₂.¹⁰ In addition, it has a relatively high electron mobility compared with either amorphous Si, low-temperature polycrystalline Si, or amorphous metal oxide semiconductors in view of thin-film transistors.^10,11 The film thickness can be controlled, and very thin films, including monolayers, can be obtained from the top-down processes,^12–14 which are more flexible for customizing the nanodevices.

High-k materials and semiconductors are inseparable in the nanodevice applications, particularly field-effect transistors (FETs). The high-k materials must be used for the gate dielectrics to achieve the ultimate field effect and the lower gate leakage current. Due to the fixed charges and the interface states from the high-k dielectrics, it is difficult to use the high-k for the gate insulators in the FETs. It is important not only to reduce those flaws, but also to diagnose them exactly. However, there are few works for diagnosing the interactions between the high-k and the MoS₂.^11,15 Therefore, in order to apply the multilayer MoS₂ to the nanodevices, the effects of a high-k dielectric to the MoS₂ should be understood.

The low-frequency noise (LFN) characteristics of FETs have been used to provide information relating to the interface quality between the Si channel and the gate dielectric in Si metal–oxide–semiconductor field-effect transistors (MOSFETs).^16–19 As the channel length of MOSFETs continues to be reduced by the scaling of device dimensions, fluctuations in the drain current become increasingly significant, and so the importance of LFN analysis has also grown. However, very little LFN analysis of MoS₂ FETs has been carried out to date.

In this article, passivation of MoS₂ using high-k dielectrics such as Al₂O₃ and the effects on the electrical properties of multilayer MoS₂ were characterized using LFN measurements.

Experimental

Bulk MoS₂ crystals (SPI Supplies, USA) were mechanically exfoliated directly onto a p⁺⁺ Si substrate, which was thermally grown using a 300 nm-thick SiO₂ layer. Fig. 1(a) (left image) shows the as-exfoliated multilayer MoS₂ on the 300 nm-thick SiO₂ substrate. We can estimate the thickness of MoS₂ from the optical image.^20,21 The channel length (0.28 μm) and width (2.3 μm) were defined using electron beam lithography. A 10 nm-thick Ti adhesion layer followed by a 100 nm-thick Au layer was deposited using electron beam evaporation, and electric contacts were defined using a lift-off process with acetone. Fig. 1(a) (right image) shows an optical image after metallization. In Fig. 1(b), atomic force microscopy (AFM) measurements confirmed that the thickness of the multilayer MoS₂ was 11.3 nm. MoS₂ is a multilayered structure with an interlayer distance of ∼0.65 nm, which is consistent with the images shown in Fig. 1(c). We can therefore determine the number of layers in the structure: an 11.3 nm-thick MoS₂ film contains approximately 17 layers. A schematic of the multilayer MoS₂ FET is shown in Fig. 1(d) before depositing the Al₂O₃ passivation layer.

Fig. 1 (a) Optical images before and after the formation of source/drain metal contacts on the multilayer MoS₂. The scale bar is 5 μm long. (b) AFM images of the multilayer MoS₂ with the source/drain metal contacts. The inset shows that the thickness of MoS₂ layer was approximately 11.3 nm. The scale bar is 2 μm long. (c) Schematic image of multilayer MoS₂. The gap between monolayers is 0.65 nm. (d) Schematic image of a back-gated multilayer MoS₂ FET. The source/drain contacts are Ti/Au. The back-gate is p⁺⁺ Si and the gate dielectric is SiO₂.

The electrical properties of the FET were characterized using a Keithley 4200 semiconductor analyzer. LFN measurements were carried out using our custom LFN characterization system,²² which was configured using a data acquisition (DAQ) module. All direct current (DC) and alternating current (AC) electrical measurements were carried out in ambient air at room temperature.

A 30 nm-thick Al₂O₃ passivation layer was deposited on the MoS₂ at 220 °C using atomic layer deposition (ALD) (Atomic Classic, CN-1 Corporation). The duration of the growth was 10 hours (300 cycles with a growth rate of 1 Å per cycle). Trimethylaluminum (TMA) (UP Chemical Co., Ltd.) and deionized (DI) water were used as precursors. Ultra-pure N₂ (99.999%) was used as a carrier and purging gas. The sequence of the ALD cycle was H₂O (1 s)/N₂ (60 s)/TMA (1 s)/N₂ (60 s). The initial pressure of the growth chamber was ∼5 × 10⁻² Torr, and it was maintained at ∼1 Torr during the deposition.

In order to ensure that thermal annealing during the ALD process did not affect the comparison between devices with and without an Al₂O₃ layer, a thermal annealing process with the same conditions as the ALD growth process (i.e. 220 °C, 10 hours, ∼7 × 10⁻² Torr, but with no precursors) was applied to those devices without an Al₂O₃ passivation layer (see the ESI for further details†). From Fig. S1,† the as-fabricated MoS₂ transistor showed Schottky-like behavior in its output characteristics; however, following the thermal annealing process, ohmic-like behavior was observed. Even these relatively low-temperature thermal anneals appear to be sufficient to achieve ohmic-like behavior to MoS₂ devices.

Typically, a significant increase in drain current, which was observed here following the thermal anneal, is attributed to a decrease in the contact resistance. There may be a number of reasons for this. First, remnant polymer residues, which may come from the scotch tape or the electron beam resist between the channel and the contact, may be removed during the thermal annealing process to improve the effective junction area.²³ These residues can also act like an interfacial layer between the MoS₂ and the metal layer and be removed by the thermal annealing.²⁴ Another possible reason for the increase in the current is that gas molecules such as oxygen and water can be desorbed from the MoS₂ surface during the annealing process. Typically, oxygen and water adsorbed onto the surface can capture electrons from the MoS₂ and decrease the carrier concentration.^25–28 If those molecules are desorbed from the surface, especially near the contact, it can result in a decrease of the depletion layer width in the MoS₂–metal Schottky junction, followed by a decrease of the contact resistance. In order to do the precise static and LFN analysis by obtaining the linear I–V shape, therefore, the thermal annealing process should be required.

Results and discussion

Fig. 2(a) shows the typical transfer characteristics of the multilayer MoS₂ transistors with and without the Al₂O₃ passivation. We can confirm that the MoS₂ FET operates as an n-channel device. Important electrical parameters such as the field-effect mobility, μ_FE, the threshold voltage, V_th, and the on/off ratio are shown in Fig. 2(b) with and without the Al₂O₃ passivation layer. Interestingly, the on/off ratio decreased from ∼ 10⁵ to ∼ 10³ when the Al₂O₃ passivation layer was included, resulting from an increase in the off-current from ∼10⁻¹³ A to ∼10⁻¹⁰ A. In Fig. S2,† all other MoS₂ transistors that we measured showed the same results, which is the off-current increase after the Al₂O₃ passivation. This can be explained by considering that an additional channel is induced by the Al₂O₃ passivation (as discussed later in the paper). If an additional channel is induced near the top of the multilayer MoS₂ in parallel with the MoS₂ channel, it will be difficult to deplete the additional channel by controlling the back-gate voltage because of the geometry of the gate (i.e. there is poor gate-coupling). This off-current increase due to the Al₂O₃ deposition is not good news for electronic device applications, but we believe that these phenomena can be reduced and removed by staking the top-gate metal on the Al₂O₃ high-k dielectric.²⁹ Choosing the work function of the gate metal can naturally deplete the electrons in the channel due to the work function difference.³⁰ Also, by controlling the top-gate bias, the electrons in the additional top channel of MoS₂ can be easily modulated due to the enhancement of the gate-coupling.

Fig. 2 Changes in the DC electrical characteristics of the multilayer MoS₂ FETs with and without the Al₂O₃ passivation. (a) Transfer characteristics without (black line) and with (red line) the Al₂O₃ passivation. The inset shows a logarithmic plot of the transfer characteristics. (b) On and off-current with and without the Al₂O₃ passivation layer, as well as the on/off ratios. The table in the inset shows the threshold voltages and μ_FE.

The threshold voltage shifted from 11.1 V to −20.5 V by including the Al₂O₃ passivation. Although most of the gas molecules on the MoS₂ surface – such as oxygen and water – were removed during the thermal annealing process, whatever molecules remain may be adsorbed on the MoS₂ surface and can be removed during the ALD process. In addition, the overall effect of doping due to the Al₂O₃ layer may explain why V_th shifted. A slight increase in μ_FE from 8.4 to 9.9 cm² V⁻¹ s⁻¹ was observed with the Al₂O₃ passivation layer; μ_FE was 17.9% larger with the high-k dielectric. These charge carrier mobilities were extracted without considering the fringing fields and the dielectric constant of the Al₂O₃. When these factors are taken into consideration, the capacitance was 19.2% larger for the device with the Al₂O₃ passivation layer (see the ESI for details of the numerical calculation of the gate capacitance†). This variation between the gate capacitance values can be compensated between the μ_FE values for devices without and with the Al₂O₃ passivation. The effects of the high-k dielectric and the thermal annealing should be separated, especially when extracting μ_FE. The field-effect mobility includes the effects of the contact resistance between the metal contact layer and the semiconductor channel. The suppression of Coulomb scattering in the high-k environment is one possible mechanism for an increase of μ_FE of MoS₂,^6,9,15,31 however, it is important to consider that the decrease of the contact resistance following the ALD process may occur.^8,9 We have already established that the thermal annealing effects of the ALD result in a reduction in the contact resistance. An anomalous effect of the high-k dielectric on μ_FE was not observed in our devices. High mobility of MoS₂ FETs, however, is absolutely necessary to the device applications. Using a low work function metal such as scandium for the contacts could raise the mobility value,³² and decreasing of the substrate interactions might be a way of getting the higher mobility.³³ The selection of the proper number of layers might be another way to improve the mobility value.³⁴

Fig. 3(a) and (b) show the normalized drain current spectral density (S_I/I_ds²) as a function of frequency (f) at different gate voltages with and without the Al₂O₃ passivation, respectively. In both cases, a 1/f dependence of the noise was observed. The normalized drain current spectral densities decreased as the gate voltages increased, which can be explained by considering that the noise sources were almost constant; however, as V_gs increased, the drain current also increased, resulting in a larger signal-to-noise ratio. It appears that these multilayer MoS₂ transistors follow the conventional 1/f noise characteristics that have been reported for numerous nanoscale devices, including graphene,^35–37 carbon nanotubes,^38,39 ZnO nanowires,^40,41 SnO₂ nanowires,^42–44 Bi₂Se₃ thin films.⁴⁵

Fig. 3 LFN characteristics of the multilayer MoS₂ FETs. The normalized drain current spectral density as a function of the frequency at various gate voltages is shown (a) without and (b) with the Al₂O₃ passivation layer. The dashed lines in the curves show the 1/f dependence. (c) The mean normalized drain current spectral density as a function of the drain current for frequencies of 10, 12, 14, 16, 18, and 20 Hz, both without (black) and with (red) the Al₂O₃ passivation layer.

In order to directly compare the noise characteristics at a given same drain current, we plot the normalized drain current spectral density, S_I/I_ds², as a function of the drain current, I_ds. These data are shown in Fig. 3(c) both with and without the Al₂O₃ passivation. At relatively large currents, in the strong accumulation regime, the noise levels were very similar. However, at relatively low current levels, i.e. in the subthreshold regime, the noise level was higher with the Al₂O₃ passivation layer. It follows that the Al₂O₃ layer resulted in an additional noise source that could be observed at the low currents.

Two models exist to describe the LFN in conventional Si MOSFETs.¹⁶ The Hooge mobility fluctuation (HMF) model describes fluctuations of the carrier mobility due to fluctuations of the mean free-path of electrons, which leads to fluctuations in the charge carrier mobility. The carrier number fluctuation (CNF) model describes fluctuations in the charge carrier density due to charges localized at the trap sites near the channel–oxide interface.

To investigate which noise model best describes the observed behavior of the multilayer MoS₂ FETs, we plotted S_I/I_ds² as a function of the drain current, I_ds, without (Fig. 4(a)) and with (Fig. 4(b)) the Al₂O₃ passivation layer. According to the CNF model, the normalized drain current spectral density can be expressed as:¹⁶

where g_m is the gate transconductance and S_Vfb is the flat band voltage spectral density, which can be expressed as:where q is the electronic charge, k_B is the Boltzmann constant, T is the temperature in Kelvin, W and L are the width and the length of the channel, respectively, C_ox is the gate capacitance per unit area, and N_it is the interface trap density. The CNF model fits well to the S_I/I_ds² − I_ds data as in Fig. 4(a) and (b) in the strong accumulation regime, both with and without Al₂O₃ passivation. (The strong accumulation regimes are represented in the transfer characteristics and in the band diagram in Fig. 4(c) and (d), respectively.) This result is plausible because the accumulation channel in the MoS₂ is probably induced near the MoS₂–SiO₂ interface by modulating the back-gate voltage, regardless of the existence of an Al₂O₃ passivation layer; therefore, trap sites near the MoS₂–SiO₂ interface can be expected to be the dominant noise source. Fig. 4(d) shows band diagrams in which a strong accumulation regime occurs when the back-gate voltage is sufficiently large (and positive) to accumulate electrons near the SiO₂ gate dielectric, regardless of the presence of the Al₂O₃ passivation layer. The interface trap density calculated using eqn (1) and (2) was N_it = 7.2 × 10¹⁰ cm⁻² eV⁻¹ without the Al₂O₃ passivation layer and N_it = 5.5 × 10¹⁰ cm⁻² eV⁻¹ with the Al₂O₃ passivation layer. Those two values are similar, and so the surface channel near the SiO₂ was not strongly affected by the top passivation layer within the strong accumulation regime. In addition, N_it was one order of magnitude larger compared with N_it ∼ 10⁹ cm⁻² eV⁻¹ at the Si–SiO₂ interface in Si MOSFETs.¹⁷ This one order of difference between the N_it values can be further improved through the optimization of the fabrication process.

Fig. 4 LFN, transfer characteristics, and band diagrams with and without the Al₂O₃ passivation layer. Normalized drain current spectral density (NSI) from the noise spectra as a function of the drain current (a) without and (b) with the Al₂O₃ passivation layer. The HMF and CNF models were fitted to the raw data. CNF_top and CNF_bottom refer to the fitted carrier number fluctuation models for the top (near the Al₂O₃) and the bottom (near the SiO₂) surfaces of the channel. The fitting data for the summation of the HMF and CNF models are denoted by “SUM”. (c) Drain current as a function of the gate overdrive voltage, V_ov = V_gs − V_th, both with and without the Al₂O₃ passivation layer. The subthreshold and the strong accumulation regimes are indicated by the gray region. (d) Simplified band diagrams without (left) and with (right) the Al₂O₃ passivation. The band diagrams at the top, middle, and bottom indicate when the device is as fabricated, with an applied negative gate voltage, and with an applied positive gate voltage, respectively. The conduction and valence band edges of SiO₂ and Al₂O₃ have been omitted for clarity.

At small currents, i.e. the subthreshold regime, there were large discrepancies between the CNF model and the measured S_I/I_ds² data shown in Fig. 4(a) and (b). The subthreshold regimes are represented as the transfer characteristics in Fig. 4(c), and as band diagrams in Fig. 4(d). Considering that multilayer MoS₂ FETs operate as accumulation-mode transistors, since MoS₂ is a natural n-type semiconductor, and that the devices are junctionless transistors, i.e. they have the same doping concentrations in the source, drain, and channel regions, we can expect that the threshold voltages should be less than or equal to the flat-band voltages.⁴⁶ The enlarged section of the transfer characteristic curve below the threshold voltage without the Al₂O₃ passivation layer, shown in Fig. 4(c), is consistent with FETs that operate in accumulation-mode and are junctionless. These kinds of “stretched-out” transfer characteristics are typically observed in accumulation-mode and junctionless transistors, and are regarded as the bulk conduction portions.^47,48 However, the threshold voltages extracted from the transfer characteristics in this study were larger than the flat band voltages.³² Due to the very small contribution of bulk conduction to the total current, this stretched-out part of the transfer characteristics can be ignored, and the surface conduction channel is important in determining the threshold voltages. If the doping density or the effective channel size of the multilayer MoS₂ is small enough, the bulk conduction channel is hard to observe in the transfer characteristics. In this study, the transfer curve shown in Fig. 4(c) suggests a relatively small bulk conduction portion. When the bulk conduction is the dominant current pathway (in the subthreshold regime), there is a possibility that the CNF model may not be appropriate, and that instead, the HMF model may better describe the noise characteristics of the subthreshold regime.

According to the HMF model, the normalized drain current spectral density can be expressed as:¹⁶

where α_H is the Hooge parameter and Q_acc is the accumulated charge. If the accumulated charge follows the form of Q_acc = C_ox(V_gs − V_th) and the accumulated charge is approximated to the bulk channel charge, the following relationship holds:where μ is the charge carrier mobility and V_ds is the drain voltage. By fitting the HMF model to the measured S_I/I_ds² without the Al₂O₃ passivation layer (Fig. 4(a)), the behavior in the subthreshold regime is well described. This HMF model is not observed even in the Si junctionless transistors that have the high portion of bulk conduction.⁴⁹ This might be the distinguished properties of layered nanomaterials which will be discussed below. The Hooge parameters extracted from eqn (3) and (4) with and without the Al₂O₃ passivation were almost identical, at α_H = 2.5 × 10⁻³. This Hooge parameter is similar to or smaller than previous reports for graphenes, carbon nanotubes, amorphous Si, and metal oxide semiconductors.^{35,36,39,43,50}

In many reports of noise analyses, it is unclear whether the noise characteristics follow the HMF or CNF model. The HMF model has rarely been introduced to explain the noise characteristics, even in Si MOSFETs. Particularly, the HMF model has been used to describe the noise characteristics of p-MOS buried-channel structures,⁵¹ and more recently, Persson et al.⁵² showed that the HMF and the CNF models could be used to describe the noise properties in the vertical wrap-gated Sn-doped InAs nanowire FETs with the core channel and the surface channel, respectively. In the case of the multilayer MoS₂ FET, however, the HMF model is relatively easily observed without the buried-channel structures or any intentional doping and the gate-all-around structures. Even in the case of the relatively thick-multilayer (∼40 nm) MoS₂ FET, we confirmed that only the HMF model was fitted all over the operation regime as in Fig. 5. This implies that the influence of the traps in the gate insulator to the conduction is very weak. Recently, Das et al.⁵³ suggested the resistor network model to describe the current distribution in multilayer MoS₂ FET based on Thomas–Fermi charge screening and interlayer coupling. According to those results, accumulation charges induced by the back gate bias can be distributed deeply along to the multilayer MoS₂ due to the high T–F charge screening length (λ ∼ 7 nm) and the interlayer resistance (R_int) has high value, so the dominant current flow may not occur though the lowest layer of the multilayer MoS₂. Once the dominant conduction is far from the gate insulator, the probability arising from the carrier trapping/detrapping in the oxide traps in the gate insulator can be reduced, which is already confirmed by other studies that we have referred to above.^51,52 This might be a reason why the HMF model is well fitted instead of the CNF model in the thick-multilayer (∼40 nm) MoS₂ FETs in the entire regime. In the case of the 11.3 nm thick-multilayer MoS₂ FET, the CNF model could be introduced to describe the noise properties in Fig. 4(a) because the thickness of the MoS₂ is relatively small, although the dominant current flow does not occur through the lowest layer. If then, there is still a possibility to introduce the CNF model in the strong accumulation regime. Our results can describe Das et al.'s work,⁵³ but more specific theory about the current flow in 2-D nanomaterials should be studied. Also, using the relatively well-described Si accumulation-mode or junctionless transistor theory to describe the electrical properties of MoS₂ FETs should be accompanied.

Fig. 5 (a) Optical images after the formation of source/drain metal contact on the thick-multilayer MoS₂. ‘D’ and ‘S’ represent the drain and the source contact, respectively. Other electrodes were intended for the four probe measurements but were not used in the noise measurements. The scale bar is 5 μm long. The inset shows that the thickness of the MoS₂ layer was approximately 40 nm by AFM. (b) Normalized drain current spectral density (NSI) from the noise spectra as a function of the drain current without the Al₂O₃ passivation layer. Only the HMF model (HMF) was fitted to the raw data.

In the device with the Al₂O₃ passivation layer (Fig. 4(b)), the HMF model does not adequately fit the S_I/I_ds² behavior. In the subthreshold regime, the surface channel near the SiO₂ was not the dominant pathway, and instead, bulk conduction and other surface current pathways induced by the Al₂O₃ passivation were dominant in the noise characteristics. Fig. 4(d) shows the band diagrams with the Al₂O₃ layer; this indicates the possibility of additional surface channels near the MoS₂–Al₂O₃ interface. By introducing the additional CNF model to fit the data in the subthreshold regime, a good fit was obtained, as shown in Fig. 4(b). This distinct difference between the devices with and without the Al₂O₃ passivation layer is consistent with the bump in the curve shown in Fig. 3(c), which was attributed to additional surface channels induced by the Al₂O₃ passivation layer. Considering the high value of the interlayer resistance (R_int),⁵³ the existence of the additional top surface channel induced by the Al₂O₃ passivation is very convincing. When both of the charges induced by Al₂O₃ on the topmost layer of the MoS₂ and the R_int are high, the conditions are sufficiently satisfied so that the dominant current flow can occur through the topmost layer in the deep subthreshold regime of the multilayer MoS₂ FET with the Al₂O₃ passivation.

If C_ox at the top surface channel caused by the Al₂O₃ layer can be approximated to that of the surface channel induced by the back-gate, the interface trap density for the Al₂O₃–MoS₂ interface can be extracted as N_it = 1.8 × 10¹² cm⁻² eV⁻¹ from the additional CNF model using eqn (1) and (2). If the C_ox is considered to be overestimated owing to the geometrical gate coupling effect, then N_it will be lower according to the C_ox² dependence as in eqn (2); therefore, we can expect N_it ∼ 10¹¹ cm⁻² eV⁻¹. This is consistent with the interface trap density (D_it) = 2.4 × 10¹² cm⁻² eV⁻¹, and D_it = 2.6 × 10¹¹ cm⁻² eV⁻¹ for the MoS₂–Al₂O₃ interface in top-gate¹⁵ and back-gate¹¹ geometries, calculated using the subthreshold swing, respectively. In addition, D_it in high-k materials has been reported to lie in the range 10¹¹ < D_it < 10¹² cm⁻² eV⁻¹.^18,19,54 If the electrical parameters such as C_ox or mobility can be extracted more precisely by using the analytical or numerical solutions, we believe that the noise analyses of the MoS₂ FETs can be a more powerful tool to diagnose the interface quality between the high-k dielectric and MoS₂.

High-k dielectrics, including Al₂O₃, HfO₂, and ZrO₂, are known to retain more fixed charges than SiO₂.^18,19,39,54 To ensure stable device operation, the effects of these fixed charges on the device characteristics should be studied. Carbon nanotube transistors have been observed to change from p-type to n-type following Al₂O₃ passivation; this was attributed to fixed charges, with the positive polarity in the Al₂O₃ leading to electrostatic doping.^55,56 Shin et al.⁵⁷ suggested that there may be a nonuniform distribution of fixed charges in Al₂O₃. In InGaAs–Al₂O₃ structures, negative fixed charges may be located near the interface between the Al₂O₃ and the InGaAs, with positive fixed charges in the Al₂O₃ away from the interface. This suggests that the total electric field in the MoS₂ in our samples may be the sum of the potential due to localized charge distribution near the MoS₂–Al₂O₃ interface and in the bulk part of the Al₂O₃ layer. Then, the dominant fixed charges can be positive in our case, as shown in Fig. 6, because the bulk part of the Al₂O₃ layer that we deposited is relatively as large as the 30 nm-thick. It is clear that an additional top surface channel in the multilayer MoS₂ transistors is induced by the Al₂O₃ passivation. The increase in the off-current and the noise characteristics is evidence of this. If those phenomena result from fixed charges in the Al₂O₃ layer, the electrostatic doping effect may be positive in the case of the multilayer MoS₂ transistors reported here.

Fig. 6 Schematic diagrams of the cross-section of the device (a) without and (b) with the Al₂O₃ passivation layer. In ambient air, gas molecules (mainly oxygen and water) are absorbed on to the MoS₂ surface and induce a depletion region. Following the Al₂O₃ passivation, the gas molecules in ambient air can no longer deplete the multilayer MoS₂; however, positive fixed charges in the Al₂O₃ layer can induce an additional conduction pathway via electrostatic doping at the top of the MoS₂ layer.

Conclusions

We have performed LFN characterization of multilayer MoS₂ FETs (∼11.3 nm) with and without an Al₂O₃ passivation layer. In the strong accumulation regime, the carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface was used to describe the noise behavior, both with and without the passivation. The interface trap density at the MoS₂–SiO₂ interface extracted from the LFN measurements was N_it = 7.2 × 10¹⁰ eV⁻¹ cm⁻² without the Al₂O₃ passivation layer and N_it = 5.5 × 10¹⁰ eV⁻¹ cm⁻² with the passivation layer. Those two similar N_it values represented that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model was introduced to describe the electrical properties in terms of bulk conduction in the subthreshold regime. For the thick-MoS₂ (∼40 nm) FET, the HMF model was fitted all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS₂. With the addition of the Al₂O₃ passivation, an additional top surface channel was induced, which led to an increase of the off-current. This change is also apparent in the noise behavior so the additional (CNF) model was successfully introduced when the Al₂O₃ passivation layer was placed. The trap density at the MoS₂–Al₂O₃ interface was N_it = 1.8 × 10¹² eV⁻¹ cm⁻². These results can be a great help to understand the interactions between MoS₂ and high-k materials.

Acknowledgements

This work was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (Converging Research Center Program, 2013K000175 and Global Frontier Research Program, No. 2011-0031638).

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Footnote

† Electronic supplementary information (ESI) available: The effects of thermal annealing, the change of the off-current, the numerically calculated gate capacitances, the raw LFN data, and specific band diagrams are described in detail here. See DOI: 10.1039/c3nr04218a

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