Physics and chemistry of CdTe/CdS thin film heterojunction photovoltaic devices: fundamental and critical aspects

Abstract

Among the armoury of photovoltaic materials, thin film heterojunction photovoltaics continue to be a promising candidate for solar energy conversion delivering a vast scope in terms of device design and fabrication. Their production does not require expensive semiconductor substrates and high temperature device processing, which allows reduced cost per unit area while maintaining reasonable efficiency. In this regard, superstrate CdTe/CdS solar cells are extensively investigated because of their suitable bandgap alignments, cost effective methods of production at large scales and stability against proton/electron irradiation. The conversion efficiencies in the range of 6–20% are achieved by structuring the device by varying the absorber/window layer thickness, junction activation/annealing steps, with more suitable front/back contacts, preparation techniques, doping with foreign ions, etc. This review focuses on fundamental and critical aspects like: (a) choice of CdS window layer and CdTe absorber layer; (b) drawbacks associated with the device including environmental problems, optical absorption losses and back contact barriers; (c) structural dynamics at CdS–CdTe interface; (d) influence of junction activation process by CdCl₂ or HCF₂Cl treatment; (e) interface and grain boundary passivation effects; (f) device degradation due to impurity diffusion and stress; (g) fabrication with suitable front and back contacts; (h) chemical processes occurring at various interfaces; (i) strategies and modifications developed to improve their efficiency. The complexity involved in understanding the multiple aspects of tuning the solar cell efficiency is reviewed in detail by considering the individual contribution from each component of the device. It is expected that this review article will enrich the materials aspects of CdTe/CdS devices for solar energy conversion and stimulate further innovative research interest on this intriguing topic.

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S. Girish Kumar

Dr S. Girish Kumar is an native of Karnataka (Kolar District, Malur Taluk) and obtained his MSc in Physical Chemistry (2005) and PhD (2012) degree in the area of photocatalysis from Bangalore University, Bangalore. He is the recipient of India's most prestigious Dr D. S. Kothari Post Doctoral Fellowship (2012) and works under the supervision of Prof. Rao at Department of Physics, I.I.Sc, Bangalore on CdTe/CdS thin film heterojunction solar cells. The study of phase transition and photoluminescence properties of mixed phase titania and other heterojunctions are his present interests.

K. S. R. Koteswara Rao

Dr K. S. R. Koteswara Rao is associate professor at the Department of Physics, Indian Institute of Science, Bangalore, India. He works in the field of semiconductors. His research interests are understanding defects in semiconductor materials and their heterostructures by optical (photoluminescence, optically induced conductivity modulation, etc.) and electrical methods. Growth and study of III–V and II–VI based binary, ternary and quaternary compound semiconductor nano- and micro-structures and their utility for device applications are his current research studies.

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Broader context

As an alternative to the widely used Si based homo junction solar cells, research interest is triggered by the development of thin films based on p-CdTe/n-CdS heterojunction solar cells. The easy preparation of these semiconductors by an array of physical and chemical methods and high absorption coefficient of absorber layer, together with their stability against high energy particle irradiation, drives their capacity towards solar energy conversion. The unique interfacial structure between the window and absorber layer is attributed to the efficient conversion of light energy. This review article discusses the fundamental and critical aspects of this novel device architecture emphasizing concepts of its physics and chemistry. The strategies developed to improve the efficiency of solar cells are discussed by considering the individual contribution from each component of the cell. Also, the prospects and focus for future development in this exciting field are suggested.

1. Introduction

Increasing worldwide demand for energy and limited fossil fuel reserves on the planet Earth require the development of reliable, sustainable and renewable energy sources.¹ Among various technologies available, PVs are believed to be the cleanest way to achieve the desired goals from the viewpoint of solar energy conversion. The II–VI semiconductors have been a focal point in this regard since they offer a spectrum of materials whose band gap energy spans the entire wavelength range of solar light with superior optical conversion efficiencies. With the exception of HgSe and HgTe (semimetals), II–VI semiconductors have a direct band gap with a sharp optical edge and a large absorption coefficient at above band-gap wavelengths. The II–VI compound semiconductors have a higher band gap energy due to their larger ionicity and high carrier effective mass, while the radiative carrier lifetime and carrier diffusion lengths are small compared to III–V compounds.² Silicon, an indirect band gap material (E_g = 1.1 eV) is a material of choice for more than 90% of PV production. However, the major drawbacks of silicon solar cells originate from their high cost involved in the fabrication, the shortage of silicon feedback and its low absorption coefficient (100 cm⁻¹), which require several hundred microns of thickness to absorb most of the incident light.^3,4 Although amorphous silicon solar cells are also used, they are sensitive for degradation upon exposure to sunlight with an efficiency loss of 10–20%.⁵ Therefore, research interest is triggered for the development of other solar cells like dye sensitized solar cells, bulk heterojunction solar cells, hybrid polymer solar cells, inorganic–organic heterojunction solar cells and quantum dot sensitized solar cells.^6–22

As an alternative to the silicon solar cell, the polycrystalline thin film CdTe/CdS heterojunction diode has drawn significant attention from commercial organizations to achieve better efficiency/cost ratio because of its facile adaptability to large scale manufacturing processes. The CdTe based solar cell is currently a very competitive PV product in the solar cell market. It is estimated that CdTe/CdS thin film technology can reduce manufacturing cost at 1 ECU per W_p compared to Si technologies, and its energy payback time can be minimized compared to others.^23,24 Since the realization of thin film solar cells based on CdTe²⁵ and novel contributions from Bonnet,²⁶ research on this module for direct conversion of solar energy to electricity has drastically improved.^27–57 The requirement of CdTe/CdS thin film devices are simple in comparison to most routinely produced electronic and optoelectronic structures, which comprises: (i) a TCO layer as front contact; (ii) an n-CdS window layer; (iii) a p-CdTe absorber layer; (iv) an electrical junction that should be engineered at the interface of window and absorber layer for efficient carrier collection; (v) a back ohmic contact. The front contact should have an electron affinity below 4.5 eV to form an ohmic contact and good band alignment with the window layer, which otherwise forms a blocking Schottky contact. The device configuration is “superstrate”, which means that light enters from the glass substrate (Fig. 1). The superstrate configuration facilitates low-cost encapsulation of solar modules and for the design of high efficiency tandem solar cells. In this device structure, several layers with different band gaps are used that allow effective transformation of solar radiation to electricity in a wide spectral range and minimize the thermalization losses.

Fig. 1 Schematic representation of a CdTe/CdS solar cell in the superstrate configuration.

Both CdTe and CdS are quite stable and can be produced using various scalable techniques like CBD, CSS, MOCVD, ED, ALE, screen printing, sputtering, sintering, MBE and HVE.^58–83 The conversion efficiency of the homojunction CdTe solar cell was not encouraging and hence a heterojunction with a wide band gap n-CdS semiconductor was developed. It is also reported that polycrystalline solar cells exhibit better performance compared to single crystal materials,⁸⁴ which is probably due to the passivation of GBs by the segregation of materials like CdF₂, CdSO₃ and CdSO₄ in a CdS film or CdTeO₃ in a CdTe film.⁸⁴ In particular, band bending that forms near CdTe GBs effectively separates photogenerated charge carrier pairs, while the GB core is an efficient transport of minority carriers.⁸⁵ However, such comparison cannot be justified as processing conditions for optimizing single crystal and polycrystalline cells are extremely different. For a small area module (1 cm²), the PV conversion attained is 16.5%, while the efficiency is slightly lower (10.5%) for large area modules (1400 cm²), which are being developed for large scale production.^86–89 Although this efficiency is achieved on a laboratory scale, CdTe/CdS thin film solar cells have already arrived to a stage comparable to more sophisticated single crystal silicon materials technology.⁵⁷

Previously published reviews discuss the back contact strategy, junction activation step and technology related issues, besides focusing on other PV materials like amorphous, microcrystalline and polycrystalline silicon solar cells, CuInSe₂, CuInS₂, CuIn_1−xGa_xSe₂, multi junctions etc.^{27–38,44–50,53} In this review, key issues in fundamental and critical aspects of CdTe/CdS PVs are discussed from the viewpoint of materials science encompassing their physics – device performance, and chemical concepts – and reactions occurring at various interfaces.

2. Choice of CdS and CdTe

As the solar cell efficiency depends on the product of V_oc and I_sc, there exists optimum band gap energy in a device for producing maximum output. A detailed analysis for the dependence of power conversion efficiency on the semiconductor band gap for the black body limit revealed that for terrestrial power generation under the AM 1.5 and AM 1 spectrum, the optimum band gap energy required is 1.5 eV which approximates to semiconductors like CdTe, InP, GaAs and CuInS₂ (Fig. 2).^90–94 In practice, a band gap energy in the range of 1.0–1.7 eV like mono crystalline and polycrystalline silicon (1.12 eV), CuInSe₂ (1.05 eV) and α-Si:H (1.7 eV) also find applications. The silicon based devices are usually a homojunction, while most of the other devices constitute a heterojunction.

Fig. 2 Power conversion efficiency as a function of semiconductor band gap. Asterisks show the best confirmed solar cell efficiencies under AM 1.5 illumination (reprinted with permission from ref. 92; copyright @ 2006 Elsevier).

2.1 Properties of the CdTe absorber layer

The CdTe is a robust semiconducting material, which can be prepared by various synthetic routes in a highly reproducible manner and its remarkable tolerance towards high processing temperatures makes it ideal for large scale industrial production. The CdTe/CdS solar cells are unusual as they exhibit superior performance only in the superstrate configuration compared to their substrate counterparts. These two polycrystals (CdTe and CdS) are chemically stable and high optical quality layers are deposited in the temperature range of 400–600 °C. Since high thermal treatment is involved during CdTe deposition by most of the preparative techniques, CdTe films are associated with V_Cd giving rise to p-type conductivity. The high ionicity (72%) of CdTe results in well-passivated crystallites, while high chemical–thermal stability is associated with strong chemical bonding (5.75 eV).⁹⁵ The stability region of CdTe is extremely narrow (2 × 10⁻⁶ atom% wide) and is symmetrical with a perfect stoichiometry at 400 °C.³⁸ At a temperature of 500–600 °C (deposition of CdTe via CSS), p-CdTe will have a carrier concentration >10¹⁴ cm⁻³ that is sufficient to form a good junction with its n-type partner. This is of paramount importance, since doping of polycrystalline film must be avoided as foreign elements, especially metals, segregate into the GBs.⁵⁷ The stability region of the Te-rich side increases to about 10⁻⁵ atom% close to the CdTe melting point (1090 °C). In vacuum, CdTe sublimates such that the vapor phase consists of Cd atoms and Te₂ molecules in exact proportion to the solid (partial pressure of Cd = 2 × partial pressure of Te₂). Consequently, CdTe deposition by thermal evaporation does not constitute any stoichiometric problems.³⁸ The CdTe solar cells have proven to be extremely stable, and devices with notable efficiency >10% are fabricated by several deposition methods.

CdTe is potentially a good absorber due to its large absorption coefficient (>1 × 10⁴ cm⁻¹)^96,97 and its direct band gap allows only a few microns of material to absorb 90% of photons with E_g > 1.45 eV.^2,57,94 Another important aspect is that the carrier lifetime for CdTe is small (of the order of 1 × 10⁻⁷ s or less) with a mobility ranging from 10 to 100 cm² V⁻¹ s⁻¹. The short optical absorption length in II–VI compounds also renders the carrier diffusion length in minority carrier devices relatively insignificant. The diffusion length in CdTe film grains will be between 1 and 5 μm and hence the active layer thickness will be within the limits of 1–5 μm.²⁷ Thus, solar cells can be fabricated using a much lesser quantity of CdTe with a depletion layer width comparable to film thickness. The reduced thickness of the absorber gives rise to a intense electric field and therefore a large fraction of carriers will be generated within the depletion layer, facilitating efficient carrier collection.⁴ CdTe offers flexibility in device design as it forms isostructural and isoelectronic alloys with other II–VI compounds such as HgTe and ZnTe, allowing the band gap of the absorber layer to be narrowed or widened for tandem cell and optical detector applications.⁹⁸ CdTe has a high temperature coefficient of bandgap (2.3–5.4 × 10⁻⁴ eV K⁻¹),³⁸ the highest stability against electron/proton irradiation (Fig. 3), a low stacking-fault energy, is predisposed to twinning and planar faulting and exhibits both p-type and n-type conductivity.^99,100 As grown CdTe under Cd-rich conditions is n-type due to the Fermi-level being pinned near the mid gap by the compensating donor effect Cd_i²⁺. Under the Te-rich limit, CdTe behaves as p-type as the Fermi-level is pinned close to VBM.¹⁰¹

Fig. 3 Degradation curves of different solar cells (reprinted with permission from ref. 116; copyright @ 2004 Elsevier).

Since the band gaps of bulk CdTe and CdS are 1.5 and 2.4 eV respectively, photons with energies within this range can reach the CdTe layer, contributing to the cells photocurrent.¹⁰² The theoretical efficiency limit for cells with the CdTe room temperature band gap (1.5 eV) is 30%.^103–105 However, a practical efficiency of 18.5% could be expected for this material with a V_oc of 0.88 V and J_sc of 270 A m⁻² (with a negligibly thin CdS).¹⁰⁶ The maximum photocurrent available from a CdTe cell under the global spectrum normalized to 100 mW cm⁻² is 30.5 mA cm⁻².⁴⁴ The efficiency of solar cells can be further enhanced by considering a few aspects like increasing the grain size of CdTe and using a thin absorber layer with controlled film morphology to achieve compact and pinhole-free layers so as to avoid short circuits, shunt resistance and weak diodes.

2.2 Properties of CdS window layer

The CdS is the most widely used window material for thin film CdTe solar cells. The multiple roles of CdS are: (i) it acts as a window layer relating to spectral response at shorter wavelength regions; (ii) it plays a vital role for the crystallinity of the CdTe layer; (iii) it facilitates the formation of large bandgap CdTe_1−xS_x mixed crystal layers near the CdS–CdTe interface, which improve the properties of the absorber layer. CdS is used either for establishing an electric field at the heterojunction interface that collects the photogenerated charge carriers or as “buffer layer” that avoids the interface mismatch between TCO and CdTe.²⁷ If CdS is used as a “buffer layer”, its resistivity should be high enough to ensure stoichiometry and a good quality layer in order to reduce the trap-state density at the interface to improve junction properties. Alternatively, if CdS is used as the active layer of the heterojunction itself, resistivity must be small for a good ohmic contact with the TCO layer and the electric field at the CdS–CdTe interface should be high to improve the V_oc.²⁷ The n-CdS window layer is an essential component of the cell; although a p-CdTe/TCO junction with efficiency >10% has been reported,¹⁰⁷ such a junction was however found to be inferior. The fundamental requirements of CdS are that it should be conductive (n ∼ 10¹⁶ cm⁻³) and thin enough to allow high transmission (50–100 nm), and uniform in order to suppress short circuit effects.

The C–V calculation for CdTe/CdS solar cells indicated a ΔE_v of 0.87 eV and an interface charge density (σ) of around 1 × 10¹³ cm⁻², which are important parameters in the improvement of solar cell quality.¹⁰⁸ Niles and Hocst experimentally reported a ΔE_v of 0.65 eV by the photoemission method¹⁰⁹ and Wei et al. reported a value of 0.99 eV using first-principles calculations.¹¹⁰ The stepwise deposition of a CdTe film on a wurtzite CdS {0001} single crystalline substrate by MBE resulted in a ΔE_v of 0.65 eV and a ΔE_c of 0.31 eV, indicating type-I band alignment (Fig. 4). Also, CdS showed strong upward band bending of 0.55 eV during junction formation.¹¹¹ The reported band offset for the CdTe/CdS heterojunction falls into a wide range of 0.58–1.19 eV.^{109,112–114} Band offsets are quite sensitive to sample preparation conditions such as substrate orientation, surface/interface states and heterojunction formation sequence.

Fig. 4 Band alignments of CdS (0001)/CdTe heterojunction (reprinted with permission from ref. 111; copyright @ 2012 IOP Science).

Due to the fascinating PV properties of the window/absorber layer and good scalability of techniques used to produce thin film PVs, these devices are already produced in modules of 60 × 120 cm² by two companies: Antec Solar in Germany and First Solar in the United States.⁵⁷ This heterostructure is usually preferred because the minority diffusion length of electrons in a p-type semiconductor is much greater than that of holes in an n-type semiconductor.¹¹⁵ These solar cells perform faster recovery from the induced damage, presumably due to strong defect compensation effects in CdTe.¹¹⁶ Recovery of light-stress induced degradation can be caused by either storage or annealing in the dark.¹¹⁷ In this case dissociation of acceptor defects in CdS, such as substitution of Cu at the Cd site (Cu¹_Cd) and a [V_Cd–Cu_i]¹ complex into V_Cd and Cu_i, back-diffusion of Cu⁺ driven by a concentration gradient and a restored junction field leads to the recovery of the original behavior.¹¹⁷ Even the reflection losses for this device are not critical as compared to a silicon solar cell. The coefficient of reflection from the mirror surface of silicon is at least 30%, and higher than 50% in the region of λ < 400 nm.¹¹⁸ Thus, the better formation enthalpy, good chemical stability, favorable opto-electronic properties and unique interfacial structure of CdS–CdTe have driven this novel device architecture as a promising contender for solar cell applications.

3. Problems associated with CdTe/CdS solar cells

3.1 Technical and environmental issues

The performance of a heterojunction depends on the formation of an interface structure during thin film deposition and any subsequent processing. The variation in the quality of materials obtained by different techniques or even with same approach but under varied growth conditions can influence the device performance. Diverse preparation techniques can also cause variation in material properties such as carrier lifetime, mobility and their absorption coefficient. One of the important requisitions for this device is to reduce the thickness of the PV active layer from the standpoint of lowering production costs and cadmium toxicity. Another issue in CdTe technology is the junction activation step involving a toxic chlorine atmosphere which should be either modified or completely eliminated. Even if full recycling of modules is offered by manufacturers and designers, it is still doubtful that the production and deployment of cadmium-based modules could be so environmentally benign as to justify their use.¹¹⁹

Tellurium is a scarce element; hence CdTe PV module production seems to be limited to a peak of a few gigawatts per year and constrained due to the volume of potentially hazardous cadmium compounds being used in a typically 3–8 μm thick CdTe layer.^119,120 Therefore, it is necessary to reduce the CdTe thickness layer in these devices. The development of cells with a much thinner layer (<1 μm, ultrathin) would help to extend tellurium supplies with additional benefits like improved understanding of device operation, reduced cost of materials and manufacturing time, high throughput, easier cell isolation, minimum use of toxic materials and reduced secondary waste treatment cost at the manufacturing process.¹²⁰ Although CdTe with a typical thickness of 1–2 μm would be optimal for both optical and electrical applications, in practice it is very hard to achieve without a subset of problems. The submicron absorber thickness deteriorates the device performance quickly due to increased defect densities accompanied by the loss of photocurrent. In addition, the absorber layer thickness becomes much smaller than the photon absorption length leading to incomplete optical absorption with a thin absorber (deep penetration loss).^121,122

3.2 Factors responsible for device degradation

3.2.1 Stress factor. It is often reported that improvement in cell performance is only temporary as the stability declines over a period of time. The CdTe solar cells are susceptible for degradation under illumination mainly due to thermal stress, low back contact stability with poor ohmic contact in CdTe, large R_s, and inhomogeneity of the CdTe/CdS heterojunction. The extent and type of degradation can vary with materials properties such as deposition parameters, layer thickness and quality, together with the nature of stress indicating that different degradation mechanisms will be operative within the cell structure. Singh and co-workers¹²³ showed that the unencapsulated solar cell stored at room temperature in a molecular sieve were stable, while cells stored at high humidity and in the open air at 100 °C suffered from drastic degradation. In fact, cells stressed in humid air reduced their efficiency from 7.5–1.3%. Based on a model, it was hypothesized that back contact degrades due to oxygen migration through the metal to tellurium excess at semiconductor surface. The oxygen combines with CdTe to form an insulating CdTeO₃ layer between the metal and semiconductor. In addition, the model indicated the fast degradation was due to the growth of CdTeO₃ from 20–80 Å for a barrier height of 0.1 eV.¹²³ The cells degraded during light-stress (in dry N₂) recovered their original performance after some time, either under air ambient conditions or by heat treatment at 200 °C in dry N₂ subjected in the dark (20 h). However, such a recovery was not observed in the case of extended stress treatments (60 h).¹¹⁷ This suggests that electronic and/or chemical changes occurring in the cell structure at shorter stress times will become irreversible in the latter case. The solar cell showed very little degradation with thermal stress at 200 °C in a dry N₂ atmosphere under dark (>50 h) due to the minor loss of FF and J_sc without any roll-over even with increasing time. In contrast, significant degradation was observed under thermal stress in air ambient at 200 °C (20 h) with great loss of FF, J_sc accompanied by roll-over. The XPS indicated the formation of CdTeO₃ or CdTe₂O₅ in an air stressed sample, while such tellurium oxides were not found in unstressed and N₂ stressed samples after sputtering. When stressing was carried out in humid air, a more pronounced degradation was observed due to the polar and screening nature of water that facilitated the oxide formation by reducing the barrier in the actual oxidation reaction.¹¹⁷ In the humid environment, water vapor tends to be adsorbed at the junction interface and the ionic species become mobile. The electric field at the junction and the application of forward bias under illumination favors the migration of ionic species across the junction surface. The surface current varies with humidity in the environment and couples to other components of dark current at the junction. Therefore, the junction surface should be protected from the environment which makes the surface ions immobile.² Hence the solar cell can be practically stable as long as oxygen and water are excluded rigorously.¹²⁴ The efficiency reduced from 11.8–10.7% with a minimal loss in V_oc after subjecting the cell to thermal treatment (200 °C, 1.5 h) under open circuit conditions with an MoO_x/Ni back contact. This was attributed to an inhibitory reaction between Ni and CdTe by the MoO_x buffer layer, which otherwise leads to the formation of nickel oxides formed by abstracting oxygen from tellurium oxide on the CdTe surface.¹²⁵

3.2.2 Impurity diffusion and grain boundary effects. The ultimate electrical property of a device depends on mobile impurities in the materials and interfaces which represents a major technological problem. Maintaining the junction quality in superstrate structures with thickness of CdS (d_CdS) <100 nm depends on the uniform interface throughout processing in order to avoid the formation of parallel junctions between CdTe and TCO having a high recombination rate compared to CdS/CdTe junction. For instance, diffusion of indium from an ITO front contact into CdS during post deposition annealing results in loss of V_oc and facilitates direct contact between CdTe and ITO via pinholes in the window layer. The non-conformal layer deposition of CdS and recrystallization during CdCl₂ treatment of the CdS/CdTe stack promotes TCO/CdTe junction formation because of sulfur diffusion into the CdTe or by the island formation of CdS. The sulfur diffusion results in spatially non-uniform consumption of the window layer leading to pinholes. This will be even more significant if the initial CdS layer is further reduced. Thus, an unintentional p–n junction between TCO and CdTe that has a different band alignment is connected in parallel with the CdS–CdTe diode influences the device performance. The interdiffusion results in excess consumption and thinning of the CdS layer affecting the space charge region, which suggests the requirement of a critical CdS thickness to be employed in PV devices.^126–128

Depending on the processing conditions, sodium present in glass substrates diffuses into the active layer resulting in grain growth and GBs widen followed by the shunting of solar cells. Such changes also facilitate the high degree of interdiffusion between CdS and CdTe and favor the junction formation of CdTe or CdTe_1−xS_x with TCO.¹²⁸ The space charge width, and hence cell parameters, decreased with increase in NaF thickness deposited on CdTe prior to the junction activation step (Table 1). The presence of sodium alters the surface energy of both CdS and CdTe and also modifies the GBs.¹²⁸ Sodium serves as shallow acceptor in CdTe with a low activation energy of 59 meV (ref. 129) and increases acceptor density lowering the space charge width.¹³⁰ In contrast, Sites and Pan reported an increase of V_oc with sodium diffusion into the device structure.¹³⁰ The sodium contamination from substrates can be reduced either by using expensive low alkaline borosilicate glass or by the inclusion of a diffusion barrier layer, which however results in increased production cost. By avoiding sodium contamination, excess interface intermixing and recrystallization as well as shunting paths can be prevented and the CdS thickness can be reduced without any adverse effects on the cell parameters. Since solar cells or modules are operated at higher temperature, diffusion of metal via V_Cd states and along tellurium-rich GBs through the absorber layer will be enhanced depending on characteristic diffusion velocity and diffusion mechanism of the metal.^131,132 Even changing the stoichiometry of metal/back contact interface and lowering the contact area will facilitate the degradation. The impurities originating from front/back contact accumulate at the window layer near the space charge region and destabilize the device efficiency.

Table 1 Effect of NaF deposition on CdTe surface prior to junction activation step. Space charge region (SCR) width at room temperature as determined from capacitance measurements (reprinted with permission from ref. 128; copyright @ 2012 Elsevier)

NaF thickness/nm	V oc/mV	FF (%)	J sc/mA cm^−2	η (%)	R p/kΩ cm^2	SCR/μm	E g/eV
0	818	72.5	23.8	14.0	4.5	2.4	1.454
0.75	784	64.5	24.5	12.4	2.6	1.6	1.450
1.5	740	53.3	23.7	9.4	0.8	0.9	1.449
3.0	629	40.0	21.1	5.3	0.3	0.8	1.449
6.0	494	38.8	15.0	2.7	0.2	0.5	1.466
12	508	42.1	12.8	2.6	0.2	0.3	1.468

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The main structural defects in the polycrystalline films are GBs. The presence of GBs affects the semiconductor optical absorption, carrier mobility and lifetime.⁸⁵ The crystal defects and impurities at GBs can induce deep level energy states within the band gap leading to trapped localized charges. These charges create a region depleted of majority charge carriers near the GB, causing an electrostatic potential barrier (band bending) for majority carrier transport with consequent reduction in effective mobility across the junction.¹³³ Thus, the enhanced recombination of charge carriers via localized energy states will be detrimental to photocurrent collection.^27,134,135 The diffusion of elements in solids can be realized by either direct diffusion (direct exchange with adjacent atom) or indirect diffusion (involving point defects). In general, indirect diffusion is favorable with the availability of vacancies in solid matrix. The impurity diffusion in polycrystalline CdTe proceeds via three channels – GBs, interstitial positions (i) and vacancies (v) inside grains. As a consequence, the diffusion of impurities must be characterized by means of three diffusion coefficients – along the GBs, interstitial and vacancies, which follows the order: D_GBs > D_i > D_v. Thus, the GBs with a high density of vacancies facilitate the rapid diffusion process.¹³⁶ It is suggested that grain boundary diffusion is a very likely mechanism for the impurity transport into the device and dopant diffusion coefficient are enhanced at GBs.^127,131 GBs in CdTe have downward bending, while those in CdTe_1−xS_x have upward bending.¹³⁷ The decoration of GBs with tellurium inclusion reduces the band bending effect in CdTe. The boundaries between single crystal grains in polycrystalline CdTe is anticipated to have a strong impact upon the PV performance.¹³⁸ It is expected that a high density of defects exists at GBs (e.g. dangling bonds, dislocations) and that impurities or stoichiometric excess tellurium will segregate to the boundary environment which may benefit the “gettering” of these defects from the grain bulk, improving the grain's crystalline quality.^138,139 Thus, the role of GBs on device performance remains controversial. In any case, GBs give rise to a host of issues including: (i) enhanced migration of dopants;¹⁴⁰ (ii) device shunting; (iii) high recombination velocities due to unpassivated surfaces; (iv) significant current leakage;¹³⁵ (v) a barrier to current transport.¹³⁴ The carrier generated at the vicinity of GBs will have much higher probability of recombination at the boundary compared to those generated closer to the junction.² There are numerous surface/interfaces in the cell with sub-micrometer grain-size having a high concentration of GBs which act as internal interfaces.

The GBs create interdependencies between various parts of the device as they form an interconnected network within the thin film and couple critical components including the back contact, CdTe or CdS grains and various interfaces. These GBs are easily oxidized in the presence of oxygen, which occupies open spaces in the dislocation cores and V_Te sites at GBs forming Cd–O bonds.¹⁴¹ Since the Cd–O bond length is smaller than the Cd–Te bond, sulfur diffusion along the GBs will be suppressed compared to the bulk. The sulfur diffusion depth inside the grains will be much shorter leading to a thinner CdTe_1−xS_x layer compared to the sample grown without the presence of oxygen (Fig. 5). Thus, the presence of sulfur at the back contact primarily arises from grain boundary diffusion.¹⁴¹ In II–VI compounds, GBs can be passivated partially by chemical treatment such as oxidation. The oxidized products like CdO usually exhibit n-type conductivity due to oxygen deficiencies and hence the surface p-absorber grains are converted to n-type conductivity. The carriers generated in the vicinity of the vertical p–n junction will be effectively collected at the junction, which are otherwise lost in recombination pathways.²

Fig. 5 Modes for the sulfur profiles inside grains and along grain boundaries for the CdTe grown (a) without and (b) with the presence of O during growth. The gray scale indicates the relative sulfur concentration in the CdTe side (reprinted with permission from ref. 141; copyright @ 2001 American Institute of Physics).

The passivation of GBs is important in the fabrication of high efficiency thin film CdTe/CdS solar cells. A more economical method for minimizing the diffusion of impurities is to reduce the substrate deposition temperature during device fabrication. The low temperature intrinsically reduces diffusion as the diffusion constant follows Arrhenius characteristics (exponential dependence with temperature).¹²⁸ The stability depends on the spatial changes of defects and impurities from the source materials during the processing conditions. Such impurities can have strong and detrimental effects on the electronic properties of the device, which can be observed in voltage-dependent QE measurements that allow distinguishing effects in different cell layers, especially in CdS by means of spectral resolution.^142,143 However, the magnitude of inhibitory effects by each specific impurity and its minimum acceptable concentration in device efficiency is not extensively investigated so far. Thus, grain size is an important parameter as it determines the grain boundary density and GBs are preferred diffusion pathways for impurity transport in polycrystalline materials. It is therefore important to minimize the impact of grain boundary effects by increasing the grain size for better performance.

3.2.3 Electrical effects. Thin film CdTe/CdS PVs are known to exhibit non ideal effects, which are not observed in single crystal silicon cells. For instance, crystalline cells exhibit “super position” wherein I–V characteristics are identical under illumination and in the dark and are shifted only by a constant current value equal to light-generated I_sc of the device. Thus, dark and light I–V curves never cross each other. In contrast, the nature of p–n junction itself seems to be altered by incident solar illumination causing the light I–V to cross the dark I–V curves at some forward bias voltage. This lack of superposition is often referred to as a “crossover” effect which reduces the device performance.¹⁴⁴ On the other-hand, roll-over also prevails due to the formation of a barrier for electron transport close to the back contact interface opposing the main cell junction.¹⁴⁵ The degradation can also result from a decrease in the diffusion length of charge carriers originating from newly formed recombination centers via diffused impurities. Thus, the presence of deep defects in CdTe captures the photogenerated carriers resulting in a decrease of output current, a loss in V_oc and lowers the cell efficiency. In contrast to the theoretical predictions of 30% efficiency for homojunction CdTe solar cells, it was shown that practical efficiency limit for CdTe/CdS heterojunction cell is 17.5%.⁹⁵

3.3 Optical absorption losses

Though the CdTe/CdS solar cells have demonstrated the highest performance to date, the CdS window layer itself limits the maximum achievable efficiency. The CdTe/CdS heterostructure exhibits a very high spectral response in the wavelength region 500–850 nm with a sharp rise at 850 nm and remains insensitive below 500 nm. Due to its moderate band gap, CdS serves as a filter for high energy photons of the solar spectrum (<500 nm) resulting in absorption loss without contributing to net photocurrent generation. The CdS film thickness of 0.1 μm absorbs 63% of incident radiation with an energy greater than its band gap,¹⁴⁶ while photocurrent loss can reach to an extent of 30.5 mA cm⁻².¹⁴⁷ Thus, generation of charge carriers by energetic photons in the n-CdS layer takes place at the surface far away from the depletion region resulting in a surface recombination current, and consequently reduces useful current delivered by the cell to the load.¹⁰² The efficiencies of solar cells can also be reduced by the optical loss at various interfaces. Before reaching the photoelectrically active CdTe layer, solar radiation must penetrate into the glass plate, TCO and CdS in the superstrate configuration (Fig. 1). Obviously, this is accompanied by optical losses upon reflection from the interfaces like air–glass, glass–TCO, TCO–CdS and CdS–CdTe and absorption in glass plate, TCO and CdS. The reflection loss at the interfaces results in lowering of the I_sc by 9%, whereas absorption in TCO and CdS layers with a typical thickness leads to a loss of 15–16% and 22–24% for SnO₂ and ITO front electrodes respectively. The reflections from the front surface of a glass without anti-reflective coating reduce the I_sc by 3.5%.¹¹⁸ In addition, the integrated device current decreased from 22.02 to 18.32 mA cm⁻² for a 100 nm thick CdS film, while such loss was less pronounced (22.55 to 20.44 mA cm⁻²) for an ultrathin CdS film.⁶² Thus, parasitic optical absorption in the CdS layer results in a predominant photocurrent loss making it necessary to minimize CdS film thickness (<100 nm) to ensure a maximum amount of light is absorbed by the CdTe layer. Maintaining the CdS thickness uniformity at the manufacturing scale requires control over the CdS deposition and CdS–CdTe interdiffusion during the fabrication of both the absorber and window layer. It is also difficult to obtain deposited CdS free from holes and caverns without empty spaces among the grains and with a homogeneous grain size distribution to favor nucleation and particle growth kinetics for CdTe.

The absorption loss in CdS cannot be avoided by reducing the thickness alone since it is related to interband optical transitions. Even at a thickness of 50 nm, a decrease in the I_sc caused by absorption in the CdS layer is 10% and further loss continued when the thickness was doubled.¹¹⁸ However, there is a trade-off between the current gain and voltage as well as FF losses with the reduction of CdS thickness. It is better to use a modified CdS layer with interdiffusion between a special sublayer and CdS or to replace CdS with another wide band-gap semiconductor to avoid optical losses. The non-radiative recombination at several interfaces also contributes to additional optical loss from the cell structure.¹⁴⁸ Considering the portion of CdS reacting with CdTe to form intrinsic layer CdS_1−xTe_x, demand for high quality CdS films acquires even more importance. The tendency to form a CdS_1−yTe_y alloy, absorption in the lower wavelength region and the large lattice mismatch with CdTe provides room to develop an alternate window material that overcomes these problems.

3.4 Fabrication of back ohmic contact and associated drawbacks

3.4.1 Limitation to back contact formation. The major problem associated with p-CdTe is the difficulty to attain low resistance and a stable electrical contact.¹⁴⁹ Since CdTe exhibits exceptionally high electron affinity (χ = 4.5 eV) and high resistivity (10⁴ to 10⁶ Ω cm), there exists no metal with a work function >5.7 eV (W_m) to form an ohmic contact within the simple Anderson junction model¹¹⁷ or to provide a zero Schottky barrier height given by Φ_b = (χ + E_g) − W_m.¹⁵⁰ Fermi level pinning, formed between the absorber and back contact metal layer and E_F − E_VB = 1 eV was found for nearly all metals independent of their work function.¹⁵¹ Thus, contacts to p-CdTe will therefore have a reverse Schottky barrier at the CdTe/metal interface opposing the main p–n junction, which limits hole transport and increases the contact resistance.^117,150 In a circuit model, this barrier will form a diode of opposite polarity to the primary junction, which distorts J–V curves by limiting the total device current at higher voltage, referred to as a “roll over” effect.^145,152 The high work function of CdTe also contributes to strong series resistance.¹⁵³ The limitations for n-type doping into the CdTe matrix are self compensation of intrinsic defects such as V_Cd and p-doping suffers from the lack of available dopants with both high solubility, shallow acceptor levels and tendency to segregate at the GBs.^{101,154−155} The donor and acceptor concentration of CdS and CdTe should be increased by an order of magnitude so as to increase the V_oc and built in voltage respectively. The hole concentration of p-CdTe is in the range of 10¹⁴ to 10¹⁵ cm⁻³ instead of the desired level of 10¹⁶ to 10¹⁷ cm⁻³ resulting in lower junction band bending (diffusion voltage) and difficulty in making ohmic contact, thereby limiting the maximum photovoltage to be expected.¹⁵⁶ It is reported that the potential of a Schottky barrier between 0.4 and 0.45 eV can limit the cell performance.¹⁵⁷ Given that a back contact barrier is inevitable, some consider that a barrier height of <200 meV will be acceptable for device operation. In addition, partial Fermi level pinning at the surface/interface by surface/interface states also complicates the problems in making a low resistance contact.¹⁵⁸

3.4.2 Approaches for stable back contact. Most of the approaches to obtain low-resistance ohmic contacts to CdTe thin films have been directed towards establishing an interface that provides the required electrical properties. Commonly used methods are; (i) use of interlayer contact materials with an electron affinity higher than p-CdTe, such as HgTe and ZnTe;^159,160 or (ii) formation of a heavily doped region at the back surface of CdTe either to reduce the barrier or moderate its width adjacent to the contact to promote tunneling, prior to back contact formation.^161–163 In practice, latter is preferred in order to shift the conduction mechanism from thermionic emission to thermionic-field emission.¹⁶⁴
(a) Chemical etching of CdTe surface. Surface pretreatments are commonly applied to modify the surface defect chemistry of the CdTe layer to facilitate low resistance contact formation.^165–168 Surface chemical etching of CdTe with dilute HCl, Br₂–CH₃OH, K₂Cr₂O₇–H₂SO₄, or a mixture of HNO₃ and H₃PO₄ (NP) in water is made to produce a Te-rich layer, which effectively leads to a p⁺ doped layer resulting in a field at the back surface.^{145,158,169–171} Irrespective of chemical treatment, this etching process converts the near surface region of CdTe film from a stoichiometric to a Te-rich p-type conductive layer. The ΔE_v will be small between the p-CdTe and Te layer (0.26 eV), which facilitates hole transfer from the p-CdTe into Te layer. Thus, band bending will occur at CdTe/Te interface and act as minority-carrier reflector to reduce recombination current on the back surface and at GBs, consequently increasing V_oc. The CL measurements revealed that these etched layers either reduce the electron penetration depth or absorb photons emitted from the underlying CdTe. The K₂Cr₂O₇–H₂SO₄ form an undesirable TeO₂ layer that hinders low-resistance contact formation, while Br₂–CH₃OH treatment causes the penetration of bromine into the entire CdTe thin film and accumulates at the CdS–CdTe interface and front contact.¹⁵⁸ The product CdBr₂ is soluble in both methanol and water, which can be subsequently removed from the surface by agitating, rinsing and leaving behind the Te-rich CdTe. It is reported that a Br₂/ethylene glycol etch (10 s) completely eliminates roll-over, while Br₂/CH₃OH only reduced the degree of roll-over even after long etching (30 s). This difference between etch solutions arose from the solvent viscosity, with ethylene glycol solution being a slower etchant due to its higher viscosity.¹¹⁷ Interestingly, NP etching is preferential to leaving the CdTe surface Te-rich thus increasing the surface conductivity and aiding the formation of tunneling junctions with more reliable contacts.¹⁷² Recently reported HNO₃–CH₃COOH (NA) etching also formed a tellurium layer of <1 nm, with the etching rate being slightly slow compared to NP etching due to the low H⁺ concentration released from CH₃COOH.¹⁷³ This chemical etching is necessary in order to remove any oxidized byproduct and residual CdCl₂ from the CdTe film surface that is normally formed during the junction activation step.¹⁷⁴

As an alternative to chemical etching processes, deposition of a Te layer on the top of CdTe is also studied. A post deposition annealing of Te–CdTe system produces a Te-rich p⁺ layer (band gap of Te layer is 0.33 eV) on the CdTe surface, which reduces the back contact barrier.¹⁷⁵ Niles et al.¹⁷⁶ reported that the minimization of the Schottky barrier close to 0.26 eV could be achieved for a thick Te layer that retains p-type conductivity. In contrast, a thinner Te layer will be dominated by interface states and will be n-type, leading to a higher barrier.¹⁷⁶ Li et al.¹⁵⁸ reported that preferential etching occurs along the GBs of CdTe even at low concentrations of NP, while more NP etching alters significantly the bulk properties of the thin film by exposing GBs and leaving behind a conductive Te-rich layer that forms shunting paths between the back contact and CdS or TCO layers, suppressing the device performance. The etching to produce a Te-rich surface is more effective in minimizing the Schottky barrier if the etching time is slightly prolonged. However, this process will be accompanied by the penetration of a metastable concentration of excess Te (V_Cd) into the subsurface region and can extend into the heterointerface; device shunting problems will be prevalent with overetching.

The Te-rich surface layers are susceptible to the formation of an oxidized product (TeO₂), leading to contact degradation through the formation of a metal/insulator/semiconductor heterostructure.^{123,177–179} The etching time and etch concentration are inversely interdependent; for low etch time, high concentration of etch solution is preferred and vice versa. The use of etching although common on the laboratory scale, cannot be preferred at the manufacturing level. Etching can lead to voids resulting in shunt paths between the crystal grains, if a very thin film absorber layer is employed.¹⁸⁰ These modified etch layers can be removed with KOH/CH₃OH etch.¹⁵⁸ Understanding the nature of CdTe surface prior to, during and after chemical etching process is of vital importance to the successful back contacting process. It is believed that surface orientation, etching process and annealing atmosphere play an important role in the oxidation of the CdTe surface.¹⁸¹ Though etching can remove surface residues, it still fails to remove the traces from GBs.¹⁸² The thickness of the film must be duly considered for the careful control of etch concentration and duration and it is essential to optimize device performance while maintaining the grain boundary integrity.

(b) Deposition with metal. The use of metals as ohmic contacts due to their low resistivity is not desirable because of their diffusing ability in different layers deteriorating the device performance. Ohmic contacts are generally formed by in-diffusion of constituents of contact materials, which results in high doping of semiconductors. As a consequence, the space charge layer associated with the barrier becomes very thin which could be tunneled by charge carriers.¹⁷³ Many metals deposited onto CdTe show significant limitations in device performance due to reaction and formation of metal telluride and elemental cadmium that could be responsible for pinning the Fermi level in CdTe.¹⁸³ The materials used to obtain ohmic contact in superstrate CdTe devices are graphite paste, Te/Au, Sb/Au, Ni, PbTe, SnTe, HgTe, ZnTe, Cu/Au, Cu/graphite, Cu doped ZnTe with metallization and Cu/Mo.^184–196

The most commonly used metal to make a non-rectifying contact with CdTe is Cu. There are various methods to apply Cu at the CdTe back surface; evaporation of thin Cu films onto the CdTe surface; application of graphite paste containing Cu powder/Cu salts or Cu doped alloys; and dipping or spraying the Te-rich surface with Cu salt solutions. An annealing step is required to initiate chemical reaction between Cu and Te to form the desired Cu_2−xTe phase and distribute Cu into the CdTe film.¹⁹⁷ Cu_xTe/CdTe can also be prepared by the deposition of Cu_xTe alloy on the CdTe film.¹⁹⁸ Varying the copper thickness during deposition probably alters both structural and optical properties of the Cu_xTe layer.

3.4.3 Copper back contact: structure, electronic and thermodynamic aspects. It is known that Cu creates acceptor states within CdTe and enhances the device performance at a concentration of 10¹⁹ cm⁻³.^199–201 In addition, Cu doping aligns the Fermi level close to VB and hence produces a low resistance contact. Prior to Cu deposition, chemical etching of CdTe is essential to create a Te-rich surface that reacts with Cu forming Cu_xTe (1 ≤ x ≤ 2).^{165–168,202–204} Thus, ohmic contact is not done directly with Cu, which diffuses into CdTe matrix, but with stable Cu_xTe that is formed on CdTe surface, which increases locally the effective doping level.^110,176 Cu_xTe exhibits p-type characteristics and hence a large number of holes appear in Cu_xTe delivering a better ohmic contact with the CdTe layers. The Cu_xTe films has more than ten polymorphic structures and their optical bandgap lies in the range of 0.5–1.08 eV depending on the value of x.²⁰⁵ Phase transition of the Cu_xTe film can also occur during fabrication depending on the deposition temperature and technique. The Cu_2−xTe phase (x = 0.015–0.026) is expected to be less susceptible to air/humidity oxidation compared to the Te-rich CdTe surface.¹¹⁷ Elemental cadmium was formed at the interface of Cu/CdTe, which was completely absent for Cu_2−xTe/CdTe (Fig. 6).²⁰⁶ The ΔE_v of 0.8 eV and ΔE_c of 0.34 ± 0.05 eV was found for Cu_2−xTe/CdTe interface and the barrier height was reduced to 0.2 eV compared to Cu/CdTe.²⁰⁶ The Cu_xTe with x > 1.4 is not a stable material,²⁰⁷ forcing the free copper to penetrate into the CdTe matrix causing the following drawbacks: (i) it segregates into grain boundaries and forms shunting paths reducing FF and V_oc;²⁰⁸ (ii) it arrives into the CdS–CdTe interface and forms a deep level or p doping in CdS to capture electrons, thereby increasing the resistivity;⁵⁷ (iii) excess Cu can destabilize the device under stress.

Fig. 6 Band diagram for the (a) CdTe/Cu_2−xTe and (b) CdTe/Cu interface as determined by photoelectron spectroscopy (reprinted with permission from ref. 206; copyright @ 2007 Elsevier).

The Fermi energy on the CdS side is close to its CBM and it is close to the VBM on the CdTe side. Hence the formation energy of Cu_Cd⁻ could be lower in n-CdS than in p-CdTe, promoting Cu diffusion from the p-CdTe layer to the n-CdS layer.¹¹⁰ The driving force for Cu diffusion stems from the high affinity of Cu towards chemical bonding with the S of CdS compared to the Te of CdTe, due to the greater chemical stability of Cu–S over Cu–Te.¹¹⁷ This results in the formation of a p⁺-Cu_2−δS phase at the CdS–CdTe interface²⁰⁹ and also forms Cl_S–Cu_Cd complexes and Cu_Cd centers at the expense of Cl_S–V_Cd complexes.¹¹⁷ The band gap of p⁺-Cu_2−δS varies in the range of 1.0–2.3 eV depending on δ, which is typically smaller than the E_g of CdS thus reducing the electrically active photon flux into the absorber layer because of the additional absorption in p⁺-Cu_2−δS leading to more optical losses.²⁰⁹ The Cu diffusion into CdS results in Cu depletion at the back contact, giving rise to the formation of a barrier for current transport. The Cu accumulation in CdS can be detrimental, only if carrier lifetimes in CdS will decrease below the value needed for electronic carrier transport across the film or if high enough to form a conducting Cu–Te shunting path through the device.¹²⁴

In CdTe, Cu exists as an interstitial ion Cu_i⁺ giving rise to shallow donor states of 55 meV (ref. 210), or substituting for Cd atom to form deep acceptor states Cu_Cd⁻ with an activation energy in the range of 0.28–0.34 eV, attributed to its amphoteric behaviour.^211–220 The Cu can also form neutral complexes (Cu_Cd⁻–Cu_i⁺) in CdTe which contains only a small percentage of electrically active Cu atoms in the crystal lattice. Complexes with Cu_i⁺ and V_Cd (Cu_i⁺–V_Cd⁻) are relatively shallow acceptors that stabilize the isolated V_Cd⁻ and other associated complexes.^216–218 The Cu migration in single crystal CdTe and in other II–VI compounds is characterized by a fast (Cu_i⁺) and slow diffusion component (Cu_Cd). Investigations have shown that the interstitial form of Cu is a fast diffuser with a diffusion coefficient as high as 10⁻¹² cm² s⁻¹ at 300 °C.^217,221,222 The CL studies revealed that Cu_Cd and Cu_i⁺–V_Cd⁻ complexes are relatively deep and shallow acceptors, respectively. Both of these states do not co-exist and their distributions are different from each other. The primary diffuser is represented by Cu_i⁺–V_Cd⁻ complexes, since their distribution is progressively uniform and deeper into the CdTe films. The diffusion of these complexes was accompanied by the dissociation of other states with V_Cd. On the other hand, Cu incorporation in the form of Cu_Cd was highly nonuniform and restricted to the back-contact interface. These results suggest that Cu diffusion is limited by Cu incorporation into V_Cd, whereas Cu_i⁺ migration and subsequent complex formation represents most of the electrically active Cu centers in CdTe films in high efficiency solar cells.²²³

The effective thermal diffusion and photodiffusion of Cu in CdTe films are 7.3 × 10⁻⁷ exp(−0.33/kT) and 4.7 × 10⁻⁸ exp(−0.2/kT), respectively, as estimated from resistivity versus duration of thermal or photoannealing in the temperature range of 60–200 °C.²²⁴ The activation energy for Cu photodiffusion (0.20 eV) is less than thermal diffusion (0.33 eV), attributable to the increase of the fast-migrating interstitial flux of photodiffused copper.^225−226 Photoinduced diffusion is detrimental for solar cells because incident light gives rise to an intense electric field which makes the ions mobile within the lattice at relatively low temperature.⁴⁴ The application of an electric field strongly influences Cu electromigration and formation/dissociation of Cu_i⁺–V_Cd/Cu_Cd states affecting the performance by modifying the doping profile and carrier concentration in the absorber layer.²²⁷ The device without Cu may have a different recombination mechanism, but junction recombination follows a Shockley–Read–Hall mechanism, with Cu having a diode factor of 2 suggesting strong midgap recombination.²²⁸ Thus, the high diffusivity of Cu in CdTe and the apparent instability of Cu_2−xTe are responsible for changes in device performance and characteristics upon exposure to light.

Metal (M = Cu or Ag) doped CdTe are susceptible for degradation after aging ascribed to instability of substitutional acceptor states (M_Cd) and formation of complexes (V_Cd–M_i and or M_Cd–M_i).²²⁹ The aging effect was found to accelerate with light soaking. It is possible that copper might accumulate close to CdS/CdTe junction and reduce the depletion layer width or by introducing shunting paths at GBs.²³⁰ The acceleration of cell degradation under illumination during stress is explained by the lowering of the electrostatic potential barrier for the diffusion of positively charged Cu ions crossing the cell junction and therefore enhanced accumulation in CdS,¹¹⁷ which was also supported by SIMS profiling and accelerated lifetime tests.¹¹⁶ The Cu (or Au) serves as an acceptor in CdS and creates a light modulating barrier in CdS CB, which decreases the effective donor concentration by serving as a recombination centre.¹¹⁶ For Au as back contact, Au diffusion in CdTe can be described by the Arrhenius expression D = 4.4 × 10⁻⁷ exp(−0.54 eV)/kT with a relatively low activation energy (0.54 eV).¹³⁶ The diffusion of Au into grains proceeds by the dissociative mechanism – the migrating impurity quickly moves by way of interstitial sites and settles in vacancies. The mechanism of Au diffusion in CdTe takes place in two ways: (i) by fast migration along the GBs; (ii) by relatively slow migration into grains which are characterized by low and high activation energies, respectively.^231,232 Grain boundary diffusion and diffusion into the grain boundary region are observed for the low and high temperature regimes, respectively. The diffusion-doping of Au into CdTe was not influenced by grain size. The weak influence of Au diffusion on the structural properties of CdTe was due to dispersal of Au atoms preferentially on V_Cd owing to the covalent radius proximity of Au and Cd.¹³⁶

Other stress-related changes include the partial conversion of Cu_2−xTe to Cu_xTe with varied copper content that is responsible for the back contact and device degradation.²³³ The high diffusivity of copper was found to be assisted by grain boundaries as well as the polycrystalline nature of CdTe.^{208,217,230,234,235} In general, diffusion along GBs is more facile compared to bulk grains because surface bonds are weaker compared to the bulk due to incomplete coordination. It should be noted that diffusion doping of n-CdTe by Cu will be accompanied by an increase of resistivity, whereas Cu diffusion in p-CdTe lowers the resistivity.²²⁴ Experimental evidence showed that the non-shallow acceptor states defect complex [V_Cd–Cl_Te]^0/− and Cu substitution at Cd sites [Cu_Cd]^0/− play critical roles in the p-doping of CdTe.²³⁶

The stability of solar cells was also influenced by the amount of Cu at the back contact. The cell was susceptible to degradation that tends to stabilize after an estimated time of 4 years for 3 nm Cu, while the cell with <0.5 nm Cu improved its performance slightly (Fig. 7).²³⁷ In addition to Cu and Au, contacts of the commonly used Ag can also diffuse rapidly towards the junction and contribute to device degradation.²³⁸ The degradation was severe under reverse bias compared to forward bias with Cu, while the efficiency of the device without copper increased marginally and remained constant under reverse bias.²²⁴ The larger degradation rate under reverse bias was related to the high electric field intensity applied to the heterojunction compared to forward bias testing. Therefore, excess Cu should be avoided in the back contact to obtain long-term device stability.²³⁹ The diffusion of Cu into the cell structure depends on the junction internal field, which in turn relies on the fact that cell is driven either by an external bias or illumination by one or more suns. Fisher et al.¹¹⁷ reported that the cell (in)stability observed with thermal stress in air or humid conditions cannot always be associated with Cu diffusion or Cu doping into the cell structure. Instead, it was due to the action of atmospheric components on the back-contact interface and/or main cell junction.

Fig. 7 Accelerated lifetime stability tests of ITO/CdTe/CdS/FTO solar cell: before (A) and after annealing at 350 °C (B) and of ITO/Cu/CdTe/CdS/FTO solar cells with 3 nm copper deposition (C) and less than 0.5 nm copper deposition (D) (reprinted with permission from ref. 237; copyright @ 2007 Elsevier).

In general, high performance CdTe solar cells requiring the formation of a low-resistance contact and increased efficiency can be achieved by incorporating an optimal amount of Cu at the back contact.²⁴⁰ A copper-containing back contact requires delicate control of the Cu content, as Cu deficiency leads to non-ohmic behavior, while excess Cu will affect the junction and can cause electrical shunts due to fast diffusion and deep penetration of Cu into the CdTe matrix.²⁴¹ A full understanding of the role of Cu and other possible contact metals for back contact chemistry and their behavior within the device structure is required before optimizing the device performance.

3.4.4 Formation of oxides on the CdTe surface. The junction activation step, carried out in air, is a complex process involving multiple reactions among the CdTe compound and Cd, Te, Cl and O elements. During the process, oxidation occurs invariably at a CdTe surface and residual oxide contributes to R_s, retarding the delivery of Cu at the back contact of CdTe.²⁴² Also, when the CdTe surface is exposed to air prior to metallization, an interfacial layer of native material oxide can also be formed. The main oxidation products are CdTeO₃, CdTeO_3.3, Te₂O₅ and TeO₂, which intensify with gradual increase in temperature and the junction activation step.²⁴³ The formation of CdTeO₃ can also decrease the CdCl₂ flux melting point, suggesting the formation of liquid flux and liquid phase assisted recrystallization of CdTe during the course of annealing (CdTe:CdCl₂:O₂). It is reported that the melting point of CdCl₂ decreases in the mixture of CdTe–CdCl₂–CdTeO₃ with an increase in the molar portion of CdTeO₃.¹⁸² Thus, the surface oxidation of CdTe occurs at a much lower temperature with CdCl₂ layers. The driving force for such oxidation stems from the oxygen diffusion/reaction with the CdTe film.

The CdTe film surface evolves from crystalline to a low-melting glassy mixture of oxides and tellurides with heat treatment in the range of 300–550 °C.²⁴³ The elemental tellurium might arise from the decomposition of CdTe having a higher melting point than the annealed temperature of 450–550 °C, at which slurry mixtures of CdTe and oxides were observed. Such oxidized products were not observed at 450 °C, but prevailed in the samples calcined at 550 °C.²⁴³ The growth of insulating CdTeO₃ between a back electrode and the CdTe surface deforms the I–V characteristics and declines the lifetime of solar cell.²⁴⁴ It is often assumed that the oxide does not form a barrier to charge carrier as it is thin enough to allow tunneling. However, thermionic emission current is affected if the barrier thickness exceeds 20 Ų⁴⁵ because electrons are blocked at the CdTe–oxide interface completely and recombine at the interface states.²⁴⁶ The oxidation process can affect the near-surface chemical equilibrium by removing disproportionate amounts of Cd or Te from the lattice, which complicates the defect vacancy structure in the film. Thus, careful control of oxygen and humidity in the annealing atmosphere is required to avoid the formation of unwanted oxides, which affects the V_Cd concentration within the CdTe film, resulting in poor device performance. CdTeO₃ is the stable thermal oxide of CdTe, which decreases the hole current for the p-CdTe–oxide–metal junction due to the lower tunneling probability with increasing oxide thickness and increase in contact barrier height.²⁴⁷ These surface oxide residues are spatially discrete, located along the GBs and can penetrate deep below the CdTe surface affecting the junction activation step.^242,248

The back contact is considered as a most important source of impurities diffusing into CdTe, CdS and the p–n junction that are responsible for device instability. An improved back contact is required to eliminate micro non-uniformities in the photocurrent response. Long term stability of the back contact may be achieved by using materials that are in thermodynamic equilibrium with CdTe and their metallization. In practice, true ohmic contacts are hard to realize and hence one defines a quasi-ohmic contact, exhibiting a low voltage drop across the metal–semiconductor interfaces, as compared to device voltage drop that may not necessarily be linear with current. The quasi-ohmic contact can be realized via convenient band bending at the metal–semiconductor junction.²⁴⁹

3.5 Interdiffusion between CdTe and CdS

3.5.1 Structure and thermodynamic aspects. The conversion efficiency is generally considered to be influenced by interdiffusion at the CdS–CdTe interface. In p-CdTe/n-CdS heterojunction, there is no energy spike in the CB; however, the interatomic distance and thermal expansion coefficient of CdS are smaller compared to CdTe.²⁵⁰ One cannot fabricate an efficient CdTe/CdS heterojunction because of the large difference in lattice (or thermal) mismatch and different crystallographic structure that are associated with dislocation network at atomically abrupt interfaces, which act as electronic defects to promote the recombination process.^251,252 Theoretical calculations have indicated that carrier generation is highest in the vicinity of the CdS/CdTe junction and declines by two orders of magnitude within the first 1 μm, interfacing with the window layer near the depletion region.²⁵³ The solid solution formed at the n-CdS/p-CdTe interface is a highly compensated resistance material because the compensation in polycrystalline occurs simultaneously at GBs and in the grain bulk.²⁵⁴

During the fabrication and subsequent annealing, interfacial layers are formed via simultaneous interdiffusion of sulfur into CdTe and Te into CdS.^255–257 This interdiffusion was qualitatively in line with the pseudo-binary CdTe–CdS phase diagram but the solubility limits were determined more accurately to be x = 0.03 and y = 0.06 at 415 °C.²⁵⁸ The formation of the CdS_xTe_1−x layer at the interface results in ‘x’ not exceeding 0.06 which represents an equilibrium solubility limit for sulfur in CdTe, although a layer of higher sulfur content might grow under non-equilibrium conditions.^259,260 It is frequently surmised that the sulfur diffusion will prevail due to its smaller atomic radius compared to tellurium, which passivates electrically active GBs and relaxes lattice mismatch between CdTe and CdS to improve device performance.^189,261,262 It is also reported that tellurium alloying with CdS can reduce the I_sc of the device.⁶² However, the degree of sulfur diffusion to passivate defects still remains unclear. Based on near-field scanning optical microscopy, it was concluded that the sulfur composition in CdTe_1−xS_x was non-uniform due to grain boundary assisted diffusion, and sulfur diffuses preferentially along the GBs than in grain bulk. In fact, the grain boundary chemical composition will be rich in sulfur (5.8 atom%) compared to the maximum of 2 atom% found in the grain bulk.^{141,263–265} The amount of sulfur penetrating the bulk of CdTe from the grain boundary must be dictated by the bulk diffusion coefficient of sulfur in CdTe, transport of sulfur through the CdS layer, amount of sulfur available in CdS film and recrystallisation of the CdS layer.^266–268 The extent of CdS consumption establishes a lower limit to thickness of CdS that can be employed while retaining a discrete CdS coating on TCO. Control over the effective CdS thickness obtained after processing is thus critical in achieving high current densities while maintaining the junction properties which govern the V_oc. As discussed earlier, consumption of the CdS layer results in the formation of a CdTe_1−xS_x/TCO junction with inferior performance. Extensive alloying forms a non-uniform CdTe_1−xS_x layer consuming a significant quantity of CdS from the device and the excess interdiffusion may also lead to the dissolution of the heterojunction itself.^137,269

The phase composition and thickness of the interfacial layer in the p–i–n structure depends on preparative conditions like substrate temperature, deposition time and annealing atmosphere, and this interfacial layer plays a decisive role in charge transfer. The CdTe layer can be separated into two groups depending on growth conditions; CdTe grown by CSS or CSVT with a deposition temperature above 500 °C are classified as a high temperature process, while techniques such as ED, HVE and sputtering which operate below 450 °C are low temperature processes. In the latter case, CdTe grows epitaxially on CdS with {111} of CdTe being parallel to the CdS {0001} plane.¹⁰¹ The CdS grain size is conserved across the interface and determines the grain diameter of CdTe, which remains unchanged throughout the absorber layer. The high density of microtwinning on the {111} plane is usually observed as a result of low stacking fault energy in CdTe.¹⁰¹ In contrast, CdTe growth at higher temperature will have a similar grain size compared to CdS at the interface and develops into much larger grains of several micrometers in diameter towards the CdTe top surface. The density of microtwins is smaller compared with low temperature grown CdTe and the orientational relationship between CdTe and CdS is less pronounced.¹⁰¹ The interdiffusion also depends on the growth technique. Electrodeposited films are grown at much lower temperature and the CdTe GBs are expected to be free from sulfur until the junction activation step or post deposition annealing. In addition, sulfur diffusion into the CdTe bulk takes a longer time compared to film growth itself. In contrast, sulfur diffusion along GBs will occur at a much faster rate than the film growth in the CSS technique, leading to thin coating of CdTe_1−xS_x that extends through the complete thickness of the CdTe film (Fig. 8).²⁷⁰ The compositional distribution of CdTe_1−xS_x is independent of CdTe thickness and rapid diffusion takes place near the CdS–CdTe interface.²⁶⁹

Fig. 8 Comparison of rate of bulk and grain boundary diffusion with film growth rate, (5 μm film-Z₀ grown in 5 min at 500 °C) (reprinted with permission from ref. 270; copyright @ 2003 Elsevier).

The interatomic distance in the {111} plane of CdTe is 10% larger compared to the ‘c’ plane of CdS.²⁷¹ It is relatively easy for the ‘c’ plane of the wurtzite structure and the {111} plane of the zinc blende structure to form the heterojunction, hence the preferred quasi-epitaxial growth habit of CdTe on CdS is CdTe {111}//CdS {0001}.^126,272 The polarity of the {0002} layers of CdS is transferred across the interface to the {111} plane of the CdTe layer.¹²⁶ It is evident that chemical bonding of Te at the CdS–CdTe interface is entirely different from that in bulk CdTe. The CdTe grown on CdS {0001} proceeds in a {111} direction at a higher rate compared to {101̄0} where the directional growth is {110}.²⁵¹ The nucleation kinetics of CdTe at elevated temperature are faster on the {0001} plane, which is attributed to adhesion of Te forming a stable surface termination on CdS {0001} but not on {101̄0}. This leads to a preferred {111} orientation of CdTe films deposited on the polycrystalline CdS substrate.²⁵¹ The lattice mismatch is large enough to generate structural defects such as intrinsic stacking faults and misfit dislocations at the interface during CdTe film growth. This introduces interface states (10¹⁴ cm⁻²) at the junction,^273,274 due to the smooth transition of CdS to CdTe through a mixed compound CdS_1−xTe_x, with x varying between 0 and 1.²⁷⁴ Unfortunately, this type of heterojunction possess limited efficiency as this transition occurs through many atomic layers, which inevitably affects the V_oc and FF. The transition must be sufficiently long to diminish interfacial states but need to be short to achieve high electric field.²⁷⁵ The isovalent substitution of sulfur for Te in CdTe/CdS heterojunction can reduce the strain arising from lattice mismatch and cause a reduction of interface states without introducing a defect state within the band gap. Meanwhile, an interstitial sulfur atom in the heterojunction will reduce lattice mismatch between the interface layers and create occupied electronic states at the upper CB.²⁷⁶ Based on DFT studies, it was concluded that an interstitial sulfur atom may induce the inversion of the surface Cd atoms and sublayer Te atoms of the Cd-terminated surface, while sulfur atoms adsorbed at top sites substitute for Te atoms or accumulate at the voids inside the Te-terminated CdTe surface as S_i or S_i1, acting as donors and then becoming impurities during grain growth.²⁷⁶ It is postulated that grain boundary passivation is partly caused by enrichment of GBs in CdTe with CdTe_1−xS_x and partly by Te enrichment that occurs during processing.¹³⁷

Ohata et al.²⁷⁷ have shown that intermixing of CdS and CdTe forms a bicrystal phase for CdTe_1−xS_x (0 < x < 1). The mixed phase has a zinc blende structure for x < 0.2 and a wurtzite structure for x > 0.2 at 700 °C, with a mixture of zinc blende and wurtzite phases between these values and phase transition from zinc blende to wurtzite was observed for x = 0.25 at 1000 °C (Fig. 9).^260,277 In screen printed CdS_xTe_1−x films, a single phase (either zinc blende or wurtzite) was observed for 0 ≤ x ≤ 0.12 and 0.97 ≤ x ≤ 1, while a mixed phase was found for 0.68 ≤ x ≤ 0.97. Irrespective of the initial composition of CdTe and CdS, only CdS_0.12Te_0.88 and CdS_0.95Te_0.05 are formed.²⁷⁸ In general, stable crystallographic forms of interfacial alloys are the zinc blende structure (F43m) for Te-rich CdTe_1−xS_x, and the wurtzite (P6₃mc) for sulfur rich CdS_1−yTe_y, which is in agreement with the CdS–CdTe phase diagram.^279,280 Within these monophasic regions, Vegard's law was followed as reported by other research groups.^259,281 Based on C–V characteristics at frequencies of 10 and 465 kHz, it was proposed that two types of CdTe_1−xS_x with a thickness of 2 × 10⁻³ (for x = 0.21) and 0.54 μm (for x = 0.68) are present with n-type and p-type conductivity, respectively.²⁵⁴

Fig. 9 XRD spectra for CdS_xTe_1−x annealed at 1000 °C, with different compositions of ‘x’ varied from 0.15 to 0.6 (reprinted with permission from ref. 260; copyright @ 1999 Elsevier).

The sulfur diffusion into CdTe is structurally rather than thermodynamically limited within the interface. Rogers et al.⁹⁹ suggested that sulfur diffusion into CdTe occurs in a region delimited by a change in CdTe microstructure, which was apparent in as-deposited cells. Thus, control of sulfur diffusion and intermixing may be achieved through CdTe deposition parameters rather than post deposition thermodynamic treatment. As-deposited CdTe had an in-plane stress of +140 MPa and hence the defect formation is highly probable. The lattice parameter showed a gradual but significant increase from a depth of 1.3 μm below the surface to the CdS–CdTe interface (Fig. 10). Upon calcination, the lattice parameter decreased towards the interface. Thus, in-plane stress is tensile rather than compressive in the case of the as-deposited cell. Such a change in lattice parameter behavior may be reasonably attributed to sulfur diffusion from CdS into CdTe, which is otherwise negligible before calcination.⁹⁹ The interdiffusion at the interface was maximized under the conditions of excess Te, which may be responsible for the displacement of the electrical p–n junction away from the metallurgical interface and into CdTe.²⁸² The sulfur diffusion in the temperature range of 372–675 °C is governed by two mechanisms with activation energies of 1.06 (±0.04) and 1.7 (±0.2) eV.²⁶⁰ Though the nature of diffusion mechanism remains unclear, it was attributed to interstitial and substitutional sulfur diffusion with diffusivities in the range of 1.5 × 10⁻¹⁶ to 7 × 10⁻¹⁴ and 1.4 × 10⁻¹⁷ to 7 × 10⁻¹³ cm² s⁻¹, respectively. In another report, it was observed that the sulfur diffusion into CdTe was insignificant at 397 °C for 30 min annealing, while CdCl₂ anneal (387 °C) revealed substantial diffusion with diffusivity D = 3.2 × 10⁻⁵ exp(−1.2 eV)/kT cm² s⁻¹.²⁸³ Based on Auger electron spectroscopy, sulfur volume diffusion into CdTe was reported to be 4.39 × 10⁻¹⁵, 6.84 × 10⁻¹⁵ and 9.13 × 10⁻¹⁵ cm² s⁻¹ at a temperature of 250, 350 and 400 °C, respectively, with an effective diffusion coefficient of 1.02 × 10⁻¹³ cm² s⁻¹ and E_a of 0.142 eV.²⁸⁴ This activation energy is approximately equal to migration of V_Cd into CdTe (155 meV), indicating that sulfur diffusion at the CdS–CdTe interface is limited by V_Cd migration into the CdTe lattice. The diffusion profile did not indicate any signature of sulfur diffusion along the GBs in this study.²⁸⁴ In the presence of oxygen, both grain boundary and bulk diffusion of sulfur into CdTe will be approximately similar, while grain boundary diffusion predominates in the complete absence of oxygen.⁶²

Fig. 10 Lattice parameter ‘a’ for CdTe measured with depth for the as-deposited (○) and annealed (■) samples (reprinted with permission from ref. 99; copyright @ 1999 Elsevier).

The CdS–CdTe interface is believed to be both a beneficial and limiting factor for solar cell performance, and the growth of the discrete region of intermediate composition during calcination can account for such behaviour. The diffusion process depends on annealing temperature, time, distribution of grains and defect density of the material. The quantification of inter-diffusion between window and absorber layer during the post deposition treatment is important in optimizing the annealing process and understanding device operation. The change in the doping level due to intermixing leads to a change in junction mechanism and space charge width, possibly resulting in reduced efficiency. It was suggested that the rapid sulfur diffusion into CdTe via GBs may cause increased shunting due to reduced band gap, or the formation of a metallurgical alloy in the intermixed region destabilizing the cell efficiency.²⁴¹ The similar grain size between CdS and CdTe can favor efficient intermixing and decrease of interface defects. The important quantities are the energetic and spatial distribution of interface state density and defects as well as the alignment of energy bands and contact potential distribution. While the intrinsic interface states due to lattice mismatch and thermal expansion coefficient cannot be minimized, extrinsic interface states may be eliminated by optimizing the processing conditions.

3.5.2 Effects on optical and electronic properties. The tellurium diffusion into the CdS layer produces a CdS_1−yTe_y ternary compound with a band gap lower than that of CdS, increasing the light absorption in the window layer and thereby diminishing the J_sc of the device. Similarly, diffusion of sulfur into CdTe forms CdTe_1−xS_x, which improves the collection of carriers generated by the long wave photons and extends the spectral domain of photosensitivity. The change in band gap upon sulfur interdiffusion is due to hybridization between S 3p and Te 5p orbitals at the interface. The interfacial values of ‘x’ and ‘y’ correspond to the solubility limits in the CdS–CdTe system at the device processing temperature. An interfacial layer consisting of a CdTe_1−xS_x solid solution graded in composition may act as a graded band gap base. The internal electric field due to the gradient in the band gap is a drag field, which seems to be responsible for the enhanced photosensitivity of the device structure.²⁸⁵ Thus, a gradual change in the hetero-interface structure decreases the tunneling current and optical losses due to the similar changes in index.^284–287

The increase of sulfur content increases the band gap of the ternary compound except for the sulfur concentration below 25%, where the band gap decreases due to the bowing effect, leading to a decrease in the low-energy cut off of the device relative to pure CdTe.^279,288 The bowing effect depressed the band gap of the ternary compound by 0.1 eV lower than the band gap of CdTe with the addition of 30% CdS.¹⁵⁰ The bowing coefficient depends strongly on x. The large bowing coefficient for Cd (S, Te) alloy is attributed to a large lattice mismatch between CdTe and CdS and large differences in the s and p atomic eigenvalues of 1.93 and 1.00 eV, respectively, between sulfur and tellurium.¹¹⁰ The bowing coefficient is larger than the band gap difference of the constituents, indicating the addition of sulfur into CdTe initially reducing the band gap and increasing it thereafter. The total photoresponse remains, however, small because of the low photosensitivity of the solar cell in the spectral domain hν > E_g. The optical band gap follows the relationship:

E_g(x) = 1.74x² − 1.01x + 1.51. (1)

The composition of a solid solution (x) can be determined from its lattice parameter ‘a’, which is intermediate between those of CdS (a = 5.832 Å) and CdTe (a = 6.423 Å) using Vegard's law, assuming E_g is a linear function of ‘a’.²⁸⁵ The sulfur content ‘x’ of an CdTe_1−xS_x film was quantitatively determined from the lattice parameter by assuming Vegard's relationship: x = 1.508(6.481 − a), with ‘a’ being the lattice parameter of the sample.²⁶⁹ Optical measurements also supported the formation of ternary alloys that reduced the photoresponse at shorter wavelength and slightly extended response at longer wavelength.^289–293 These regions are separated by a miscibility gap where both phases exist and optical absorption results from both wurtzite and zinc blende phases.²⁷⁹ This has been explained by the parabolic dependence of the CdS_xTe_1−x band gap upon stoichiometry.²⁷⁷

The interdiffusion between CdS and CdTe was evidenced from PL studies, which exhibit different features depending on the CdTe thickness; for 1.5 μm CdTe, PL spectra showed a deeper shift compared to a device with 1.0 μm CdTe (Fig. 11). Furthermore, the PL spectrum for 1.5 μm CdTe showed a broad and asymmetric peak at 2.019 eV (yellow band) and 1.825 eV (red band), while the 1 μm CdTe cell shows a broad peak in the yellow band. This was due to alloying as a result of interdiffusion, which causes the appearance of new peaks in the PL spectra.²⁹⁴ Duffy et al.²⁹⁵ reported the loss of photoactivity in CdS only for thick CdTe films, whereas CdS was still photoactive when thin layers of CdTe on CdS were annealed. This indicates that interdiffusion does not occur to the same extent in the case of CdTe thin layers on CdS. It follows that the space charge layer extends into the underlying CdS layer in the case of thinner CdTe films, which was not observed for thicker CdTe films. The CdTe_1−xS_x appears to be compositionally homogeneous in the junction region, whereas CdS_1−yTe_y is highly defective and compositionally inhomogeneous. This accounts for photo-inactivity of CdS after heat treatment and junction formation. According to theoretical analysis, if the surface recombination rate at a CdS_1−yTe_y/CdTe_1−xS_x heterojunction is <10⁴ cm s⁻¹, the device efficiency can be improved by moving the p–n junction towards the CdS_1−yTe_y/CdTe_1−xS_x surface. Alternatively, shifting the p–n junction towards the CdTe region would be more preferable for a surface recombination rate of >10⁴ cm s⁻¹, such that it limits the negative role of surface recombination.²⁹⁶ For a low value of applied voltage, the space charge region is near to metallurgical junction where CdTe_1−xS_x is formed, while the space charge region is completely formed in CdTe at higher value of applied voltage (>0.4 V).¹⁰⁸ In addition, capacitance–voltage and current–voltage characteristics also showed that CdS_1−xTe_x formed at heterojunction are inhomogeneous in both conductivity and composition. The current–voltage characteristic in the current density range of 10⁻⁸ to 10⁻⁵ A cm⁻² are governed by the thermal electron emission whereas current in the range of 10⁻⁴ to 10⁻² A cm⁻² is limited by recombination of charge carriers in the electroneutral region of the CdTe_1−xS_x solid solution.²⁵⁴

Fig. 11 PL spectra of CdTe/CdS interface recorded at T = 60 K from the glass side using an Ar ion laser of wavelength 488 nm as excitation source (reprinted with permission from ref. 294; copyright @ 2012 Elsevier).

3.5.3 Challenges to tailor interface structure. Advances in PVs are crucially dependent on a fundamental understanding of the physical–chemical–electronic properties of solar cell materials. The VB and CB curvature due to the difference between the band edge positions of both the absorber and window layer at the junction interface are considered as unique feature of heterostructure affecting the light conversion efficiency and stability. The interfacial layer may consist of discrete or continuous solid solutions and its composition can be controlled, e.g. by varying the deposition time and annealing temperature. Electrically, interface charges facilitate discontinuity in the electric field and can severely affect the band bending. Interface dipoles, which are due to inductive polarization of chemical bonds or due to two sheets of oppositely charged ions, contribute a zero net charge on the scale of observation but induce a discontinuity in the electrostatic potential across the junction.¹⁰⁸

From standpoint of band structure, it would be favorable if the VB of two materials did not include any relative offset that causes an energy spike at the junction. Also, there should be an appreciable built-in voltage at the junction, which can be transformed into useful work under the operating conditions. In addition, proper alignment of energy levels across the phase boundaries must be assured. The band edge alignments are decisive factors and are also objects of interface engineering which need to be optimized with respect to the electronic properties of dissimilar phase boundaries.²⁹⁷ The investigation of heterojunction band discontinuity is important because ΔE_v and ΔE_c determine the transport and confinement properties at the heterojunction.^298−300 Thus, a major challenge is to find a proper alignment of energy bands across the interfaces of the heterostructure.

The combination of lattice mismatched or dissimilar materials cause Fermi level pinning or surface recombination losses, limiting the practical efficiency. Also, important are various interfaces between different layers, as each layer has a different crystallographic structure, morphology, particle size distribution, lattice constant, electron affinity/work function, thermal expansion coefficient, diffusion coefficient, chemical affinity, charge carrier mobility, mechanical adhesion etc. These interfaces results in stress/strain, defect/impurity states, surface/interface/bulk recombination centers, photon reflection/transmission/scattering, impurity diffusion and interdiffusion among the layers, changes in chemical composition and opto-electronic properties influencing the device performance.³⁰¹ The interface properties are modified during device processing as a result of a growth process involving the sequential deposition of multilayers at different deposition conditions. In addition, post deposition involving high temperature annealing in different ambients can also alter interface and intergrain properties. Due to synergy of such complexity, the analysis of device parameters is complicated significantly.

Despite extensive research, composition of the interfacial layer between CdTe and CdS has not yet been fully understood and determined. A resolution of this problem would make it possible to fabricate new devices and enhance the performance of already existing CdTe/CdS devices. A full-scale understanding of the complex parameters controlling heterojunction formation with respect to deposition technique would allow insights into the interfacial electronic band structures and provide valuable information for analyzing device performance and failures at each consecutive stage.

4. Junction activation process: treatment methods and related effects

The photoelectric current in solar cells is influenced by the energetic spectrum of localized states within the band gap. The energetic diagram and physical characteristics of localized levels are determined by the annealing conditions. In order to obtain large grains as well as to improve the device electronic parameters, post-annealing of deposited films is a routine procedure in the device fabrication process. Most of the techniques rely on optimizing the properties of CdTe layer and the CdS–CdTe interface after their deposition with CdCl₂ treatment, commonly referred to as a “junction activation process”.

4.1 Wet and dry CdCl₂ treatment

Irrespective of CdTe layer deposition method, CdCl₂ activation step is standard and vital process in fabricating high efficiency PV devices. During this process, a small amount of solid CdCl₂ may segregate on CdTe surface.³⁰² The most commonly used agent is the hygroscopic salt CdCl₂, which melts at 569 °C and boils at 963 °C with a vapor pressure of 13.3 kPa at 656 °C.^197,303 The CdTe–CdCl₂ phase diagram indicates only sub-atomic percentage solubility of Cl in CdTe at temperature below 525 °C and hence promotes Cl diffusion into the CdTe layer along GBs.^263,304 The CdCl₂ treatment by wet method involves: (i) dipping of CdTe layer in a CdCl₂–CH₃OH or CdCl₂–H₂O solution followed by drying to precipitate the CdCl₂ film;³⁰⁵ (ii) the CdCl₂ layer is deposited on CdTe followed by annealing. Conventionally activation treatment is performed by immersing a thin film in a CdCl₂ solution and heated in air or inert atmosphere at 400–500 °C for a desired interval of time.²⁷⁵ After heat treatment, the sample is washed with water to remove residual CdCl₂.

The presence of oxygen during CdCl₂ treatment results in a low resistance CdTe layer compared to the film prepared in a pure Ar atmosphere, typically with a carrier density in the order of 10¹⁴ to 10¹⁵ cm⁻³.⁴⁴ The annealing in either He–O₂ or in pure He leads to the formation of a surface chlorine residue comprising Cd, Te, Cl and O in the form of oxides and oxychlorides. The XPS analysis revealed that annealing in an inert atmosphere leads to the formation of Cl–Te bonds in the form of tellurium oxychlorides, while thermal treatment in oxidizing ambient results in Cd–O in the form of cadmium oxide along with tellurium oxychloride, which needs to be removed prior to back contact formation.³⁰⁶ It was shown that a solar cell comprising CSS-CdTe heat-treated with CdCl₂ in an He atmosphere had a very similar cell performance compared to those treated in oxygen. This suggests that either the presence of oxygen did not affect the electronic defects, or the concentration of any oxygen-related complexes may be too low for detection using DLTS.³⁰⁷ In another study, DLTS studies revealed two closely spaced defects (0.44 & 0.42 eV below the CB) for air-activated solar cells and a broad band (although not characterized fully, it is located 0.40 eV below CB) for vacuum activated solar cells.³⁰⁸ The annealing of CdCl₂ and CdTe in vacuum does not instigate any chemical reaction.³⁰⁶ In addition, Cl₂ enhances the concentration of Cl²_Te, which is a donor in CdTe and forms an n-type CdTe (S,O) layer at the interface under ambient oxygen.³⁰⁹

Dutta and Krishna³¹⁰ suggested that in situ CdCl₂ treatment results in less surface oxidation compared to an ex situ process, as the latter promotes Te oxidation on the surface and the former gives a relatively oxide-free surface. This means that in situ treatment can provide a chemically clean surface for efficient back contact formation.³¹¹ However, in situ CdCl₂ treatment was effective only at the surface and up to p-type doping, which is restricted to a few layers of CdTe film only.³¹² The advantage of wet CdCl₂ treatment lies in the handling and easy disposal of the rinsate. However, this surface treatment is effective only for small-cell fabrication and fails for large area manufacturing due to a non-uniform distribution of CdCl₂ and processing in a humid environment leading to cell degradation. In addition, residual CdCl₂ may not be eliminated completely by washing, as the formation of water-insoluble oxychlorides can stick to the film.³⁰⁶ As an alternative to the wet method, vapor treatment of CdTe with chloride vapor has been reported to yield better reproducibility and is beneficial for process control as it eliminates the formation of liquid waste associated with the solution method.^313–318 The processing time is reduced since simultaneous deposition and heat treatment is involved, and it eliminates cadmium-containing waste accompanied by the ease of integration in an inline vacuum manufacturing process.¹⁴⁷

In any case, CdCl₂ is believed to act as a fluxing agent that increases the atomic mobility of CdTe or CdS at the annealing temperature. Increasing the temperature above 500 °C, the grain size becomes smaller and pinholes exist causing short or large current leakage in the device. It is likely that CdCl₂ acting as a sintering agent is vaporized at temperatures >490 °C, which is the eutectic temperature between CdCl₂ and CdTe, and thus CdCl₂ treatment may not influence the grain growth.³¹⁹ Annealing of CdCl₂-treated cells removes the TeO₃ while annealing the untreated device enhances the formation of TeO₃. The Cd atoms of CdCl₂ combine preferentially with sulfur or tellurium atoms and substitute for oxide atoms at the CdS surface, indicating that CdCl₂ dissociates the oxide layer effectively (CdO or TeO₃) at the surface of CdS or CdTe film.³²⁰ A clear knowledge of annealing temperature is necessary to dissolve completely the oxidation on the CdTe and CdS surface. For instance, the relative percentage of TeO₃ was 11, 18, 2 and 9% for as-grown samples annealed at 345, 390 and 420 °C, respectively. Thus, TeO₃ almost disappear and a CdTe surface containing only Cd–Te bonds was present for the samples annealed at 390 °C.³²⁰

4.2 Beneficial effects of junction activation step

The beneficial effects of CdCl₂ treatment are well known in terms of several aspects such as: the change in the surface morphology of the film; the formation of crevices at GBs; recrystallization; reduced optical loss; strain recovery; grain growth and grain coalescence; interdiffusion enhanced leading to the formation of a CdTe_xS_1−x/CdS_yTe_1−y interface, where x and y are less than or equal to the solubility limit at about 400 °C (x ∼ 0.03 and y ∼ 0.06); minimum non-uniformity of sulfur distribution at the interface; enhanced p-type conductivity of CdTe; passivation of interface defects (Fig. 12); reduction in planar (and lattice) defects and porosity at GBs; removal of interstitial Te or V_Cd; reduction of the density of deep levels in the band gap; randomization of the CdTe film orientation; change in the concentration and distribution of trapping states in CdTe; increased hole depletion near the GBs resulting in enhanced charge separation; decrease of leakage current caused by tunneling; and interface recombination accompanied by increased carrier collection.^{36,44,45,117,126,150,197,275,321–350} CL revealed that CdCl₂ treatment results in passivation or outdiffusion of Cd interstitials.³⁵¹ Surface photovoltage spectral studies showed that an increase in effective carrier generation length and an improvement in junction quality due to decrease in the density of grain boundary states throughout the CdTe bulk and depletion region after CdCl₂ treatment as compared to only air annealed samples.³⁵² The CdCl₂ acts as a flux, facilitating a solid solution formation between different Cd (or Zn) chalcogenides.^353,354 The CdCl₂ treatment is also reported to invert the GBs due to the formation of Cl_Te donor surface defects as a result of Cl segregation at GBs compared to grain bulk.^263,355,356 These defects will lead to inversion of GBs if Cl concentration is high enough such that is not neutralized by O_Te acceptors.³⁵⁷ The mechanism by which chlorine promotes structural changes in CdTe and CdS is most likely by the formation of CdO and TeCl₂ at GBs.³⁵⁵

Fig. 12 Band energy diagram of the CdS–CdTe interface prepared by physical vapor deposition before activation (left) and after activation (right) (reprinted with permission from ref. 328; copyright @ 2005 Wiley Interscience).

4.2.1 Grain growth and solid state defect mechanism. The as-deposited CdTe layer contains submicrometer sized, {111} oriented, columnar grains with high density of stacking faults and microtwins resulting in a poor electrical p–n junction. During the activation process, CdTe will be subjected to grain growth, recovery and recrystallization processes. The presence of Cl enhances the recrystallization of the CdTe layer starting from its surface, while recovery of the CdTe layer takes place at the interface via reduction of microtwins. The simultaneous occurrence of recrystallisation and recovery results in a preferred alignment of GBs in CdTe parallel to the interface.¹²⁶ Recrystallisation constitutes the nucleation and growth of new lattice with a low strain energy at the expense of the original lattice accompanied by the grain growth. The driving force for this process stems from the high strain energy present in the original lattice.³⁴³ During the first minute of annealing under Cl influence, grain growth is the dominant mechanism driven by the difference in density of the structural defects and the high grain boundary energy. The continuous annealing results in recovery of CdTe microstructure close to the interface while a volume closer to the CdTe surface shows recrystallisation driven by a high density of twins.¹²⁶ The increase of grain size is mainly attributed to CdCl₂ providing a crystallization seed for CdTe during annealing and also for the reduction of an atomic diffusion barrier at the grain boundaries.^358–361

CdCl₂ (solid) + O₂ (gas) + CdTe (solid)⇔ TeCl₂ (g) + 2CdO (solid) (2)

The presence of TeCl₂ vapor would increase the surface mobility of both Cd and Te and hence promote CdTe recrystallization.

Polycrystalline films inherently show non-uniform stress in the film but a uniform stress value after in situ CdCl₂ treatment.³¹⁰ It should be noted that air-annealed CdTe film does not show any significant grain growth and is likely that the presence of CdCl₂ during annealing induces a sintering mechanism within the CdTe film that acts to decrease the intergrain pore size and increase the average grain size.²⁹³ Thus, the combined effect of improvement in microstructure, layer interdiffusion and electronic properties with a junction activation step improves the device efficiency. However, excess CdCl₂ can also enhance the surface oxidation (TeO₂) and roughness of the film.²⁸³

The junction activation step may or may not induce recrystallization of CdTe depending on the initial stress of the material and nature of the deposited layers.³⁶² The CdTe films deposited by CSS do not undergo recrystallisation upon annealing with CdCl₂,^363–365 but reduce the structural defects and affect the GBs, resulting in higher effective acceptor concentration.¹⁰¹ The grain growth for smaller CdTe grains after CdCl₂ treatment will be assisted by the fluxing agent of CdCl₂ and strain present in the small grains. The small grains are easy to reorient and coalescence occurs leading to drastic grain growth. However, for a densely packed larger grain size having a low concentration of defects and low stress state,^363–365 the junction activation step may not produce sufficient energy to reorient the grains.²⁴³ Interestingly, CdTe deposited at low temperature via a CSS and radio frequency magnetron sputtering method experienced identical physical changes with the activation step.³⁴³ The CdCl₂ treatment did not influence the grain size of CdTe obtained via a nonvacuum chemical molecular beam deposition method (CMBD) but a significant impact on the mobility and carrier concentration was observed.³⁶⁶ Thus, grain growth of CdTe after activation depends on the initial grain size of CdTe; the smaller the grain size, the more significant is the grain growth. It is proposed that chlorine would increase stress in grain boundary regions where the recrystallisation process is likely to start during the heat treatment.³⁴³ Only those species arriving or attaching to the surface near the grain boundary take part in the grain growth process.³²⁴ In particular, the grain boundary region becomes heavily p-doped due to preferred grain boundary diffusion and segregation of chlorine and oxygen.⁴⁵ The diffusion coefficient of Cl in CdTe for GBs is known to be five orders of magnitude larger compared to bulk CdTe.¹²⁶ Hence, samples with high grain boundary length per unit area are most likely to exhibit rapid grain growth.³²⁴ During activation, small CdTe grains are transformed directly into the vapor phase and recrystallize to a better organized CdTe matrix:^95,257

CdTe_(s) + CdCl_2(s) ⇒ Cd_(g) + Te_(g) + Cl_2(g) ⇒ CdTe_(s) + CdCl_2(s) (3)

The presence of Cl₂ favors the CdTe crystalline growth by means of local vapor phase transport. In this way, small grains disappear and the CdS–CdTe interface is effectively reorganized. The grain growth of CdS during excess CdCl₂ treatment may introduce stress at the TCO–CdS interface, resulting in the loss of adhesion between two layers or lead to film blistering or peeling.

After treating CBD-CdS with CdCl₂, the following defect reactions arise:³⁶⁷

V_S (in CdS) + CdCl₂ → Cd_Cd + 2Cl_S (4)

The other possibility is that CdCl₂ incorporation generates V_Cd and Cl_S in CdS:

CdCl₂ → V_Cd + 2Cl_S (5)

The out-diffusion of Cd from CdS to CdTe takes place because CdTe is Cd deficient, causing V_Cd at the CdS surface:

CdS + V_Cd (in CdTe) → V_Cd (in CdS) + CdTe (6)

CdCl₂ treatment may introduce Cl-rich precipitates into CdTe but their influence on the device performance is not known. The chlorine-rich residue surface will be chemically and thermally stable and thus etching with HNO₃ is generally required to obtain a chlorine free surface.³⁶⁸

Castaldini et al. have enumerated 12 defect trap levels for Cl dopants in CdTe and have shown the importance of A centers [V_Cd–Cl_Te] and mid-gap traps.³⁶⁹ Valdna et al.³⁷⁰ have shown that (Te_i²⁻–Cl_Te⁺)⁻ and or (V_Cd^2––Cl_Te⁺)⁻ shallow acceptor complexes stabilize the high p-type conductivity of CdTe films. The CdTe treated with CdCl₂ introduces three defects; V_Cd, Cl_Te and their defect complex V_CdCl_Te.³⁶⁷ During the annealing of CdTe with CdCl₂, it is possible that one CdCl₂ molecule can generate one V_Cd and two Cl atoms in Te sites (Cl_Te). The diffusion length (L) of minority carriers was same (0.31 μm) for both untreated and CdCl₂ treated cells. This means that L is not affected by the grain size and is probably given by the carrier lifetime in the grain bulk. The value of L might be limited by a deep level in the band gap of CdTe.⁷⁷

4.2.2 Effects on optical and electrical properties. In many cases, the junction activation step causes significant structural changes that are coupled to the electronic properties of deposited layers. Annealing with chlorides changes the electronic structure of the heterojunction via formation of additional energy levels by S, Cd and Cl, while thermal annealing leads to atomic rearrangement in the structure, and Cl together with V_Cd forms [V_Cd²⁻–Cl_Te⁺]⁻ and [V_Cd⁻–Cl_Te⁺]⁰ acceptor centers.³⁷¹ The band gap was found to be 1.55, 1.54 and 1.52 eV for as-grown, annealed and CdCl₂ treated CdTe layers, respectively.³⁴⁵ The observed trend at the absorption edge towards lower photon energies for heat treated layers could be attributed to a change in grain size and stoichiometry due to the loss of Cd resulting in the formation of shallow acceptor levels.^341,372,373 The shift of anodic Fermi level towards CB as well as cathodic towards VB is observed after CdCl₂ treatment.^310,330 A shift of 200 meV in the Fermi energy towards VB after in situ CdCl₂ treatment and a shift of 100 meV in the Fermi level position for an ex situ CdCl₂ treated CdTe thin film is observed in VB XPS spectra. The shift in Fermi level is restricted near to the surface in the ex situ process while it may be throughout the complete CdTe layer for an in situ process.³¹⁰

The improvement in p-type conductivity of CdTe and electrical properties during the junction activation step is attributed to complex interaction between CdCl₂, impurities and sulfur interdiffusion. From a theoretical point of view, chlorine is predicted to promote further p-type doping of CdTe via a V_Cd–Cl_Te complex with an ionization energy of 30 meV below that of V_Cd.³⁵¹ Hence, chloride diffusion into grains and within a border region of larger grains during the CdCl₂ treatment promotes p-type conversion of CdTe layers. The as-deposited CdTe film is p-type with a resistivity of 10⁴ to 10⁵ Ω cm originating from native stoichiometric defects like V_Cd, which drops to 7–100 Ω cm after CdCl₂ treatment.^374,375 The low concentration of chlorine (10¹⁶ to 10¹⁸ atom cm⁻³) leads to low resistance p-type conductivity, while a semi-insulating property was observed for a higher concentration of Cl (>10¹⁹ atom cm⁻³) in a CdTe lattice.^370,376 It is also reported that photoconductivity of the n-CdS (and p-CdTe) film increased when heated in CdCl₂ solution, due to the generation of non-equilibrium charge carriers from the non-ionized acceptor levels positioned at 0.07 eV higher than the VB top.³⁷⁷ In addition, the current transport mechanism switches from tunneling/interface recombination to recombination in the depletion region (thermal emission) attributed to the elimination of electrically active interface states by a mechanism that is not possible by simple annealing, as revealed by both temperature dependent J–V characteristics and spectral response measurements under reverse bias.^352,375 This change in current transport mechanism was found to be associated with: (i) an increase in heterojunction barrier height; (ii) a decrease in dark leakage current; (iii) an increase in cell V_oc.³⁵² Some authors ascribe the effect at least partly to the reduction in the volume fraction of material influenced by GBs due to grain growth.¹⁷² DLTS measurements showed that depletion region recombination probably occurs through a large density of deep states at E_v + 0.64 eV arising from a (V_Cd–Cl)⁻ defect complex as a result of interaction between V_Cd introduced by heat treatment and chlorine from CdCl₂.³⁵² These deep acceptor traps, though important factors for diode current transport, will have a non homogeneous distribution inside the CdTe layer which is detrimental to V_oc.^352,378

During the fabrication of a cell, the junction activation step “dominantes” over the back contact fabrication, as the former exerts significant impact on the surface composition and chemical nature of the interfaces.³⁷⁹ The thickness of CdCl₂ plays a major role; if the layer is too thin, the effect of CdCl₂ will not be apparent and an optimal V_oc is difficult to obtain for a very thick CdCl₂ layer.¹⁸⁹ The CdCl₂ treatment decreases the resistivity of stoichiometric CdTe (1 : 1 of Cd–Te) film owing to an increase in the carrier concentration from 2.3 × 10⁷ to 4.7 × 10¹² cm⁻³. This is because oxygen occupies tellurium vacancy V_Te²⁺ and as a result the donor level (E_c −0.48 eV) passivates and acceptor level (E_v +0.15 eV) activates. The resistivity as well as carrier concentration does not change much for Cd-rich and Te-rich CdTe obtained by CMBD, indicating that the junction activation step may not be necessary for CdTe obtained by this novel method.³⁶⁶

Junction degradation was investigated using a CdTe layer with a high concentration of V_Cd.³⁶⁷ In the PL spectra, as-deposited CdTe exhibits a sharp peak at 1.59 eV, a broad band at 1.44 eV and a satellite peak at 1.57 eV. The peak at 1.44 eV corresponded to electronic transition from the CB edge to V_Cd and its broadness indicates that the distribution of a deep energy level by V_Cd is not well-defined. The peak at 1.59 eV is a bound exciton transition peak which is slightly lower than the band gap of CdTe (1.61 eV at 10 K) and the peak at 1.57 eV is a satellite bound-exciton transition peak due to phonon scattering.^227,380 Upon treatment with CdCl₂, the peak at 1.44 eV is shifted by 5 meV (1.435 eV) due to structural relaxation with CdCl₂ treatment, and a new signal at 1.455 eV was attributed to the transition from CB to a V_Cd–Cl_Te defect. After treating with a Cu₂Te back contact, a new peak at 1.52 eV was observed due to defects caused by Cu atoms in the Cd site (Cu_Cd), which shifted to 1.53 eV because of Cu_CdCl_Te defect formation.³⁶⁷ The junction activation step resulted in the modification of the energy diagram in the recombination levels. For an untreated cell structure SnO₂/CdS/CdTe/Ni, two types of recombination levels with lifetimes τ₁ = 16 μs and τ₂ = 30 μs were observed at 80 K.³⁷⁷ The recombination levels with τ₁ characteristic time are stable in the whole temperature range, but decrease weakly at 200 K reaching a value of 12 μs. However, τ₂ reaches a maximum of 50 μs at 140 K and decreases to 25 μs at 300 K (Fig. 13). For treated cells (heated in CdCl₂), τ₃ (13 μs) at ≤140 K decreases to 5 μs at 200 K due to the shift of quasi Fermi level that transforms the two hole capture levels into recombination levels. The τ₄ reaches a maximum of 37 μs at ∼260 K followed by sudden decrease thereafter, and τ₅ remains active for temperatures ≥210 K reaching 180 μs at 300 K, accounting for the high photoconductivity of the devivce.³⁷⁷ The junction activation for CdTe/CdS/SnO₂/ITO/glass indicates a diffusion process at two interfaces: (i) interdiffusion of CdS and CdTe at the CdS–CdTe interface; (ii) 5% Cd diffusion into entire SnO₂ layer.³⁸¹ The diffusion of Cd into the SnO₂ layer reduced the band gap of SnO₂. The ΔE_v of 0.7 and 2.0 eV was found for activated CdS–SnO₂ and CdTe–SnO₂ interfaces, respectively. The activation resulted in a Fermi level shift in both CdS and CdTe by 0.2 eV towards the CB. It is important to note that such changes in doping of CdS and CdTe were not observed when they were deposited separately from each other into an SnO₂ electrode. Hence, interdiffusion of CdTe and CdS must be responsible for the observed change in electronic properties. In addition, CdCl₂ treatment changed the surface morphology of the CdTe layer while SnO₂ and CdS films were almost unaffected.³⁸¹

Fig. 13 The lifetime of the non-equilibrium charge carriers in the temperature interval from 80–300 K. Energy levels active in the un-annealed CdTe films; curves 1 and 2. Recombination levels active in the presence of CdCl₂ structure; curves 3, 4 and 5 (reprinted with permission from ref. 377; copyright @ 2005 Elsevier).

4.2.3 Effects on interfacial structure. As pointed in a previous section, intermixing of CdS and CdTe during the activation step turns the abrupt junction into a linearly graded one, while simultaneously inducing pin-holes.³⁸² The dimensions of the intermixed region depend on several parameters involving CdCl₂ treatment. The diffusion coefficient of Cl in CdTe is small; 7.6 × 10⁻¹⁴ cm² s⁻¹ at 400 °C,³⁷⁶ which yields an ‘L’ of 120 nm for a 30 min anneal. If the penetration of Cl into grains is small, migration through GBs could be much faster. In this way, Cl atoms could reach the CdS–CdTe interface and become incorporated as donors in the intermixed alloy region. This results in enhanced n-type conductivity on the side of the junction leading to n/p transition with lower diode saturation current.¹⁵⁴ Niles and Hasoon³⁸³ found a thin CdCl₂ layer prevents the loss of sulfur during the CdS treatment. The heterointerface without CdCl₂ treatment shows compressive microstress varying from −98 to −158 MPa near the surface. Interestingly, CdCl₂ spray during CdTe deposition showed −19 MPa near the surface and CdCl₂ spray prior to CdTe deposition exhibited a tensile stress of +20 to +40 MPa. The recrystallization of CdTe causes partial sulfur diffusion when CdCl₂ is introduced during CdTe deposition, while sulfur diffuses uniformly from the interface to the entire CdTe film for CdCl₂ treatment prior to CdTe deposition.³¹⁰ The CdCl₂ treatment induces sulfur atoms to migrate from the CdS layer towards the back contact, but no sulfur atoms could reach the back surface. Instead, they were found as S–Cd bonds (as in CdS or Cd(S, Te) environment) and some in oxidized form.³⁷⁹

In the as-deposited film, diffusion of sulfur into CdTe is very significant compared to Te diffusion into CdS.³⁸⁴ The interface width increased from 0.24 to 0.36 μm after annealing at 380 °C, followed by the shift of the metallurgical junction peak towards the CdTe side. There was a progressive loss of sulfur from CdS and an increase in Te concentration at the surface that influenced each other. With further annealing at 400 °C, width increases to 0.48 μm with significant loss of sulfur leaving a Cd rich surface (Fig. 14). The significant loss of sulfur at 400 °C was due to both diffusion and sublimation, indicating that the degradation of the heterojunction and the influx of Te was not sufficient to occupy all V_S sites. The net effect after annealing decreased the concentration of anions. The change in sulfur concentration exhibits two distinct features: a broad region corresponding to the fast diffusion across the interface and into the CdTe film, while a slow diffusion was found to be independent of temperature. The increase of interface width because of CdTe_xS_1−x alloy formation was supported by XRD analysis, where the diffraction peaks shifted towards higher angles (Fig. 15).³⁸⁴

Fig. 14 Auger depth profile of CdTe/CdS device fabricated under different annealing conditions (reprinted with permission from ref. 384; copyright @ 2007 Elsevier).

Fig. 15 Graphs showing the shift of the characteristic peaks of CdTe due to the formation of the alloy CdTe_1−xS_x. (A) (511)/(333) peak and (B) the (220) peak (reprinted with permission from ref. 384; copyright @ 2007 Elsevier).

4.2.4 Effects on impurity diffusion. Semiconductor processing relies on the ability to control impurities that are usually present in devices at higher concentrations compared to the initial precursor used. The structure–electronic nature of the interface during junction activation step determines the quality of heterojunction as well as the PV efficiency. Recent investigations showed that CdCl₂ treatment affects the interior of CdTe grains via potential incorporation of electrically active impurities.³⁸⁵ The segregation of CdCl₂ at GBs provides impurities, which are more conductive than grain bulk and passivate the GBs.^262,386 Impurities such as Cl, Na, In and Sb increased after CdCl₂ treatment in CdTe/CdS/In₂O₃:F/glass structure, suggesting that these impurities are likely to be present in CdCl₂ itself (Fig. 16). The In and Na may also originate from TCO and the glass substrate respectively. On the other hand, O, Cu, Zn, Sn and Pb had the same concentration and distribution before and after treatment, indicating that they did not originate from CdCl₂. The diffusion of silicon also occurs from the glass substrate during CdCl₂ processing.³⁸⁷ In another study, Pb, Sn, Zn, Sb and Cu had invariant levels, when CdTe was deposited with 5 N and 7 N purity. Meanwhile impurities like Cl, O, Na and Si showed higher levels for the device grown using 5 N CdTe compared to 7 N CdTe, indicating that these impurities are likely to originate from CdTe starting materials. More importantly, In, Si, Pb, Zn and Sn depth profiles suggests that CdS–CdTe interface is slightly graded due to better interdiffusion of sulfur and tellurium when 5 N purity is used compared to 7 N. However, sulfur and tellurium profiles showed that this interface has the same shape regardless of material source or purity.³⁸⁸ Metallic copper was found when back contact formation of Cu/Au was performed in air, but was completely absent with CdCl₂ treatment due to enhanced diffusion of Cu into the CdTe film.³⁷⁹

Fig. 16 Species that are present in the CdCl₂ starting material: quantitative SIMS depth profiles of In, Cl, Na and Sb impurity atoms for the CdTe/CdS/In₂O₃:F/glass structures without (a) and with CdCl₂ treatment (b) (reprinted with permission from ref. 387; copyright @ 2005 Elsevier).

The relative concentration of several isotopes, as revealed by SIMS analysis, followed the order: ¹⁶O > ³⁵Cl > ¹²C > ³⁴S through the main body of the CdTe matrix.¹²⁷ It is known that CdTe has a propensity for self compensation and hence effective dopant concentration may be an order of magnitude lower than the total concentration of impurities. SIMS analysis of solar cell after the removal of glass substrate showed an increased concentration of Cl, Na and Sb impurities in CdS after CdCl₂ treatment, while Pb, O, Sn and Cu conserve the same concentration. Furthermore, Zn, Si and In had a slightly lower concentration after CdCl₂ treatment. Sodium was concentrated at the CdS–CdTe and TCO–CdS interfaces, while the peak concentration shifted to the CdS layer during processing conditions.³⁸⁹ During CdCl₂ treatment at 400 °C, there is a possibility of formation of compounds such as ZnCl₂, InCl₃ and SiCl₄. The SiCl₄ is gaseous at this temperature, while ZnCl₂ and InCl₃ have a high vapor pressure compared to CdCl₂. This is the most likely explanation for the observed decrease in Zn, Si and In concentration after CdCl₂ treatment.³⁸⁹ In addition, CBD-CdS also revealed a high concentration of carbonaceous species in the cell matrix. The presence of carbon would have adverse effect on chloride diffusion and associated recrystallisation of CdTe.¹²⁷ Alkali metals are mobile, with small activation energies below 1 eV for diffusion in CdTe.³⁹⁰ Thus, care is necessary to avoid sodium concentration, which can diffuse from the glass substrate as contamination during the activation step. Boyle et al.¹²⁷ found that cell efficiency was in the range of 6.9–7.8% despite the presence of several impurities from CBD-CdS; no correlation between performance and impurity distribution could be found. This result further strengthens the use of polycrystalline thin films for solar cell applications at lower costs by utilizing lower grade source materials. Emziane et al.³⁹¹ reported that nearly 83–91% of impurities present in the CdCl₂ precursor serve as potential dopants in CdTe. The electrically active impurities in CdTe are generally considered to be IA (Li, Na, K), IIIB (Al, Ga, In, Tl), VB (N, P, As, Sb), VIIB (F, Cl, Br, I), and IB (Cu, Ag, Au) elements in periodic table. The behavior of I A and I B elements is complicated because of their smaller atomic or ionic radii with high diffusivity and hence might leave the lattice position to serve as interstitial donors. The possible relationship between impurity profiles, solar cell efficiency and stability together with reproducibility needs to be further investigated.

4.2.5 Junction activation with Freon gas (HCF₂Cl). The conventional wet/dry CdCl₂ treatment has few drawbacks from the view point of manufacturing process: (i) CdCl₂ has quite a low evaporation temperature (500 °C in air); (ii) it cannot be stored in large quantities as it could be dangerous in case of fire and Cd release into the environment; (iii) CdCl₂ is soluble in water and several measures must be taken to prevent environmental pollution and damage to health; (iv) etching processes used to remove residual CdCl₂ face the additional problem of the disposal of etchants.³⁰² Alternatively, non-toxic HCF₂Cl can be used, which eliminates the step of CdCl₂ evaporation and subsequent surface chemical etching via vacuum annealing, making the device more suitable for industrial production. Another advantage of HCF₂Cl treatment is the absence of CdCl₂ residue on the CdTe surface.³⁶¹ Polarized Raman spectroscopy revealed that HCF₂Cl treatment provides a clean surface and also serves as potent etcher by smoothing the film surface and makes it Te-rich, facilitating good ohmic contact on CdTe.³⁶¹ During heat treatment, HCF₂Cl decomposes and CdTe starts to evaporate:

CdTe_(s) + 2Cl_2(g) → CdCl_2(s) + TeCl_2(g) → CdTe_(s) + 2Cl_2(g) (7)

This reaction favors CdTe film recrystallization and increases its crystalline quality. After heat treatment, the sample is kept under high vacuum in order to re-evaporate CdCl₂, which could be deposited on the CdTe surface. Both HCF₂Cl and CdCl₂ treatment showed a similar grain growth mechanism, but with a different impact on GBs; treatment with Freon gas leads to compact structures with reduced GBs, while CdCl₂-treated layers exhibit wider and more pronounced boundaries. Freon gas treatment may not relax compressive stress generated by lattice and thermal mismatch between CdTe and CdS as they do not diffuse much through the GBs.³⁶¹

The device glass/ITO/ZnO/CdS/CdTe/Cu–Mo activated with a mixture of HCF₂Cl and other gases exhibit an efficiency in the range of 14.0–14.6% and this remains unchanged even after the first month of its manufactured lifetime.³⁹² In this study, CdS was treated in an oxygen atmosphere before CdTe deposition, which suppressed the interdiffusion and resulted in better control over the formation of intermixed CdS_xTe_1−x near the junction. The decrease of reverse current was observed after annealing in HCF₂Cl gas.³⁹³ The efficiency of this cell was found to vary with the partial pressure of HCF₂Cl and the cell structure treated at 40 mbar exhibited a 14.8% efficiency. The diode factor of 1.8 was observed for untreated cells, indicating that recombination currents dominate the junction transport mechanism due to a high density of interface defects. The diode factor reduces to 1.2 for HCF₂Cl (40 mbar partial pressure) treated cells suggesting decrease in the density of interface recombination centers. The cell treated with 50 mbar showed again a sharp behavior by increasing the diode factor to 1.8 as a consequence of junction degradation. The activation energy for the impurity diffusion decreases by increasing the HCF₂Cl partial pressure due to the enlargement of band formed by [V_Cd–Cl_Te] complexes.^302,394 CL studies revealed that some Cl (or F) impurities are incorporated inside CdTe grains, where a high V_Cd concentration could favor the formation of a (V_Cd–Cl_Te) complex.³⁰² The only drawback in using HCF₂Cl, which is an ozone depleting agent, but this can be recovered and reused in a closed loop during industrial production. The activation process with Freon gas is not universal, and it depends on the fabrication process of CdS (or CdTe) thin films. Despite extensive study, the change in fundamental material properties induced by the junction activation step leading to improvement in device performance is far from being understood.

5. Properties of CdCl₂-activated and heat-treated CdTe/CdS solar cells

5.1 Changes in textural properties

The CdTe deposited on a glass substrate via CSS at low temperature (340 °C) showed preferential orientation along the {111} direction, while high-temperature (520 °C) processed CdTe preferred {400} crystal plane nucleation. After activation with CdCl₂, the strong {111} texture of low temperature CdTe converts to a {400} texture, similar to the non-activated sample.³⁹⁵ In another study, a {311} plane orientation was observed for the as-grown films, while heat/CdCl₂ treatment resulted in the orientation of {111} at the expense of the {311} plane, indicating a recrystallization from a nearly random grain orientation to a pronounced {111} texture.^100,382 Samantilleke et al.³⁹⁶ reported that as-deposited CdTe wurtzite film showed a marked improvement in {002} reflection after annealing in air followed by CdCl₂ treatment and disappearance of Te diffraction peaks (Fig. 17). At 150 and 300 °C, CdTe grown on HVE-CdS layers exhibit a {111} orientation before and after CdCl₂ treatment. On the other hand, CdTe grown on CBD-CdS preferred a {111} orientation at 150 °C, while {111}, {311} and {422} orientations were observed at 300 °C.³⁹⁷ The creation of new grains due to disintegration of some large grains was a consequence of the relaxation of excessive strain in the lattice. The coalescence of small grains into larger ones is caused by CdCl₂ sintering flux with annealing at high temperature. Because of the composite nature of CdTe layers, XRD peaks corresponding to crystallographic planes of as-deposited CdTe grains and regenerated grains will be observed.³⁹⁷

Fig. 17 XRD patterns of CdTe for as deposited (a), annealed in air for (b) 3 h and (c) 2 h following CdCl₂ treatment. The peaks marked ‘X’ arise from FTO electrode (reprinted with permission from ref. 396; copyright @ 2011 Elsevier).

The CdTe film deposited on a CdS/ITO/glass substrate via radio frequency sputtering exhibit a zincblende structure with a preferred orientation of {111} and {511} crystal planes.³¹⁹ A weak {002} hexagonal plane of CdS appeared with dry CdCl₂ treatment, while the same was not observed for the wet CdCl₂ process. Regardless of CdCl₂ treatment, several peaks corresponding to the {220}, {311}, {331} and {422} planes of cubic phase appeared and intensified with an increase in annealing temperature at the expense of the {111} plane. Paulson and Dutta³¹⁸ reported that in the presence of sufficient CdCl₂ vapor pressure, CdTe grains grow preferentially in the cubic phase with {111} orientation. It is also reported that as-grown and vacuum-evaporated thin film CdTe showed a biphasic nature that was cubic and hexagonal, while CdCl₂-treated CdTe showed only a cubic phase with the preferred {111} orientation.³⁴⁵ Thus, the relieved strain energy may contribute to grain growth with {111} growth in CdCl₂ treated films, whereas films without an activation step will have a high density of imperfections in the lattice that may not have preferential grain growth. Major et al.¹³⁸ reported that preferred orientations {111} were lost for films with smaller grain size. This mechanism was due to: (i) randomly oriented nucleation; and (ii) fast growing orientation which dominated by outgrowing the slower ones, taking place only when islands were present in high densities and to their co-operative interactions. Such a difference was attributed to the influence of chamber pressure during CdTe grain growth via CSS. It is therefore inferred that growth conditions, rather than the grain size itself control the preferred orientation. From the above discussions, it is clear that texture changes and crystallographic rearrangements are not identical for all films, indicating that the number of grains of different orientation depends on grain size, temperature and preparative methods, in addition to activation treatment.³⁹⁸

5.2 Efficiency of annealed solar cells

During the preparation of CdS or CdTe, annealing removes excess Cd or S/Te leading to reduction in Cd/Te or Cd/S content at the surface. Hence the improved device performance during the annealing process is due to the increase of the depletion layer width via removal of recombination centers in the form of Cd and Te/S energy levels. The annealing of CdTe/CdS layers with front contact ITO/polyimide under an oxygen atmosphere showed 11.4% efficiency (V_oc = 765 mV, J_sc = 20.9 mA cm⁻² and FF = 71%), while as-deposited cells had only 8.5% (V_oc = 746 mV, J_sc = 19.3 mA cm⁻² and FF = 59.1%) which was attributed to the high stability of annealed films. Despite the higher sheet resistance of the ITO layer, a maximum current density was obtained for the annealed films.³⁹⁹ The efficiency of the solar cell was increased after annealing (300 °C, 25 min) due to the crystallization of the Cu_xTe_1−x layer, which improved the conductivity of the back contact.²³⁷ The current transport across the junction is controlled by a thermally activated process for in situ cleaning of CdS prior to CdTe deposition, while interface recombination via tunneling was observed without in situ cleaning of CdS. This was due to a high density of interface states in the latter compared to former.²⁵⁰ With an in situ cleaning technique, solar cells of about 1 cm² area have achieved an efficiency of 10.5%. Thermochemical data indicated that in situ cleaning of CdS via heating in a hydrogen atmosphere (400 °C, 20 min) will vaporize a thin layer of CdS from the substrate surface and reduce any oxides on the surface of the source material. Thus the clean interface will minimize the extrinsic interface states.²⁵⁰ Layer-by-layer mass spectrometry analysis of heterostructure showed that annealing in air for 10 min leads to the redistribution of Cd, resulting in excess Cd aggregation at the CdTe surface and formation of V_Cd in bulk CdTe.²⁹⁶ The lengthy process of heating (400 °C, >10 min) results in the formation of CdO and CdTeO₃ at the layer surface generating V_Cd in the bulk CdTe layer without passivating the non-radiative recombination centers.^16,203,400 Since V_Cd in CdTe serves as an acceptor, generation of these vacancies gives rise to inversion in the conducting type of the graded gap from n-CdTe_1−xS_x to p-CdTe_1−xS_x, which means that p–n junction moves to CdS_1−yTe_y/CdTe_1−xS_x surface. Short term annealing, however, results in only indium diffusion from the In doped n-CdS layer and in this case the p–n junction shifts to the CdTe region. The diffusion length is a function of the lifetime and mobility of carriers relating to recombination and trapping within the grains and or GBs serving as recombination centers for minority carriers and trapping centers for majority carriers. Since annealing promotes the incipient fusion of smaller crystallites, it reduces the grain boundary density increasing the diffusion length.⁴⁰¹ The CdTe grown on CdS/SnO₂/ITO at a substrate temperature of 340 and >500 °C showed superior cell characteristics, as these temperatures render a favorable film morphology with compact layers consisting of larger grains with a size of the film thickness and a minor concentration of voids and craters.³²⁶

5.3 Efficiency of CdCl₂ treated solar cells

The efficiency of solar cell with CSS-CdTe deposited at low temperature (420–474 °C) was tuned by changing the degree of saturation in CdCl₂–CH₃OH from 50 to 75%. With increase in the degree of saturation, the efficiency was increased at a given temperature. In contrast, an opposite trend was observed with high temperature deposited CdTe solar cells (620 °C). The efficiency was almost same for the above device for a 100% saturated solution (Table 2).³⁴³ This result showed that depositing CdTe via CSS at low temperature can be beneficial for device fabrication as it eliminates the problems associated with the softening of the soda lime glass substrate and consequent diffusion of impurities into the film structure. The CdCl₂ treatment drastically improved the efficiency for CdTe deposited at low temperature, while only a marginal improvement was observed for the high temperature CdTe deposited cell.³⁴³ The conversion efficiency, 11.5%, increased after dry CdCl₂ treatment at a temperature of 400 °C and decreased thereafter, which is caused by the change of interface states between CdS and CdTe due to interdiffusion, and also due to the increased grain size with a decrease in the number of GBs (Fig. 18).³¹⁹ However, wet CdCl₂ treatment was not effective for grain growth and reproducible results were not obtained. The efficiency increased from 7.1–14.1% for a glass/ITO/CdS/CdTe/C/Ag device with a decrease in CdCl₂ treatment temperature (T-CdCl₂) from 460–415 °C, which was correlated to homogenization of the spatial distribution of excitons bound to the acceptor states of CdTe or impurities leading to optimized p-type conversion of CdTe.³⁵¹ On the other hand, when T-CdCl₂ is kept constant, the efficiency decreased with increase in substrate temperature >630 °C during CdTe deposition.³⁵¹ Vapor chloride treatment of CdTe in O₂ ambient showed a high FF of 72.5% compared to cells that were heated in inert He (64.4%) and H₂ (68.5%) ambients. The J–V feature of oxygen-annealed devices during the CdCl₂ treatment has been found to affect the consumption of CdS and the defect structure of CdTe.^147,313 The solar cells exhibit maximum V_oc and J_sc after CdCl₂ vapor treatment for 60 min (Table 3).²⁷⁵ For this treatment time, CdCl₂ enhances the crystalline quality of the intermixed region by decreasing non-radiative recombination centers and only a minor consumption of CdS layer takes place. The decrease in efficiency for longer treatment times was attributed to: (i) excess diffusion of Te into CdS forming CdS_yTe_1−y, which reduces the high energy portion of the device spectral response; (ii) consumption of CdS layer and formation of CdTe/ITO microjunctions; (iii) compensation of excess Cl; and (iv) an intermixed phase that gradually disappears, as revealed by PL studies.^275,402 In contrast, FF attained a maximum value at 30 min suggesting that the optimization was observed over a broad range of 30–60 min. Such behavior could be attributed to CdS, which received only thermal treatment prior to CdTe deposition rendering improper mixing of CdTe and CdS.²⁷⁵ In another study, a device treated with CdCl₂ (400 °C in air, 10 min) resulted in high efficiency compared to other annealed films treated in the range of 20–60 min (Table 4).⁴⁰³ For very low annealing times, CdCl₂ treatment promotes the sulfur diffusion into CdTe to form a CdS_xTe_1−x alloy near the interface. The 1.5 eV band in untreated CdTe shifts to 1.445 eV after CdCl₂ treatment, indicating a change in the dominant PL recombination pathway. It is likely that the CdCl₂ promoted sulfur diffusion near the interface passivates the grain boundary and increases the relative luminescence efficiency by reducing the non-radiative recombination centers. For a very long annealing time, diffusion of sulfur towards the back surface of the cell takes place implying that all the CdS is consumed and uniform solid solution results.⁴⁰³

Table 2 The cell parameters for CdTe growth and CdCl₂ treated at different temperatures (reprinted with permission from ref. 343; copyright @ 1999 American Vacuum Society)

Film	CdCl2 treatment		V oc/mV	J sc/mA cm^−2	FF (%)	η (%)
	T/°C	CdCl2–methanol (%)
Low temperature (420–474 °C)	—	—	416	5.6	31.0	0.7
	400	100	689	12.9	38.6	3.4
	400	50	617	18.1	42.1	4.7
	400	75	741	18.3	46.6	6.3
	420	50	747	21.0	54.0	8.5
	420	75	745	20.8	57.4	8.9
High temperature (620 °C)	—	—	710	9.6	60.9	8.4
	400	100	631	11.3	52.9	3.8
	400	50	798	19.9	66.7	10.6
	400	75	720	20.2	48.5	7.1
	420	50	773	19.8	56.0	8.6

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Fig. 18 Influence of annealing temperature with evaporated CdCl₂ layer on CdTe/CdS solar cell parameters (reprinted with permission from ref. 319; copyright @ 2011 Elsevier).

Table 3 Cell parameters after CdCl₂ vapor treatment at different time intervals (reprinted with permission from ref. 275; copyright @ 2010 Elsevier)

CdCl2 treatment in minutes	J sc/mA cm^−2	V oc/mV	FF (%)	R sh/Ω cm^−2	R s/Ω cm^−2	η (%)
15	9.7	578	39.1	146	25.7	2.2
20	13.7	595	43.5	133	17.1	3.5
30	14.7	618	52.4	112	13.7	4.7
40	16.4	641	35.7	247	23.7	3.7
60	18.5	663	40.8	137	20.0	4.7
70	17.0	470	30.2	20	21.6	2.4
90	10.0	191	25.7	55	18.0	0.5

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Table 4 Annealing time dependent cell parameters at 400 °C (reprinted with permission from ref. 403; copyright @ 2000 Elsevier)

Annealing time/min	V oc/V	J sc/mA cm^−2	FF (%)	η (%)
As grown	0.55	13	31	2.1
10	0.70	22	57	8.4
20	0.72	21	51	7.9
30	0.67	18	53	6.6
40	0.64	20	53	6.7
60	0.62	19	50	6.0

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The solar cells with SnO₂ front contact and Ni back contact showed high FF when dipped in CdCl₂ compared to MnCl₂ and CsCl (Table 5).⁴⁰⁴ The poor current for MnCl₂ and CsCl was due to the lower carrier mobility in the absorber. Thus the roles played by Mn and Cd atoms on the surface and or inside CdTe layer are different in that Cd reduces the film resistance, while opposite was observed for Mn. However, a low FF of 0.48 for CdCl₂ treated solar cells was mainly due to the parasitic back barrier, which serves as secondary parasitic diode connected in series but with opposite polarity to the main photocurrent-generating diode. Such a barrier has a distinct signature; reduced FF along with a “rollover” of J–V curves that turns down in the higher voltage range. Though the V_oc increased slightly at lower temperature, the rollover becomes much more pronounced as the temperature is reduced and the back contact barrier becomes progressively larger compared to kT implying the J_sc temperature dependence is due to the back barrier effect extending well into the power quadrant.⁴⁰⁴ The heat treatment increased the efficiency from 1.2–3.6% mainly as a result of an increase in J_sc from 6.5 (for as deposited cells) to 15 A cm⁻² without a change in the V_oc (0.55 V) and FF (39%). However, CdCl₂ treatment resulted in a drastic improvement in the cell parameters (V_oc = 0.65 V, J_sc = 26.5 A cm⁻² and FF = 56%) with an efficiency of 10% via switching the current transport mechanism from tunneling to a thermally activated process.³⁷⁵ As-deposited films did not exhibit a back contact effect due to their high resistivity. The R_s decreased from 76 to 16.7 and 6.7 Ω sq⁻¹ for heat- and CdCl₂-treated films, respectively, while leakage resistance although decreased for heat-treated films (106 Ω sq⁻¹), was enhanced after CdCl₂ treatment (180 Ω sq⁻¹) compared to as-deposited films (150 Ω sq⁻¹) accounting for improvement in the FF of these cells. The collection efficiency of CdCl₂ treated cells showed a well-formed junction compared to as-deposited and heat-treated films.³⁷⁵

Table 5 Cell parameters treated with different chlorides (reprinted with permission from ref. 404; copyright @ 2003 Elsevier)

Cell parameters	Not treated	Dipped in different chloride solutions and annealed in air
		CsCl	MnCl2	CdCl2
J sc/mA cm^−2	0.28	5.9	12.5	18.9
V oc/mV	380	460	390	820
FF (%)	0.21	0.27	0.26	0.48
η (%)	0.02	0.4	1.3	7.4

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Temperature dependent I–V analysis in the dark indicated that above 280 K, the dominant current transport mechanisms in Au–CdTe/CdS–TO (as-grown) (G1) and Au–(annealed) CdTe/CdS–TO (G2) devices are determined by interface state recombination, while current transport was limited by the depletion region recombination for Au–(CdCl₂ dipped and annealed) CdTe/CdS–TO (G3).⁴⁰⁵ Below 280 K, multistep tunneling was the dominant transport mechanism for the above devices. The high-frequency C–V studies for G1 and G2 revealed that the capacitance values were independent of reverse bias in the entire temperature range due to the presence of a thin insulation layer at the CdS–CdTe interface, while the G3 device showed a dependence on voltage (Fig. 19). Thus, the C–V variation observed in device G3 is attributed to the narrowing of depletion width and improvement in junction interface via decrease of interface state density. The DLTS revealed that majority carrier hole traps in G1 localized at E_v + 0.19, E_v + 0.20, E_v + 0.22, E_v + 0.30 and E_v + 0.40 disappeared after CdCl₂ heat treatment, resulting in the formation of new hole trap at E_v + 0.45 eV. The low efficiency of vacuum-deposited solar cells investigated in this study was attributed to the presence of complex or extended defects originating from V_Cd and impurities like gold or chlorine.⁴⁰⁵

Fig. 19 The C–V characteristics for typical devices from groups (a) G1, (b) G2 and (c) G3 measured at various temperatures and 1 MHz frequency (reprinted with permission from ref. 405; copyright @ 2004 Elsevier).

The solar cell treated with CdCl₂ and Cu₂Te/Au back contact showed a conversion efficiency of 12% which was lowered to 6% after subjection to thermal stress. However, the performance was increased to 9.5% by applying a reverse bias to thermally stressed cells.³⁶⁷ The stress test revealed that Cu atoms occupying CdS shield from the light intensity penetrating into the CdTe layer. The stronger light-shielding at the shorter wavelength region suggests that deep-level Cu impurity is located at 1.55 eV below the CB, so that electrons can be freely activated from Cu states to CB. The copper atoms from the back contact diffuse through the CdTe layer and are incorporated into the CdS layer, which result in less n type states and reduce the junction potential.³⁶⁷

6. Improvement in the efficiency of CdTe/CdS solar cells by varying the properties of individual components

6.1 High efficiency reported solar cells

The annealing of CdS in an H₂ atmosphere prior to CdTe deposition exhibits an efficiency of 15.8%.^406,407 The use of a high substrate temperature for CdTe deposition via CSS promotes the formation of an interfacial layer, shifting the electrical junction to a p-CdTe layer and improving the cell parameters. The back contact involved chemical etching with a 0.1% Br₂–CH₃OH solution or an NP etch followed by the application of a doped graphite paste. The decrease in CSS substrate temperature during CdTe deposition and increase of CdS thickness was detrimental to performance. However, V_oc was relatively independent of substrate temperature in the range of 540–625 °C.^406,407 The CTO (Cd₂SnO₄)/ZTO(ZnSnO_x)/CdS:O/CdTe/back contact structure exhibited an efficiency of 13.9% and 16.5% with an infrared transmission of 50%.^205,256 The CdS:O window layer has a higher optical band gap (2.5–3.1 eV) and smaller grain size compared to a conventional CdS film resulting from its high oxygen atomic concentration. The CdS:O also had a high photoconductivity ratio, demonstrating its high material quality and lower defect density. In addition, oxygen content reduces tellurium diffusion from CdTe into CdS and improved QE in the lower wavelength region. By integrating a ZTO buffer layer, the probability of forming a localized CTO/CdTe junction was significantly reduced.²⁵⁶ In addition, the ZTO buffer served as an “etch stop” layer during back contact formation and greatly reduced the shunting problems. The interdiffusion between ZTO and CdS during CdCl₂ treatment may relieve the stress at the ZTO–CdS interface and improve their adhesion to the substrate. The use of a resistive or buffer layer in addition to conductive TCO appears to be beneficial, especially for those devices fabricated with thin CdS films. By incorporating a very thin resistive buffer layer, a CdS layer with a thickness of <50 nm could be used that can improve the blue response, CdS film morphology and conversion efficiency.⁴⁰⁸ Dharmadasa et al.⁴⁰⁹ reported an efficiency of 18% for a glass/conducting glass/CdS/CdTe/metal device, where the depletion width of the device structure is greater than the combined thickness of the CdS/CdTe layer. Since both the absorber and window layer were n-type, further incorporation of n-type dopant is expected to improve the electrical conductivity of the device structure.

6.2 Solar cells deposited on an Mo substrate

Conventional thin film solar cells manufactured on a glass substrate have the disadvantage of weight and the fragile nature of their modules in which glass makes up to 98% of the device thickness and weight.⁴¹⁰ Its poor thermal expansivity and conductivity causes thermal gradients and non-uniform device properties on panels with a continuous fabrication process involving high temperature (>500 °C).^411,412 Normally, thermal treatment during the cell fabrication reaches the melting temperature of ordinary soda lime glass, causing the rupture of the glass substrate or diffusion of sodium into the cell structure.⁴¹³ A passivating layer like Al₂O₃, SiO₂ or 1 μm ITO (90% In₂O₃ and 10% SnO₂) is usually deposited to avoid sodium diffusion from the glass substrate.¹⁷⁴ As an alternative, solar cells can also be deposited on metal foil or a polymer substrate,⁴¹⁴ which results in cost reduction, high material utilization, increased fabrication scalability and more importantly they do not show a “darkening of color” as observed in some glass based cells under particle irradiation. CdTe and Mo have very similar thermal expansion coefficients of 5.0 × 10⁻⁶ and 4.8 × 10⁻⁶ K⁻¹, respectively. Even after annealing (550 °C, 2 h), CdTe does not peel away from Mo foil nor form blisters/bubbles.⁴¹⁵ Since high purity Mo can be obtained, problems associated with dopant impurity diffusion into CdTe will be reduced at the elevated temperature.

Solar cells deposited on the Mo substrate showed an efficiency of 5.3%.¹⁸⁹ A thin layer of Cu and Te film was used as a contact layer between CdTe and Mo. A series of experiments revealed that both CdS and CdTe pretreated with CdCl₂ and CdTe annealed in air with double CdS layer (a CdS film of 200 nm followed by annealing and deposition of a second CdS layer with 800 nm thickness) exhibit a V_oc of 824 mV compared to other cells wherein CdTe was annealed in nitrogen and CdS (or CdTe) without CdCl₂ treatment. The first layer of CdS will be consumed by CdTe due to interdiffusion of tellurium and sulfur across the interface by forming a Cd–Te–S solid state alloy. After the first layer is annealed, it becomes CdTe_xS_1−x, and sometimes it becomes p-type as determined by the four point probe technique.^416a The p–n junction is thus destroyed, and is again recovered after the deposition of second layer and further improved after annealing. The enhancement in the presence of oxygen was attributed to its role as an acceptor dopant and its incorporation in both CdS and CdTe passivates the interface states inhibiting the formation of a buried p-CdTe/n-CdTe homojunction.⁴¹⁷ These studies further revealed that the depletion layer spans the entire CdS and CdTe film thickness and the cell needs to be conceived as a single junction device instead of three separate junctions (Mo–CdTe, CdTe–CdS, and CdS–TCO).⁴¹⁷ The solar cell deposited on a flexible Mo substrate using a thin interlayer Au/Pd alloy annealed at 400 °C showed an efficiency of 3.5%.⁴¹³ It was assumed that the thickness of the CdS layer decreased during the thermal treatment as a result of CdS sublimation from the surface. The V_oc dropped from 0.5 to 0.2 V for the films calcined at 450 °C. The difference in work function of p-CdTe and Mo necessitates for an interlayer that can form a non-rectifying contact between CdTe and Mo.⁴¹³ Such measures are usually referred to as a back surface field (BSF), which increases the cell performance by reducing recombination at the back contact leading to improved V_oc and reduced R_s. In another study, the cell deposited on 100 μm thick Mo foil with a ZnTe:N back contact resulted in 7.06% efficiency. However, such a structure suffered from poor V_oc and FF with strong roll-over under forward current because of an inefficient back contact.⁴¹⁸ The low efficiency of the solar cells in these cases is caused by the fact that the conventional device structure must be inverted, which restricts device processing and consequently limits the electronic quality of the CdTe layer. Very recently, Kranz et al.^416b reported a breakthrough efficiency of 13.6% in the substrate configuration via controlled doping of Cu into the CdTe layer. The addition of 0.8 × 10¹⁵ Cu atoms per cm² (sub-monolayer, with an equivalent thickness of 1 Å) to 5 μm thick CdTe decreased the resistivity and increased the hole density. Furthermore, this optimum Cu doping resulted in a space charge region of 1.8 μm and caused sufficient band bending close to the CdS to generate a strong electric field leading to effective carrier collection. Although, the substrate configuration allows better control of p-type doping into CdTe matrix in the absence of n-CdS layer, back diffusion of metals during subsequent processing of the window layer and front contact is hard to control.

6.3 Solar cells with different front contact

The solar cell fabricated via radio frequency sputtering at 250 °C using an AZO front contact exhibited a high efficiency of 14.0%, while 12.6% was observed for SnO₂:F based solar cells (Table 6).⁴¹⁹ The advantages of AZO over SnO₂:F as front contact are: (i) the AZO showed excellent transparency in the entire visible spectrum; (ii) a high carrier mobility and low current density as indicated by Hall measurements; (iii) lower sheet resistance of 2.47 at the centre and 3.47 at the edge compared to SnO₂:F (7.29 Ω sq⁻¹) resulting in lower R_s. The higher collection in the blue region (360–560 nm) was observed for AZO compared to SnO₂:F despite that the deposited layer was 0.13 μm in both cases. Furthermore, interdiffusion of Zn into CdS modifies the AZO–CdS interface during CdCl₂ treatment, which increases the band gap and transmittance of the CdS layer.⁴²⁰ The higher QE response (11%) was observed in the visible region (550–825 nm) due to the better transparency of AZO (Fig. 20). An efficiency of 15.4 and 15.6% was obtained for solar cells deposited on borosilicate (BSG) and aluminosilicate glass (ASG) respectively, while the performance was lowered with other substrates using AZO/i:ZnO bilayer front contact (Table 7).⁴²¹ The high V_oc of AZO/i:ZnO/CdTe compared to AZO/CdTe and higher voltage at i:ZnO/CdTe junction together with restriction of current flowing back into weak diodes is attributed to the beneficial effect of the i:ZnO layer with a thickness of 50 and 100 nm.⁴²¹ Increasing the thickness of the i:ZnO layer leads to UV absorption losses (which results in potential current loss of 0.7 mA cm⁻²), narrowing the depletion layer width and hence reducing the collection efficiency in the longer wavelength region (685–830 nm). In contrast, a sprayed AZO of 3.2 μm thickness exhibits a high V_oc and lower efficiency of 12.1% without antireflection coating compared to sputtered AZO.⁴²² The average value of >11% measured for 22 fabricated solar cells highlights the high homogeneity of the sprayed AZO layer and the feasibility of deposition in solar cell applications.⁴²² An efficiency of 13.5% was reported for high-vacuum evaporated solar cells with a thick AZO/i:ZnO bilayer deposited on soda lime glass, despite the large content of sodium in the glass substrate.¹²⁸ This is caused by the superior diffusion barrier properties of the thick bilayer due to both increased thickness as well as large grain size. In contrast, application of a thin buffer barrier resulted in widened GBs for CdTe because of significant sodium diffusion deteriorating the cell performance.¹²⁸

Table 6 CdTe/CdS device data on SnO:F and ZnO:Al (reprinted with permission from ref. 419; copyright @ 2004 American Institute of Physics)

TCO	V oc/mV	J sc/mA cm^−2	FF (%)	η (%)	R s/Ω cm^2	R sh/Ω cm^2
SnO2:F	820	20.7	73.96	12.6	3.9	1822
ZnO:Al	814	23.6	73.25	14.0	3.16	989

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Fig. 20 QE curves of CdTe/CdS solar cells using ZnO:Al and SnO₂:F front contact (reprinted with permission from ref. 419; copyright @ 2004 American Institute of Physics).

Table 7 Cell parameters grown on different substrates with AZO/i.ZnO bilayer front contact (reprinted with permission from ref. 421; copyright @ 2011 Elsevier)

Substrate	V oc/mV	J sc/mA cm^−2	FF (%)	η (%)
a Antireflection coating applied.
ASG	834	24.7^a	75.9	15.6
BSG	821	25.0^a	74.8	15.4
SLG no barrier	821	22.9	72.4	13.0
Polyimide 7.5 μ	823	19.6	76.5	12.4
Polyimide 12.5 μ	799	17.8	72.2	10.3
TeC15 (FTO)	826	20.1	73.0	12.1
BSG/Mo	658	21.4	61.2	8.6

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The application of low cost APCVD graphene films grown on Cu foil at 1000 °C by varying the H₂–CH₄–Ar gas rate as front electrodes with a ZnO barrier layer resulted in 4.17% efficiency (Fig. 21).⁴²³ The choice of graphene stems from its suitable work function (4.42 eV) close to FTO (4.4 eV). ZnO improved the continuity and crystallinity of CdS film and also prevented unwanted forward leakage current enhancing the lateral current collection. The device without a ZnO barrier showed an efficiency of 2.81% due to a poor interface between CdS nanoparticles and the graphene film resulting in poor wetting and incomplete surface coverage. This allows forward leakage current to the graphene front contact, simultaneously reducing the efficiency. Graphene films exhibit an extremely high carrier mobility (up to 600 cm² V⁻¹ s⁻¹) compared to commercial TCFs with a sheet resistance in the range of 1150–220 Ω sq⁻¹ and better optical transparency of 97.1–83.7% in the 350–2000 nm spectral region depending on the number of layers. The number of layers was found to be 1, 2, 4 and 7 for H₂ gas flow rate of 10, 30, 50 and 80 in sccm in H₂-CH₄-Ar.⁴²³

Fig. 21 Schematic diagram and J–V features of a solar cell with graphene front electrode (reprinted with permission from ref. 423; copyright @ 2011 Wiley-VCH).

Among the various TCOs, such as Sn-doped In₂O₃, F-doped In₂O₃ (FIO), Cd₂SnO₄, Ge-doped In₂O₃, SnO₂ and Zn₂SnO₄ devices, the FIO-based device showed the highest efficiency of 14%. The sputtering atmosphere used for the deposition of FIO was a mixture of Ar, Ar + H₂ and CHF₃ (Table 8). In addition, smooth and transparent FIO had resistivity of 2.5 × 10⁻⁴ Ω cm and 1000 Å of this material were sufficient to passivate sodium atoms which would otherwise diffuse into the film from soda lime glass.⁴²⁴

Table 8 Characteristics of TCOs as front contacts for the CdTe/CdS solar cells included (reprinted with permission from ref. 424; copyright @ 2003 Elsevier)

TCO	Sputtering gas	Resistivity/Ω cm	Transparency 400–800 nm	Stability of the device^a	Reproducibility
a Stability of device on different TCO after the aging process on ‘open circuit conditions’, under 10 suns, at a temperature of 110 °C for 2 h.
ITO	Ar + 4% H2	2 × 10^−4	≥80%	Good	Good
SnO2	Ar + 20% H2	8 × 10^−4	80%	—	—
IGO	Ar + CHF3 + H2	2 × 10^−4	85%	Very good	Very good
Cd2SnO4	Ar + 50% O2	2 × 10^−4	85%	Very good	Very good
Zn2SnO4	Ar + 50% O2	10^−2	≈90%	—	—
INO:F	Ar + CHF3 + H2	2.5 × 10^−4	≥85%	Excellent	Excellent

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A sufficiently thick and large grained AZO layer as TCO can effectively suppress sodium diffusion from soda lime glass and protect the device from degradation.¹²⁸ High electron mobility and better transparency of AZO in the wavelength region <900 nm makes it an attractive candidate for CdTe solar cells.⁴¹⁸ The main disadvantage of AZO is its instability at high temperature due to aluminium diffusion or inter diffusion across the ZnO–CdS interface during the process conditions and illumination.⁴¹⁹ Graphene as a front electrode would be quite encouraging because of the limited availability of indium, the high production costs and poor performance as a result of deterioration and brittleness due to ion diffusion.⁴²⁵ Transparent conducting oxides are very important for the design of solar cells not only for their electro-optical properties but also for their favorable interaction with CdS. It is also useful to take advantage of the different properties of two TCOs by forming a bilayer consisting of a highly conducting and very thin layer of suitable materials. This structure can minimize forward current through pinholes in the window layer and eliminate the formation of shunting microjunctions.⁵

6.4 Influence of CdS layer thickness on device performance

The device efficiency increased with decrease in d_CdS from 114 to 95 nm without change in V_oc and FF (Fig. 22).²⁷¹ This was ascribed to an increase in J_sc with a reduction in d_CdS that improved the spectral response in the shorter wavelength region (λ < 590 nm). For d_CdS < 85 nm, large decreases in V_oc and FF were observed without change in J_sc, resulting in poor efficiency. The increased recombination of charge carriers in PV active layer lowers the infrared response with the reduction of CdS thickness. The electroreflectance measurements indicated that interdiffusion rate will be low for very small d_CdS, thus increasing the lattice mismatch and interface states at the CdS–CdTe interface.²⁷¹ The deterioration of CdTe_1−xS_x inhibits the grain growth of CdTe and increases the dark current at low bias voltages, resulting in low FF and V_oc. The dominant influence of CdTe_1−xS_x with d_CdS < 85 nm lies in changing the diode properties of the cell rather than its trivial optical properties as window layer.²⁷¹ The solar cells with a CSS-CdS film thickness of 160 nm showed superior performance (10.9%) compared with different thicknesses such as 200, 130 and 180 nm at various substrate, source temperatures and times along with a copper-free back contact.³⁹⁵ This suggests that neither a high nor reduced CdS thickness could contribute to enhanced performance. The high efficiency was attributed to a rise in the substrate temperature from 380 to 420 °C during the deposition leading to a more homogeneous and dense CdS film.³⁹⁵ The efficiency was further increased to 12% after fabricating the cell with a copper back contact. A thinner CdS film (130 nm) was used as substrate to deposit a CdTe film at 340 °C, while a thicker CdS film (180 nm) was used to deposit CdTe at 520 °C indicating that the optimal temperature for CdTe deposition depends on the CdS film thickness. In addition, the junction activation treatment for high-temperature deposited CdTe was annealing at 380 °C for 25 min, and 400 °C for 30 min in the case of low-temperature CdTe.³⁹⁵ The device efficiency was improved by introducing an In (or Sn)-oxide buffer layer onto the TCO film and V_oc > 0.84 V and FF > 75% was achieved.⁴²⁶ The In-oxide layer breaks off the influence of ITO during the heat treatment and reduces the strain or dislocation at the ITO–CdS interface in the vicinity of the CdTe/CdS junction. The increase of the diode factor without In-oxide buffer was explained by the decrease of QE in the entire wavelength region with forward bias, while such junction recombination dependence on forward bias voltage was not observed with an In-oxide buffer layer. A significant improvement in FF was not achieved due to the thermal expansion coefficient of glass substrate. However, by using a two-step CdS formation method, the efficiency was improved on a soda lime glass substrate due to the evaporation of CdS which promoted the interdiffusion of sulfur and tellurium (Table 9). In addition, fabricated cells using a two-step CdS film did not reduce its QE in the wavelength region of 500–550 nm (Fig. 23). A high efficiency of 15% was also obtained with a corning glass substrate.⁴²⁶

Fig. 22 Photovoltaic performances as a function of CdS layer thickness (reprinted with permission from ref. 271; copyright @ 2003 Elsevier).

Table 9 Characteristics of the cells fabricated on corning and soda lime glass (under AM 1.5 G condition, 25 °C, calibration with GaAs standard cell) included (reprinted with permission from ref. 426; copyright @ 1997 Elsevier)

Glass substrate	In-oxide buffer	2-step CdS	V oc/V	J sc/mA cm^−2	FF (%)	η (%)
Corning 7059			0.747	24.2	58.9	10.7
	✓		0.842	25.0	75.9	16.0
		✓	0.805	25.8	71.5	14.8
	✓	✓	0.824	26.0	72.0	15.4
Sodalime			0.572	22.8	60.3	7.88
	✓		0.830	22.4	67.5	12.6
		✓	0.807	23.8	71.7	13.8
	✓	✓	0.819	23.9	74.1	14.5

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Fig. 23 Change in spectral response of the cells fabricated on corning glass by introducing the two step CdS formation method (reprinted with permission from ref. 426; copyright @ 1997 Elsevier).

The solar cell with bilayer (120 + 40 nm) CBD-CdS showed 6.55% efficiency compared to other structures, which were different in the junction activation step.⁴²⁷ CdCl₂ treatment was applied after bilayer deposition of CdS to obtain the best device; the first CdS layer at 75 °C for 10 min and the second CdS film was deposited at 40 °C for 45 min to form the bilayer. In others, meanwhile, junction activation was done after first layer deposition of CdS or at each stage of CdS deposition (Fig. 24). The spectral response as a function of wavelength showed a maximum at 600 nm corresponding to the carrier collection generated in the depletion layer due to the strong electric field in this region. A slow decrease for the maximum down to 400 nm indicates that the CdS bilayer is thin enough to allow light-generated charge carriers beyond 510 nm corresponding to the CdS band gap.⁴²⁷ The bilayer CdS comprising of CSS-CdS (bottom) and a second CBD-CdS layer on top showed a high efficiency of 10.1% compared to their individual counterparts.⁵⁹ The CSS-CdS possesses a larger grain size and more cracks among the GBs, while CBD-CdS has very small grain size. Thus, CBD-CdS covers CSS-CdS producing a complete absence of pinholes and cracks in the multilayer structure. The multilayer film was more homogeneous and compact and its thickness (80 nm) was lower than either CSS-CdS (150 nm) or CBD-CdS (150 nm), thus allowing more photons to pass through the window layer.⁵⁹ As a window layer, multilayer CdS with uniform grain size distribution exerts a positive effect on the performance of final device structure.

Fig. 24 CdTe/CdS solar cell with CBD-CdS bilayers treated with CdCl₂ at different stages (reprinted with permission from ref. 427; copyright @ 2008 Elsevier).

6.5 Solar cells with designed window layers

The unoptimized metal/CdTe/CdS/Cd_1−xZn_xS device grown on TCO coated soda lime glass of 3 mm thickness without an antireflection coating exhibited 10% efficiency due to a better spectral response in the short wavelength region.¹⁰² The high electron affinity (χ_n) of CdS compared to CdTe (χ_p) eliminates the energy spike at the CdTe/CdS junction. The graded junction between Cd_1−xZn_xS/CdS exists due to their solubility, in which band gap edges change over certain distance with a finite slope corresponding to the electric field strength. For a thin CdS film, the slope covers the whole of their intermediate layer and coupling with Cd_1−xZn_xS extends the depletion region throughout the original thickness (W_g) of the CdS layer and up to χ_p in the CdTe layer (Fig. 25). However, efficiency was lower compared to traditional cells due to the diffusion of Zn and the large lattice mismatch between Cd_1−xZn_xS and CdTe that pins the Fermi levels restricting their motion, as the displacement of a quasi Fermi level at the interface determines the V_oc.¹⁰² The increase of V_oc from 520 to 830 mV with x varying from 0 to 0.35 was attributed to a reduction in the electron affinity mismatch difference between Cd_1−xZn_xS and CdTe films at the interface. The lattice mismatch of Cd_1−xZn_xS with CdTe are 3.7 and 4% for x = 0 and 1 respectively, while a minimum of 0.06% was observed for x = 0.65. The total efficiency did not exceed >4% owing to the high resistivity of the solid solution based films.⁴²⁸ The substitution of Zn into CdS structure improved the efficiency for all the absorber layer thickness (2.25, 1.0 and 0.5 μm CdTe) except for 0.2 μm thick CdTe.¹²¹ This reflects the poor performance of the thinnest device as a result of microshorting because of incomplete coverage of 0.2 μm thick CdTe. In addition, the ultrathin film lost the benefit of an improved blue response due to the diffusion of zinc from the window layer associated with CdCl₂ treatment. However, reduction in the CdCl₂ layer thickness was found to recover the blue response.¹²¹ In another study, the Cd_0.9Zn_0.1S window layer increased the efficiency to 11.42% as compared to only CdS (7.31%).⁴²⁹ The observed increase in J_sc was attributed to a shift in the optical band gap of the window layer from 2.4–2.7 eV, improving the blue response and shifting the absorption edge from 500–400 nm for the ternary alloy window layer. Thus, Cd_1−xZn_xS/CdS served as suitable window layer similar to CdS to improve the short wavelength response without compromising the transport properties, series and shunt resistance of the solar cell.¹⁰² The ZnCdS is used as a window material for the fabrication of p–n junction without lattice mismatch in the device based on CuIn_xGa_1−xSe₂,⁴³⁰ or CuIn(S_zSe_1−z)₂,⁴³¹ CuInSe₂ and CuGaSe₂.⁴³² However, Cd_1−xZn_xS film in CdTe devices has some serious drawbacks such as a linear change in lattice parameter with Zn content and electrical resistivity increases from <1 Ω cm to >10¹⁰ Ω cm as ‘x’ increases from 0 to 1.⁴³³

Fig. 25 Ideal band diagrams of Cd_1−xZn_xS/CdS/CdTe system (a) before and (b) after junction formation (reprinted with permission from ref. 102; copyright @ 2000 Elsevier).

The optical transmittance of the strong interface In_x(OOH,S)_y/CdS double layer improved significantly in the wavelength region of 500–600 nm with increase in the thickness of In_x(OOH,S)_y (Fig. 26). The increase of transmittance in the wavelength range of 400–500 nm was attributed to a reduced thickness of CdS in comparison to the bare CdS (180 nm) film. The efficiency was found to be 9.55% for only CdS and declined to 6.3% for the double layer.⁴³⁴ In addition, J_sc, V_oc and FF were not improved with In_x(OOH,S)_y because of a lower potential barrier at the window–absorber interface. It was suggested that the CdS in the double layer is less n-type due to Cd out-diffusion from CdS to In_x(OOH,S)_y during the CdTe deposition via CSS method at 575 °C. The series and parallel resistances with double layer were larger and smaller, respectively, compared to only CdS. The large J₀ with In_x(OOH,S)_y suggested that it is necessary to increase the doping concentration of In_x(OOH,S)_y/CdS to achieve a more n-type window layer.⁴³⁴

Fig. 26 Optical transmittance of In_x(OOH,S)_y/CdS double layers with various CdS thickness (reprinted with permission from ref. 434; copyright @ 2009 Elsevier).

6.6 Influence of CdTe thickness on device performance

One of the critical stages in device fabrication is the deposition of a CdTe layer with controlled thickness, composition and stoichiometry. Many advantages were accrued from reducing the thickness of the absorber layer, such as reduced deposition time and post-deposition processing with low environmental impact.^435,436 An efficiency of 9.7–11.8% for ultrathin CdTe thickness of 0.7–1.28 μm was found as compared to standard device with 2.3 μm CdTe (13%).¹²⁰ The cell efficiency remained largely insensitive with CdS thickness within the range of 0.05–0.13 μm. The ultrathin CdTe cells (<1 μm) had a high density of weak diodes and more non-uniformity resulting in poor yield and low V_oc. The aniline treatment was found to increase FF and V_oc without change in J_sc as a result of reduced shunting. The post deposition process of 10 min CdCl₂ treatment, 15 Å Cu back contact and 18 min of back contact diffusion was found to be optimum conditions for the cells with <1 μm thick CdTe.¹²⁰ Electrodeposited CdTe (1.4 μm, deposited for 3 h) showed higher performance compared to a thin CdTe (1.0 μm, deposited in 2 h) device due to Te segregation on the CdTe surface which improved the back contact.³⁹⁶ A distortion in forward current was observed for the cell with a thin CdTe layer (1.0 μm) leading to a lower FF (0.44) and efficiency (3.3%), while cells with a thick layer (1.4 μm) provided a better ohmic contact at the interface (4.4% efficiency). The Te-rich surface layer is associated with increased conductivity and Te segregation minimizes the use of acidic etchants to create a Te-rich surface. The spectral photoresponse revealed that the IPCE of electrodeposited CdTe declined at lower photon energy, which is a characteristic feature of poor grain boundary passivation despite CdCl₂ treatment.³⁹⁶ In addition, solar cells with 1.5 μm CdTe have a larger J_sc by a factor of 913 times higher than 1.0 μm CdTe. It also has a smaller dark saturation current density and a small diode factor both in the dark and light. Thus, a solar cell with a thick CdTe showed more interdiffusion at the CdS–CdTe interface and better PV characteristics.²⁹⁴ The efficiency increased from 0.54–11.34% through tuning the grain size of CdTe from 0.94 to ≥3.6 μm by varying the nitrogen pressure from 2–200 Torr via a CSS method.¹³⁸ This may be due to a reduced probability of nucleation taking place at elevated pressure, resulting in lower nucleation density. This gives a direct method for the control of grain size in CdTe films with the linear relationship between grain size and pressure: D (μm) = 0.027 × P (Torr) + 0.90. The R_s was optimized at 100 Torr and no changes were observed at 200 Torr, indicating a limiting point at which R_s was no longer dominated by grain boundary phenomena, rather it was influenced by the CdTe/Au back contact interface.¹³⁸

To inhibit the possible recombination loss at the back contact, a wide band gap material like ZnTe (2.2 eV) is proposed, which acts as a BSF to repel the carriers at CdTe/ZnTe and reflect towards the CdTe/CdS heterojunction.⁴³⁷ Both V_oc and J_sc for CdS/CdTe/ZnTe increased with the increase in the CdTe thickness, while they decreased for conventional solar cells. In addition, a marginal decrease in efficiency was observed by reducing the CdTe thickness from 2–1 μm with a ZnTe back contact, which is enough to absorb most of the incident photons from solar light (Fig. 27). In contrast, the efficiency decreased below 4 μm thick CdTe and declined drastically for conventional solar cells.²⁵³ The efficiency was tuned from 8.0–13.3% by varying the CdTe thickness from 0.25–2.1 μm by careful optimization of magnetron sputtering conditions, CdS and Cu thickness, CdCl₂ activation and a back contact diffusion process.¹²² The efficiency increased from 6.8–12% with the increase in magnetron sputtered CdTe thickness from 0.3–1.0 μm and stability under light soaking was independent of CdTe thickness (0.5–2.5 μm).⁴³⁵ In another study, V_oc was enhanced by an increment in absorber thickness from 0.5–2.0 μm CdTe obtained by MOCVD due to enhancement in the photogenerated current as the absorption volume is increased. These devices did not exhibit any roll-over features in light J–V curves, indicating a better ohmic contact formation. The smaller V_oc for a thin absorber device suggests an increase of saturation current as a result of the decrease in photogenerated carriers.⁴²⁹ Based on a model, it was proposed that better suitability would be realized by decreasing and increasing the CdS and CdTe thickness, respectively, for NP etched devices. In contrast, this effect was reversed for the devices without NP etching. The physical mechanisms for improved stability with NP etching for a thick CdTe layer may be attributed to the grain-boundary penetrating ability of the etchant.¹⁶¹

Fig. 27 Solar cell performance versus CdTe thickness with and without ZnTe layer (reprinted with permission ref. 253; copyright @ 2007 Elsevier).

The process of back contact formation and surface chemical etching limits the reduction in thickness of absorber layer that can be achieved. In general, thick absorber layers are used to avoid pinholes reaching through the window layer, which leads to shorting from the back contact. In order to reduce the CdTe thickness without compromising the ultrathin quality of the film, a controlled and tunable methodology capable of producing uniform layers must be fabricated. However, a loss of J_sc is inherent with reduction in the absorber layer thickness.

6.7 Effect of doping on device performance

During the device fabrication, oxygen is often present or intentionally introduced during CdTe growth and annealing atmosphere. In the case of both CdTe and CdS, oxygen doping is known to play a role in its morphology, structure, passivation of deep gap states, and hardening against diffusion.^275,438,439 In CdTe, the oxygen effect is manifested in grain size, enhanced p-doping and passivation of GBs, while a prominent effect is to make it resistant to in-diffusion of tellurium and out diffusion of sulfur in the CdS.⁶² In general, CdTe films grown without O₂ show a very large grain size and it is relatively easy to form a shunting path by pinholes formed in the film. In addition, oxygen has a notable effect on the nucleation and growth of the CdTe layer; nucleation site density increases with increasing oxygen content, resulting in lower growth rates, smaller grains and a microscopically more compact and dense structure suppressing the possibility of shunting problems. The presence of oxygen during CSS-CdTe deposition also promotes wurtzite CdTe nucleation.⁶² Valdna et al.⁴⁴⁰ reported that the film resistivity decreased with the incorporation of a small quantity of oxygen into CdTe matrix, while it increased up to six orders of magnitude at a high concentration of oxygen.

The V_oc and FF increased as a function of oxygen concentration (oxygen doping into CdTe) showing maxima at 50 and 90%, while a reverse saturation current prevailed for the device fabricated under the lowest O₂ partial pressure (Fig. 28).⁴⁴¹ The increase of oxygen partial pressure during CSS-CdTe deposition enhanced the net hole concentration and saturated around 3.4 × 10¹⁴ cm⁻³. The change in carrier concentration is consistent with the V_oc behavior; higher doping leads to an increase of the built in voltage and consequently enhancement of V_oc. The spectral response of the heterojunction decreased with increasing O₂ partial pressure in the region of 500–600 nm. The presence of O₂ slows down the reaction between Cd and Te atoms such that Te atoms react with CdS to form CdTe_xS_1−x, leading to an improved junction quality. On the other hand, doping with Sb also resulted in a high V_oc and hole barrier (net carrier concentration) due to larger band bending at the interface. The V_oc reached a maximum at 450 °C and decreased thereafter due to excess recombination because of more Sb reaching the main junction. It was shown that CdTe will be semi-insulating at a very high concentration of Sb in CdTe, as excess Sb substitutes for Cd sites to compensate Sb_Te and V_Cd.⁴⁴² The excess surface Sb or formation of Sb₂Te₃ can be beneficial for the formation of a stable back contact.

Fig. 28 The V_oc and FF for CdTe cells fabricated under different oxygen partial pressures (reprinted with permission from ref. 441; copyright @ 2009 Elsevier).

Based on PL spectral studies, the role of oxygen in oxygen/chloride co-processing of the device includes: (i) enhancement in the concentration of Cl_Te and V_Cd in CdTe; (ii) promoting the diffusion of Te into CdS under highly oxidizing conditions, yielding Te–O complexes; (iii) acting to fill V_S with O_S.³⁰⁹ It is also reported that the amount of Cl and O in CdTe is interdependent i.e., the presence of one of them favors the presence of others.⁴⁴³ As-deposited solar cells showed a efficiency of 5.4%, which increased to 6.6% when CBD-CdS was annealed for 5 min in oxygen ambient prior to CdTe deposition. It was hypothesized that annealing of CdS in oxygen ambient hardens CdS against the diffusion of sulfur and tellurium at the interface. Further improvement in the device efficiency to 9.8% was achieved by etching the CdS film with acid to remove oxide formed during the course of annealing.⁶⁰ The device fabricated on a sapphire substrate using an ITO:F/SnO₂ bilayer increased the efficiency from 11.5–14.0% as a result of O incorporation in CdTe.⁴⁴⁴ The parameters were not affected even after light soaking at a temperature of 100 °C and 20 suns for 20–30 min. The SIMS depth profile indicated that O incorporation leads to an increase in the amount of O (from 10¹⁹ to 10²⁰ cm⁻³) together with doping of electrically active Cl into the CdTe (CdS) layer during CdCl₂ activation. In addition, O at the interface region may also decrease the diffusion of Te from CdTe to CdS side. The O and Cl seem to be an electrically active complex within the CdTe, and to a lesser extent within CdS, which improve the device performance.⁴⁴³ In contrast, interdiffusion across the CdTe/CBD-CdS interface was quite low due to the high concentration of oxygen, while it was effective for CdTe/CSS-CdS.⁴⁴⁵ The presence of oxygen in CdTe did not have any particular effect on the distribution/concentration of impurities like Na, Br, F, In and Sn, while the concentration of Si was lowered, as confirmed by SIMS analysis.⁴⁴³ The importance of CdS–CdTe interdiffusion and O and Cl co-doping is yet to be understood more quantitatively.

The FTO/CdS/CdTe:I/Au cells showed a V_oc of 700 mV.⁴⁴⁶ The iodine dopant enhanced the optical absorption and also improved the electrical conductivity by a factor of 5, indicating a positive effect of n-type doping. The device capacitance was unchanged at 56 pF with applied voltage revealing that the depletion width of device structure is greater than the combined thickness of CdTe/CdS layers. This suggests that a doping concentration <10¹⁵ cm⁻³ in CdTe produces a wider depletion width, greater than the complete device depth. The current–voltage characteristics indicated the presence of a high potential barrier of 1.2 eV with a low ideality factor of 1.40.⁴⁴⁶ Tran et al.⁴⁴⁷ also showed that the absence of a mid band gap and ionized impurity scattering centers due to iodine inclusion into CdTe layers, which otherwise results in the loss of short circuit current. The low FF (0.33–0.40) for this device was due to the larger R_s of the doped material. In the case of non aqueous electro-deposited CdS/Cd_1−xZn_xTe cells, a best performance (J_sc = 26.66 mA cm⁻², V_oc = 600 mV, FF = 0.42 and η = 8.3%) was achieved for 2 × 10⁻³ M ZnCl₂ in a Sb doped CdTe bath.²⁴⁹ The better match of absorber band gap close to the desired optimum value and low R_s of metal–Cd_1−xZn_xTe contact compared to metal–CdTe resulted in higher efficiency. A Mott–Schottky plot revealed that the carrier concentration and built-in potential was 2.72 × 10¹⁷ cm⁻³ and 1.02 eV respectively. Though the Zn incorporation led to higher V_oc, correlation between device performance and Zn mole fraction in Cd_1−xZn_xTe was not observed. The R_s decreased via incorporation of Sb in the absorber layer under both dark and light illuminating conditions. In addition, spectral measurements were higher in Sb doped CdS/Cd_1−xZn_xTe cell relative to the undoped cell in the wavelength range of 520–820 nm leading to higher J_sc. The increase in QE on Sb doping is an indicative of better carrier collection.²⁴⁹ Doping of Bi (4 × 10¹⁷ cm⁻³) into CdTe matrix resulted in an efficiency of 8.0%, while doping at low (1 × 10¹⁷ cm⁻³) and high (2 × 10¹⁹ cm⁻³) content was found to be detrimental, which was attributed to the high and low resistivity of doped samples, respectively.⁴⁴⁸ These results can be understood based on the substitution of Bi in the CdTe matrix; Bi occupies V_Cd at low concentration serving as donor and V_Te at higher concentration acting as acceptor.^449,450 Most of the doping atoms have high mobility and tendency to segregate in the absorber layer; the choice of suitable dopants is still a challenging issue.

6.8 Solar cells fabricated with different back contact

6.8.1 Carbon based/copper/nickel/gold/silver back contacts. The device with Cu₂Te back contact was optimized after annealing at 180 °C (Fig. 29), attributed to a coherent interface of the hexagonal Cu₂Te {0001} and CdTe {111} plane. The R_s decreased with increase in heat treatment of the back contact from 100–180 °C and a sudden enhancement was observed at high temperature as a result of Schottky barrier formation.⁴⁵¹ The incomplete formation of a p⁺ contact at 100 °C results in a high R_s with a diode factor of 3.3. The concentration of Cu at the junction interface and CdTe bulk were 6.57 × 10¹⁴ and 1.13 × 10¹⁵ cm⁻³, respectively. This might be due to diffusion of Cd from CdS to Cd-deficient CdTe, which favored the occupation of V_Cd sites by diffused Cu. Hegedus and McCandless²²⁸ observed similar junction properties and resistance for the devices with wet and dry Cu back contacts. The device with a dry Cu contact had less “roll-over” in forward bias after stressing, while a significant blocking contact formation was observed via wet contact of Cu. In addition, a dry contact process requires much less Cu (2 nm) to achieve an ohmic contact and high forward current conduction in the dark compared to a wet contact (15 nm, Fig. 30). The key differences between dry and wet contacts are that the former leaves a thin Te layer and is less penetrating along the junction boundaries.²²⁸ The cell without Cu contact was characterized by a low V_oc, high J_sc and current limitation (roll-over), while the addition of 5 nm Cu improves the V_oc by 50 mV by eliminating the roll-over (Fig. 31).⁴⁵² Beyond this 5 nm thickness, cell parameters was reduced suggesting the existence of an optimal level of Cu thickness to exhibit high efficiency. Drive level capacitance profiling studies suggested the increase of trap state density (10¹⁴ to 10¹⁵ cm⁻³) with an increment in Cu thickness from 0–20 nm. Shallow-level defects can contribute carriers at room temperature, increasing the performance, while deep-level defects at higher Cu content would be detrimental. The increase of deep-level trap density is a plausible explanation for reduced carrier lifetime at high Cu concentrations. In addition, QE in the longer wavelength region is reduced with increase in Cu thickness suggesting massive charge carrier recombination at the CdTe layers in the presence of Cu defects (Fig. 32).⁴⁵²

Fig. 29 The solar cell parameters of ITO/CdS/CdTe/Cu₂Te/Au cells as a function of annealing temperature (reprinted with permission from ref. 451; copyright @ 2003 Elsevier).

Fig. 30 Light and dark J–V curves for devices with wet (15 nm Cu) and dry (2 nm Cu) contact process (reprinted with permission from ref. 228; copyright @ 2005 Elsevier).

Fig. 31 The current–voltage curves for devices with different Cu layer thickness varying from 0–100 nm (reprinted with permission from ref. 452; copyright @ 2008 Elsevier).

Fig. 32 QE curves of CdTe/CdS solar cells as a function of Cu thickness varying from 0–100 nm (reprinted with permission from ref. 452; copyright @ 2008 Elsevier).

Device instability was increased by an increase in Cu content at the back contact, while “interfacial” Cu was not susceptible to device degradation highlighting that Cu substitution at the interface is beneficial while maintaining respectable performance levels.⁴⁵³ The device with Cu showed a drop in V_oc after light soaking, while it was restored after annealing. However, the device without copper showed a slight decay at the initial stage and remained largely insensitive to consecutive annealing (Fig. 33).¹⁶⁴ Through a procedure of light-soaking for several minutes and low temperature (100 °C), solar cells showed a higher efficiency of 11.4% through decreasing R_s and ionic redistribution in the junction region with a ZnO buffer layer and Cu/Mo back contact. The low carrier density of Cu/Mo contact was sufficient to have a barrier height low enough to create a quasi ohmic contact without the presence of rollover.⁴⁵⁴

Fig. 33 Open-circuit voltage variation with light-soaking stress and annealing for a CdTe/CdS device where the CdTe layer was Cu doped. The points on the graph are: A—initial anneal; B—2 days light soak; C—35 days light soak; D—second anneal; E—2 days light soak after the second anneal; F—third anneal (reprinted with permission from ref. 164; copyright @ 2000 American Institute of Physics).

The device glass/Cd₂SnO₄/ZnSnO_x/CdS/CdTe showed a better FF with a 10 nm Cu thickness. XRD indexed the presence of both CuTe and Cu_1.4Te without Cu₂Te formation. However, the formation of Cu₂Te with large amount of Cu failed to produce a good R_s for the cell. The Cu diffuses into the front region along the grain boundary, resulting in increased shunting at higher Cu levels. In addition, the barrier height was lowest for the device with 10 nm of Cu and increased thereafter (Table 10).⁴⁵⁵ Cu diffusion from the ZnTe:Cu contact interface increased the net acceptor concentration in the CdTe layer reducing the space charge width of the junction with simultaneous enhancement in current collection.⁴⁵⁶

Table 10 The device parameters for various Cu thickness (reprinted with permission from ref. 455; copyright @ 2007 Elsevier). A few parameters are not considered for clarity

Thickness of Cu/nm	V oc/V	FF (%)	η (%)	J sc/mA cm^−2	Φ (b)/eV
0	0.733	59.8	10.1	23.0	0.53
10	0.797	71.3	12.9	22.7	0.48
60	0.783	68.0	12.1	23.2	0.50
95	0.767	67.2	11.7	22.7	0.51
110	0.761	65.5	11.1	22.2	0.52
130	0.725	53.2	7.3	18.8	0.54

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The Ag or Ni deposition on an Cu loaded graphite layer back-contact enhanced the device stability.⁴⁵⁷ In the absence of graphite, the Ag contact was susceptible for degradation due to the rapid diffusion of Ag and by the formation of metastable resistive shunts. Ni was plagued by Ni₃Te₂ phase formation that minimized Ni diffusion contributing to the loss of FF. A modest degradation (10–15% reduction in efficiency) was observed with a graphite layer, while there was a significant loss in efficiency (25–45%) for Ag and Ni contacts without a graphite layer. In addition, LBIC studies revealed the formation of micro non-uniformities with stress in Ag- or Ni-only devices, resulting in ohmic microshunts and poor collection of charge carriers due to the diffusion of these metals. Thus, the graphite layer served as a diffusion barrier preventing the migration of these metals from the back contact. The graphite paste contained polyacrylic acid (PAA) polymer at 70% by weight when dried. PAA is a “super absorbent polymer” and is used in cation exchange resins because the acidic hydrogen on the carboxylic functionality can be readily exchanged with several metal cations. The Ag and Ni cations are known to exchange quite readily, and hence the ability of PAA to bind metal cations must be the underlying reason for the enhanced stability of solar cells.⁴⁵⁷ The device with graphite/Ag (or Ni) showed a similar initial performance of 66% FF, which was reduced in the absence of a graphite layer (Fig. 34). The net current density estimated via C–V measurements for only Ag as the back contact is twice compared to others even before and after stress (Fig. 35). In the case of other back contacts like graphite/Ag, graphite/Ni and only Ni devices, a Te-rich interlayer between CdTe and back contacts effectively “getters” Cu from the graphite paste mixture in the course of annealing and serves as a source of Cu with subsequent stress. However, this finite (200–300 nm) Cu source outdiffusion is augmented by a much larger source of Ag in the form of a very thick (50–100 μm) Ag paste layer for an Ag-only contact. This constant replenishment of Ag into the device is likely to be responsible for the smaller decrease in carrier density with stress in the Ag-only case.⁴⁵⁷

Fig. 34 Fill factor and efficiency as a function of light illumination stress time for devices with different back contact; graphite/Ag (–●–), graphite/Ni (–○–), Ag only (–■–) and Ni only (–□–) (reprinted with permission from ref. 457; copyright @ 2006 Elsevier).

Fig. 35 (a) Capacitance versus voltage measurement, and (b) carrier density as function of distance from the junction before and after 707 h of stress (reprinted with permission from ref. 457; copyright @ 2006 Elsevier).

A low R_s and high FF was achieved for the large area thin film (1376 cm²) solar cell submodule with CdTe thickness of 3–5 μm and an Ag paste loaded graphite back electrode. For a CdTe thickness of <3 μm, pinholes occur, leading to a higher leakage current with a drop in FF and V_oc.⁴⁵⁸ High quality and uniform film thickness of the TCO, CdS and CdTe layers contribute to an efficiency of 10.5 and 8.4% for a large-area sub-module with aperture area of 1376 and 5413 cm², respectively. The major cost reduction for this cell comes from the development of TCO film preparation technology, APCSS techniques to obtain the CdTe film and a patterning technology for large-area substrates.⁴⁵⁸ In another study, a CdTe thin film prepared by APCSS had a large grain size and less crystal defects compared to those grown under vacuum conditions.⁴⁵⁹ The CdTe film deposited from a dry milled powder source on CdS film showed a better efficiency compared to conventional sources due to the decreased Te and oxygen content in the powder after dry-milling in air for 4 h. Milled CdTe powder is well suited for APCSS as better nucleation and a large grain size CdTe is obtained. In this cell structure, a graphite carbon paste with 7 wt% carbon black powder resulted in a low back contact resistance with a high FF and V_oc (Fig. 36). This suggests that carbon black powder enhances the ohmic contact between the CdTe surface and graphite carbon layer. The best cells were obtained from Cu and Pb doped graphite paste containing a mixture of 7 wt% carbon black glass flints mixed in a solvent. By this fabrication, solar cells with efficiencies in the range of 14–15% were obtained over a small area of 1 cm², while 11% was achieved for large area (5327 cm²) modules.⁴⁵⁹ This high efficiency was attributed to the high quality of the CdTe/CdS junction and the stable back contact. In these cells, the density of carbon black powder in the graphitic carbon paste for screen printing is a key factor in reducing the R_s with a rough CdTe surface. The APCSS have a few detrimental aspects for low cost PV production such as: (i) a high interdiffusion rate of CdS and CdTe during deposition; (ii) a high temperature resistive glass is required due to high deposition temperature; (iii) a longer deposition time is needed for APCSS compared to vacuum deposition.⁴⁵⁹

Fig. 36 Variation in the device characteristics with carbon black density in graphite paste (reprinted with permission from ref. 459; copyright @ 2003 Elsevier).

Conductive graphite paste is a good back contact material for CdTe/CdS solar cells. The work function of graphite nearly matches that of CdTe and the highly polarized valence orbitals of Te (6s & 6p) have an intense chemical interaction with the delocalized C 3p_z orbitals.⁴⁶⁰ The CdTe generates a hole and this transfers to the graphite electrode in the solar cell. Though the doped graphite back contact serves as diffusion barrier for Cu migration,^379,461 graphite is relatively low-conducting due to its anisotropic electrical conduction. The hole conductivity perpendicular to the graphite layer (30–50 S cm⁻¹) is much smaller compared to in-plane conductivity (10⁶ S cm⁻¹) leading to low carrier collection and high back contact resistance,⁴⁶² reflecting the weaker interaction between layers (van der Waals forces with a slightly delocalized π to π* interaction). In this context, graphene has recently attracted tremendous attention compared to other carbon based back electrodes due to its robust characteristics, such as exceptional electron/hole carrier mobility and high mechanical strength. Graphene has only in-plane conductivity and multilayer graphene with a perfect hexagonal carbon lattice is expected to have a lower electrical conductivity along the c-direction (perpendicular to graphene layer) than normal graphite.⁴⁶⁰

The cell parameters obtained for reduced graphene oxide (r-GO), pristine graphene (PG) and boron doped graphene (BG) highlight that BG serves as an efficient back contact (Table 11).⁴⁶⁰ The PG prepared by a bottom-up approach had fewer defects with a better electrical transport performance than the chemically reduced exfoliated graphene oxide sheets, as evidenced by Raman spectroscopy. The BG had even higher electrical resistance and a higher work function than PG due to the larger density of states generated near the Fermi level. It is known that the Fermi level of graphene doped with 2 atom% of boron and nitrogen shifts by −0.65 and +0.59 eV, respectively.⁴⁶³ Thus, boron doping increased the hole concentration in the VB of the graphene sheet and a large carrier concentration together with a shift in absolute Fermi level was achieved. As an electron deficient dopant, boron increases the work function of graphene allowing it to serve as a better ohmic contact. As expected, the BG cell had higher efficiency of 7.86% indicating that a highly conductive BG can reduce the barrier height to enhance the efficiency.⁴⁶⁰ However, integrated graphene-based back electrodes still exhibits poor electrical conductivity due to the large resistance from the interface of submicron graphene sheets limiting the charge carrier collection. Further improvement up to 9.1% was achieved with the use of a highly crystalline 3-layer graphene (5 wt% Cu doped graphene) electrode prepared on 3D template Ni foams by the APCVD method (Fig. 37).⁴⁶⁴ The graphene sheets in the graphene network are interconnected into 3D flexible graphene networks, which eliminate the contact resistance from GBs and promote electrical conductivity. The assembled graphenes exhibit outstanding electrical properties and their conductivities reached up to 550–600 S cm⁻¹. This efficiency remained the same during measurements over a two-month period, which highlights the excellent reproducibility and device stability.⁴⁶⁴ Feng et al.⁴⁶⁵ reported a device with a novel 1D Cu nanowire (NWs)/3D graphene back contact with an efficiency of 12.1% compared to the traditional back contact of Cu-nanoparticle-doped graphite (10.5%) and Cu thin films (9.1%). This high efficiency was due to the giant 3D network of graphene, which supplies a more effective hole transportation channel and efficient back contact. In addition, 1D Cu NWs of 100 nm have a large specific surface area and interact effectively with Te atoms to form a stable intermediate layer. In such a situation, a tunnel current conduction mechanism dominates in which the tunnel current increases sharply and overcomes the loss of holes from the barrier. In fact, the formation of stable CuTe at the interface of Cu NWs and CdTe benefits this back contact from the point of thermal stability, while Cu diffusion via the thermal field into the p–n heterojunction reduces the device performance with other back contacts.⁴⁶⁵ Interestingly, the Cu_xTe intermediate layer attached to Cu NW/graphene exhibits a CuTe phase with a preferred {001} peak, while those attached to other Cu-doped back contacts showed a Cu_1.44Te phase with a {002} peak. The electrical conductivity (16.7 S cm⁻¹) and the carrier mobility (16.2 cm² V⁻¹ s⁻¹) of Cu (NW)/graphene were higher than Cu particles/graphene and Cu particles/graphite. The cells with Cu NW/graphene were more sensitive to the visible light response (560–685 nm) and QE reached ∼86.5% at 620 nm, while it was reduced to 85.2% for Cu particles/graphene at the same position. However, no such peaks were observed for Cu particles/graphite and Cu thin films. The high QE in the visible light range was ascribed to the highly conducting Cu NWs/graphene that effectively capture holes from CdTe absorber due to the formation of a CuTe phase.⁴⁶⁵ These results suggest that the graphene-based conducting materials can be explored as novel low cost back electrodes for CdTe/CdS devices in near future.

Table 11 Photovoltaic performance of r-GO, PG, and BG based CdTe solar cells (reprinted with permission from ref. 460; copyright @ 2011 Royal Society of Chemistry)

Back electrode	J sc/mA cm^−2	V oc/V	FF (%)	η (%)
r-GO	18.38	0.685	51.6	6.50
PG	20.81	0.674	52.9	7.41
BG	21.96	0.685	52.2	7.86

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Fig. 37 (a) SEM cross-sectional image and top-view of the graphene film in the inset. (b) Schematic CdTe/CdS solar cell with a 3D graphene back electrode. (c) Band structure of the graphene-based CdTe/CdS solar cell. (d) J–V characteristics of CdTe/CdS solar cell with graphene back electrode (reprinted with permission from ref. 464; copyright @ 2011 Royal Society of Chemistry).

The J–V curves showed that roll-over in dark and light in forward-bias conditions due to the high back barrier formed between CdTe and Ni layer, while the addition of a 1.2 μm Te layer eliminated the roll-over.¹⁵⁵ Though the Te layer was found to increase the efficiency (8 to 10%) and FF (0.35 to 0.55) but lower the V_oc (0.82 to 0.74 eV). The current density reached a maximum of 24.8 mA cm⁻² as it diminishes the hole injection from the back contact. These cells had a superior current because of their higher blue photosensitivity but an inferior V_oc in relation to the absorption band gap.¹⁵⁵ Annealing with Ni or NiTe₂ as back contact improved the I–V characteristics compared to as-deposited cells and an efficiency of >10% was reported. These cells were susceptible to reversible degradation under storage in ambient air (H₂O vapor) and remained stable in dry air. SIMS investigation revealed that Ni movement or accumulation into the device was not observed after thermal stress (200 °C in air for 20 h).⁴⁶⁶ NA etching improved the FF compared to NP etching due to a smaller series resistance for the device. As a result of the sharp boundary layer by NA etching, a less-extended Cd deficient CdTe boundary layer is formed at the interface region leading to efficient tunneling between CdTe and the Au back contact.¹⁷³

6.8.2 Sb₂Te₃ buffer layer/metal back contact. Sb₂Te₃ is a stable compound having a forbidden energy gap of 0.3 eV (p⁺ type) and is a degenerate p-type semiconductor with a very low resistivity (10⁻⁴ Ω cm). The work function of p-type Sb₂Te₃ lies in the range of 5.12–5.8 eV, which matches with CdTe and hence a stable ohmic contact can be expected.⁴⁶⁷ The Sb_Cd⁺ donors segregate in GBs, which may compensate V_Cd in p-CdTe and also lead to a higher Fermi level for CdTe with Sb₂Te₃ after annealing. In addition, Sb_Cd⁺ donors in GBs cause Coulombic repulsion to holes from the grain bulk to reduce recombination. The Sb impurities accumulated in CdTe grain diffuses rapidly into the CdTe layer and more photogenerated carriers are separated by segregated Sb_Cd⁺ donors into the GBs. The Sb_Cd⁺ compensates holes in the bulk CdTe grains and thus the hole concentration in the grain bulk decreases.⁴⁶⁷ In addition to its facile preparation, it eliminates the need for a surface etching process for CdTe film prior to back contact formation.

Romeo et al.²⁷⁴ fabricated a novel solar cell with an Sb₂Te₃/Mo back contact, which exhibited 74% FF with a conversion efficiency of 14.6%, while 62% FF was observed without CdCl₂ treatment. It has been speculated that CdTe grown on an untreated CdS surface results in a poor junction because the smaller CdS crystallite exposes a large surface for CdTe nucleation thus allowing slow transition of CdS to CdTe. A fine grained CdS film can easily mix with CdTe to form CdS_1−xTe_x resulting in a buried homojunction. After treatment with CdCl₂, good morphology and compactness favors the formation of a junction, which develops in a few layers with a very small concentration of interface states. CdCl₂ with a thickness of 3000 Å deposited by evaporation and annealed for 30 min at 430 °C showed a superior performance compared with other CdCl₂ thicknesses. On the other hand, Sb diffuses slightly into the CdTe matrix making a thin p⁺ CdTe layer in contact with a low resistivity Sb₂Te₃ film thus facilitating the formation of an ohmic contact.²⁷⁴ These cells did not show any appreciable degradation during a test period of 6 months when kept at 60 °C under 10 suns in open circuit conditions.¹⁷⁴ In another study, a solar cell with an Sb₂Te₃/Au back contact exhibited an efficiency of 13.1% after annealing compared to as-deposited (9.0%), despite the high barrier for hole transport in the former (0.4 eV) against the latter (0.28 eV).⁴⁶⁷ This efficiency was ascribed to the band-bending from the Sb_Cd⁺ donor at grain boundaries that facilitate charge carrier separation in the vicinity of GBs. The electrons are drawn into the GB core and flow towards the junction, while holes are transported through the grain bulk towards the back contact. This charge separation leads to reduced recombination and enhancement in the collection of photogenerated charge carriers. In addition, a slight amount of Sb diffuses to the vicinity of the CdTe/CdS heterojunction forming substitutional Sb_Te⁻ acceptors at the Cd-rich limit, which reduces the barrier height for the CdTe thin film. Alternatively, Sb diffuses and substitutes for Cd atom to form Sb_Cd⁺ donors at the Te-rich limit.⁴⁶⁷ The device containing a fast diffuser like Cu, Al or Au was susceptible to degradation, while cells with Mo metallization were stable when a buffer layer of Sb or Sb₂Te₃ is applied. The diffused impurities tend to accumulate in CdS and at the front contact of the TCO–CdS interface, thus changing the electrical properties of the junction and shunts in extreme cases.¹¹⁶ The cell efficiency with an Sb₂Te₃/Mo back contact increased during the first 5 months of testing, relatively, by 10%. This can be attributed to the light soaking effect and changes at the back contact interface facilitating a better contact, as supported by I–V analysis. After 9 months of testing, although device performance declined it still remained above 4% of its initial efficiency. In contrast, cells with an Sb/Mo back contact suffered from severe degradation attributed to the oxidation of the back contact and increase of the barrier height.¹¹⁶ Matin et al.⁴⁶⁸ proposed that 1.0 μm CdTe, 50 nm CdS, 100 nm of buffer layer and 100 nm of BSR was sufficient to produce an efficiency of 15% with reasonable stability. The cell structure with an i-ZnO buffer layer and ZnTe BSR layer with an Al back contact showed better stability and achieved the best performance, with a linear thermal coefficient of −0.25% per degree Celsius, while it was −0.40% for the Sb₂Te₃/Mo contact.

It is reported that CdTe/Sb₂Te₃ is in thermodynamic equilibrium and no reaction occurs resulting in long term stability from a chemical point of view. However, metallization with Ni:V alloys enhanced the electrical barrier, consequently reducing the efficiency. This is because the Ni/Sb₂Te₃ interface was not in thermodynamic equilibrium and spontaneous reactions led to NiTe_x, NiSb_x and Sb₂O₃ at the interface.⁴⁶⁹ Based on thermodynamic considerations, it was deduced that Sb₂Te₃ tunnel contacts offer no reliable chemical stability in combination with back contact metals. The NiTe₂ was identified as a crystalline product due to the diffusion of Ni and its tendency to form alloys with the Sb–Te phase or Sb₂Te₃. Thus, Ni will reach the absorber and the intermediate telluride layer is consumed and tunnel contact is destroyed. On the other hand, Mo/Sb₂Te₃ is found to be chemically stable and the Mo may not have a high diffusion velocity to create a reaction zone to form any alloy. Thus, Sb₂Te₃ tunnel contacts combined with Mo will be suitable back contact systems for long term stability.¹³² Alternatively, the formation of high trap densities within the CdTe bulk material affects adversely the internal electric field distribution, if Mo diffuses through Sb₂Te₃ and penetrates into the absorber layer.¹³¹ Though Sb₂Te₃ can be successfully used as a Cu-free back contact, its stability and resistivity are highly dependent on processing conditions and materials purity, and the doping effects of these tellurides can be further complicated by the dopant compensation, as reported for Sb in a CdTe matrix.⁴⁶¹

6.8.3 MoO_x buffer layer/metal back contact. The solar cell with an MoO_x/Ni back contact deposited on FTO soda lime glass showed a high efficiency of 12.2% for an MoO_x thickness of 40 nm along with excellent FF (80.4%) and V_oc (816 mV) via completely eliminating the roll-over effect that was otherwise observed with an Ni only back contact (Table 12).⁴⁷⁰ The choice of MoO_x lies in its high work function (Φ_s = 6.80–6.86 eV) and ease of preparation by vapor deposition method.^471,472 The J–V behavior of MoO_x/Ni was almost similar to an NP etch/Ni back contact indicating the formation of a good ohmic contact to p-CdTe. In contrast, NP etch/Al was found to be highly non-ohmic. The excess coverage of MoO_x (80 nm) introduces additional R_s, as MoO_x is essentially an insulating material. The cell stability was increased since MoO_x buffer served as a barrier for Ni diffusion into CdTe, which otherwise results in device degradation.⁴⁷⁰ In the absence of MoO_x, Ni deposition reduces tellurium oxide content from the surface with consequent lowering of surface work function resulting in non-ohmic contact.¹²⁵ The CdTe films rinsed with water and then dried under N₂ flow prior to MoO_x/Ni back contact showed 71.4% FF, while those cells fabricated without water rinsing suffered from severe roll-over (FF 47.4%).⁴⁷³ This suggests that the water rinsing step removes the surface residues from CdTe prior to MoO_x deposition. The ohmicity of CdTe/MoO_x is largely controlled by the deposition of first few monolayers of MoO_x on CdTe surface. The existence of a thin residual layer compensates substantially the work function of MoO_x resulting in roll-over. It was proposed that water soluble and chlorine containing residues will be completely removed by rinsing CdTe with water. The MoO_x produced by thermal evaporation showed normal J–V characteristics, while those prepared by sputtering exhibit roll-over attributed to a reduction in work function of MoO_x from 6.8–5.9 in the latter.⁴⁷³ The MoO_x prepared by thermal evaporation is transparent and shows little absorption in the visible region with stoichiometric composition, while a mixture of Mo⁶⁺ and Mo⁵⁺ was found for sputtered MoO_x. The efficiencies in the range of 11.5–12.9% were observed for various metals like Ni, Mo, Cr, Al and Mg and no direct correlation of efficiency with the work function of metals could be derived. Regardless of metals, device stability decreased for vacuum annealing (200 °C) at 4.5 h and the net effect remained almost constant up to 19 h (Fig. 38).⁴⁷³ The cells with Mo and Ni electrodes were stable while Cr and Al were found to be least stable due to the reactivity of the back contact metal with the MoO_x buffer layer. Such reaction leads to partial reduction of MoO_x and lowers its work function. The severe instability associated with the Al back contact is related to its large standard enthalpy of formation for Al₂O₃ (−1675.7 kJ mol⁻¹) compared to MoO₃ (−745.1 kJ mol⁻¹) favoring the abstraction of oxygen from MoO_x in contact with Al, while the stability of Ni and Mo are consistent with a lower standard enthalpy formation for their oxides. The thermal and light soaking stability improved with a high work function MoO_x buffer, as it served as a diffusion barrier to minimize the interaction of the metal electrode with CdTe.^474,475 However, MoO_x is highly sensitive to surface contamination as the air exposure of MoO_x after its deposition reduces the work function from 6.80–5.24 eV.⁴⁷²

Table 12 Photovoltaic parameters of CdS/CdTe solar cells with MoO_x/Ni back contacts. “NP” designates a control cell without MoO_x but pretreated with NP etch (reprinted with permission from ref. 470; copyright @ 2010 American Institute of Physics)

MoOx/nm	J sc/mA cm^−2	V oc/mV	FF (%)	η (%)	R s/Ω cm^2
0	19.9	701	60.2	8.4	16.6
1	20.1	786	63.9	10.1	9.9
5	20.1	810	68.0	11.1	5.6
10	20.8	808	68.9	11.6	5.2
40	21.3	816	70.4	12.2	4.7
80	21.0	800	64.7	10.9	5.9
NP	20.4	795	66.4	10.8	5.8

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Fig. 38 Degradation of cells with different back contacts under vacuum annealing at 200 °C for 4.5 h (reprinted with permission from ref. 473; copyright @ 2012 Elsevier).

6.9 Bifacial solar cells

Bifacial solar cells (ITO/CdTe/CdS/FTO/glass) displayed 7.9 and 1% efficiency for front and rear side illumination respectively. The lower efficiency for back illumination, was due to poor charge carrier collection that were photogenerated far away from heterojunction. In addition, this device was stable compared to standard solar cells with an Cu/Au back contact that were otherwise susceptible to degradation.⁴⁷⁶ The reduction in the thickness of CdTe to 2.5 μm showed an efficiency of 10.3 and 2.1% for front and back illumination, respectively. The efficiency at back illumination increased to 3.2% and reduced to 8% for the front side with a further decrease in CdTe thickness to 1.0 μm.²³⁷ The glass/SnO₂:F/CdS/0.68 μm thick CdTe/ZnTe:N/ITO device exhibits efficiencies of 5.7 and 5% for glass and contact side illumination, respectively.⁴⁷⁷ The QE with glass and contact side illumination showed a higher response at 600 and 800 nm, respectively, which was explained by the wavelength dependence of absorption coefficient, illumination side and position of the junction. For the QE curve with glass side illumination, light must pass through glass, SnO₂:F and CdS inducing optical losses at 400–500 nm due to CdS absorption. However, light will first pass through ITO and then to ZnTe:N (2.2 eV) without any QE onset at 560 nm or below for contact side illumination. Thus, it can be assumed that generation and collection of the charge carrier pair takes place from this layer, which induces higher QE compared to glass side illumination at lower wavelength. Since most of photons are absorbed near the back contact far away from the junction, assisted by a weak electric field region, these carriers are more sensitive to back surface recombination.⁴⁷⁷ The I–V characteristics recorded upon illumination of the front side for glass/SnO₂:F/CdS/CdTe/Cu/ITO varied insignificantly for all 8 years of testing compared to starting state. However, I_sc was increased by a factor of 2 and additional inflection point appeared in I–V studies compared to the starting state for rear side illumination.⁴⁷⁸ This difference was accounted for, by the degradation process taking place at the back contact as Cu diffuses over the GBs and shunts the rear barrier due to an increase in the conductivity of GBs. This process decreases the R_s, the main contribution of which was made by a weakly illuminated depletion region of the rear barrier. In this case, shunting of the rear barrier also leads to an increase in its diode saturation current causing inflection points in the I–V curve when illuminated from the rear side.⁴⁷⁸ These bifacial photovoltaics are attractive for tandem solar cells and its configuration is beneficial for industrial in-line production and also suitable for roll-to-roll manufacturing of solar modules.

7. Effects of preparative methods on device performance

The efficiency in the device was governed by the S/Cd ratio in CdS preparation by the CBD method.⁴⁷⁹ A maximum efficiency of 12.3% was observed for S (thiourea)/Cd (CdCl₂) ratio of 5.0 compared with other S/Cd ratio of 1, 2.5 and 10 whose efficiencies were 7.1, 8.3 and 5.4% respectively. The QE reached a maximum for S/Cd = 5 at the lower wavelength region due to the formation of CdTe_1−xS_x alloy (Fig. 39), while it was not changed in the longer wavelength region. The PL studies revealed that for a S/Cd ratio <5, sulfur goes into the CdS GBs, while the amount of interstitial S decreases due to sulfur precipitation into the solution for a S/Cd ratio >5. Hence, CdS deposition with varied S/Cd content affects the interface characteristics between CdS and CdTe as well as the absorption coefficient of CdS without modifying the bulk properties of CdTe. The cell degradation decreased from 70 to 17% with change in the S/Cd ratio from 3 : 1 to 7 : 1.⁴⁸⁰ The maximum degradation (80%) was observed for an S/Cd ratio of 8 : 1 and the best efficiency was achieved for an S/Cd ratio of 5 : 1 (and 6 : 1). The J–V curve did not show any saturation effect for a fresh device, which is an indication of an acceptable R_s for the device. This cell was kept in an open environment for a period of 36 months. The decrease in efficiency was related to oxidation or chemical changes at the surface leading to changes in shunt resistance together with Cu segregation through the grain boundary of CdS and CdTe (Table 13).⁴⁸⁰ The efficiency was reduced to 11.2 and 6.3% for CdS grown by CSVT,^481,482 due to the larger R_s for CSVT-CdS compared to CBD-CdS solar cells. It was shown that sulfur enrichment in the CBD-CdS layer reduces carrier density at GBs.⁴⁸² Thus, larger photoconductivity of the CBD-CdS layer may result in better FF. The spectral response indicated an efficient interface between CBD-CdS and CdTe compared to CSVT-CdS and CdTe, though J_sc is almost same for both the solar cells.⁴⁸¹ Using photoacoustic spectroscopy, it was shown that the charge carrier recombination velocity is 2.0 ± 0.3 × 10³ cm s⁻¹ at the CdS–CdTe interface for this optimum concentration (S/Cd = 5)⁴⁸² indicating a low density of recombination carriers are available at the interface. In addition, the properties of the CdS layer are correlated with the kinetics of the deposition process with change in thiourea concentration; a low thiourea concentration causes very slow growth leading to a thinner but more homogeneous layer with optimum characteristics. For higher concentrations (S/Cd = 6), the reaction rate becomes progressively large enough to promote quick CdS precipitation resulting in the formation of agglomerates in the solution rather than nucleation on the substrate surface affecting the interface characteristics.^482,483 The CBD-CdS showed following characteristics with increase in S/Cd ratio: (i) optical transmittance above threshold increased from 68–72%; (ii) high resistivity in the dark but with a large photoconductive gain; (iii) grain size becomes smaller from 55.4–47.2 nm;⁴⁸³ (iv) diode factor decreased from 2.9–2.1; (v) band gap values increased from 2.45–2.52 eV. The higher band gap improves the I_sc, while the small grain size will have fewer pinholes. All these properties account for enhancement in the solar cell performance.^479–484 The unique advantage of the CBD technique for depositing CdS is that very thin films (60–80 nm) can be deposited with a uniform surface coverage and low pinhole density. In addition, an absorption coefficient of CBD-CdS will be lower compared to films deposited by other methods having the same thickness.⁶⁰ In contrast to the above results, efficiency with CBD-CdS layers (150 nm) was as low as 5–6% compared to HVE-CdS layers (300 nm) of 12.3%.³⁹⁷ The surface texture remained smooth before and after vacuum annealing for CBD-CdS and changed from rough to smooth for HVE-CdS. The junction activation step reduced the efficiency from 12.3 to 11.2% due to excess intermixing of CdTe and CdS, as evidenced by a large decrease of the CdTe lattice parameter from 6.499 to 6.446 Å after CdCl₂ treatment.³⁹⁷ In another study, a device with CSS-CdS showed a high efficiency (9.63%) compared to CBD-CdS (8.24%).⁵⁹ The XPS analysis indicated that the Fermi level of the CSS-CdS film is closer to the CB than that of CBD-CdS. The increased n-doping of the CdS layer leads to a higher position of the Fermi level, which results in sufficient band bending at the CdTe side. Thus, the built-in potential of the CdTe film was increased and a higher V_oc was obtained. In addition, higher n-doping of the window layer can extend the depletion width in the CdTe layer increasing the photocurrent collection. The other reasons were the better crystallinity, higher optical transmittance and less recombination near the interface between CdTe and CSS-CdS.⁵⁹

Fig. 39 Internal quantum efficiencies for CdTe/CdS solar cells with different thiourea/CdCl₂ (R_tc) ratios in the CBD-CdS (reprinted with permission from ref. 479; copyright @ 2006 Elsevier).

Table 13 Cell parameters and percentage degradation of the cell with various S/Cd ratios over a measurement period of 36 months; October 03–December 06 (reprinted with permission from ref. 480; copyright @ 2009 Elsevier)

S/Cd	V oc/mV	J sc/mA cm^−2	FF (%)	η (%)	Degradation
3 : 1	0.613–0.528	18.7–10.2	0.58–0.33	6.7–1.9	70
4 : 1	0.74–0.623	18.7–10.9	0.70–0.62	9.8–4.3	55
5 : 1	0.745–0.649	21.4–17.0	0.70–0.46	11.1–5.4	51
6 : 1	0.746–0.64	20.2–16.4	0.73–0.57	11.1–6.0	44
7 : 1	0.73–0.649	18.4–17.6	0.62–0.60	8.4–7.0	17
8 : 1	0.524–0.450	18.4–5.7	0.57–0.41	5.5–1.1	80

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The CdTe deposited by MOCVD under a Te-rich ambient resulted in 11.9% efficiency, while those fabricated under Cd-rich conditions were <6% only.¹⁴⁰ The monotonic increase of V_oc while going from a Cd-rich to Te-rich ambient suggests the improvement in interface quality as a result of atomic interdiffusion, which was beneficial for reducing the lattice mismatch or gradual transition of CdS to CdTe with fewer interface states. Carrier transport analysis showed that transport mechanism switches from tunneling/interface recombination in Cd-rich cells to depletion region recombination limited transport in Te-rich cells.¹⁴⁰ Based on XPS, SIMS and optical reflectance measurements, it was concluded that high efficiency devices possess a Te-rich CdTe surface (Cd/Te ratio < 1 or 0.85) with smooth interfaces, while low efficiency cells displayed near stoichiometric or Cd-rich CdTe surfaces and abrupt interfaces (Cd/Te ratio >1).²⁸⁶ The well-defined interference fringes due to abrupt interfaces result in multiple reflections from parallel CdTe layers for low efficiency devices, while such interference fringes were completely absent for high efficiency cells. Since the reflectance coefficient R = [(n₂ − n₁)/(n₂ + n₁)]² at the abrupt interface between the two materials, gradual variation between CdS–CdTe and SnO₂–CdS leads to a gradual variation of the refractive index from SnO₂ to CdS and CdS to CdTe, which could decrease the reflectance loss as light passes through the glass–SnO₂–CdS–CdTe layers and increases the solar cell efficiency. The decrease of optical loss due to gradual change in refractive index is a dominant factor that improved the efficiency in these PV devices.²⁸⁶

8. Effects of particle irradiation on device efficiency

One of the important requirements of solar cells for possible space or satellite applications is the stability against high energy particle irradiation, which is incident on the device material, creates dislocations, displaces atoms from their lattice sites, and introduces electronic traps within the band gap. This reduces carrier concentration, mobility and lifetime leading to a gradual deterioration in performance over a period of time.^485,486

The effect of 8 MeV electron irradiation of solar cells exhibits different behavior depending on doses ranging from 0.1 to 100 kGy at RT.⁴⁸⁷ At a very small dose of 0.1 kGy, an enhancement in efficiency was observed due to an increase in minority carrier lifetime in the base region caused by the passivation of recombination centers.⁴⁸⁸ Above 0.1 kGy, the efficiency was reduced without much change in FF and V_oc. Optical absorbance studies revealed that the solar cells turned brown after irradiation and this darkening increased with electron dose up to 25 kGy, beyond which darkening did not change much with dose. This darkening process was due to ionization followed by the creation of color centers in the glass by 8 MeV electrons.⁴⁸⁷ Batzner et al.⁴⁸⁹ and Romeo et al.⁴⁹⁰ have reported similar results for solar cells on glass substrates irradiated with electrons of 1–3 MeV and protons of 5–15 MeV. Thus, irradiation also induces ionization damage in the glass giving rise to color centers enabling photon absorption in the glass itself causing the additional optical loss. Hence, it can be concluded that a low efficiency of superstrate devices upon irradiation may also be due to darkening of the glass and not necessarily associated with device degradation.⁴⁸⁷ Both the diode ideality factor and reverse saturation current increased above 10 kGy electron dose, indicating the stability against electron irradiation (Fig. 40). The R_s decreased up to 10 kGy and drastically increased thereafter. The cell degradation above 10 kGy was ascribed to decrease in minority carrier diffusion length as a result of radiation-induced defects. There was a marginal difference in the decrease of capacitance for unirradiated (26.7–9.13 nF) and irradiated (26.7–8.65 nF) samples with the frequency at 1 V suggesting that irradiation did not significantly contribute to the concentration of deep level defects at the interface.^486,487 For the solar cells developed at ETH Zurich, protons of 650 keV were most damaging, and less damage resulted from 1 and 2.2 MeV protons (Fig. 41), which is in accordance with NIEL estimates (for protons, NIEL is higher for lower energies).¹¹⁶ Proton irradiation has no effect on the efficiencies for low fluencies up to 10¹¹ cm⁻². The efficiencies are lost followed by a decrease in J_sc at higher fluencies because of increased recombination density. In contrast, degradation was weakly affected by electron irradiation.¹¹⁶ The use of space quality CeO₂ doped glass, which remains transparent even after irradiation, would be beneficial to overcome this problem.

Fig. 40 Reverse saturation current and ideality factor of CdTe/CdS solar cell as functions of electron irradiation dose (reprinted with permission from ref. 487; copyright @ 2009 Elsevier).

Fig. 41 Relative efficiencies of the irradiated CdTe cells as a function of the proton fluence (reprinted with permission from ref. 116; copyright @ 2004 Elsevier).

9. Innovative cell structure

The inverted p–n junction between n-CdTe/p-diamond exhibits an internal QE of 70% at 500 nm (ignoring the reflection and absorption losses of the diamond film). The junction formation between diamond/CdTe results in interface states and dislocations disturbing the photocurrent to some degree.⁴⁹¹ The n-CdTe/p-diamond film showed a built-in voltage of 1.0 eV at the junction, comparable to a CdTe/CdS solar cell. The J–V characteristics in the dark behave like a rectifying diode with an ideality factor of 1.23 at 0.1 V. Under illumination, the device produced a V_oc, J_sc and FF of 0.23 V, 1.54 mA cm⁻² and 0.32, respectively. The external QE measured was 10% for green light at 500 nm and reduced to zero at the absorption edge of 840 nm, indicating a high degree of recombination in the CdTe bulk and low transmittance of the diamond film (Fig. 42).⁴⁹¹

Fig. 42 (a) J–V data for the p-diamond/n-CdTe inverted heterojunction solar cell in the dark and under illumination. (b) Spectral response of the diamond/CdTe solar cell (reprinted with permission from ref. 491; copyright @ 2001 Elsevier).

Coating of FCA on a solar cell makes it sensitive to light at wavelengths <510 nm and transforms the wavelength of incident light from the non-incentive (<510 nm) to the incentive region (>510 nm).⁴⁹² The hemispherical reflectivity of an FCA coated solar cell increased in the wavelength region of 400–500 nm, attributed to the increase of scattering as a result of isotropic emission of fluorescent light. The maximum output power increases to 8 and 14% upon illumination with white light and daylight fluorescent lamps, respectively. This difference is because the light energy at wavelengths <510 nm is larger in the latter case compared to the former. Although FCA did not degrade the cell, it is unsuitable for practical purposes.⁴⁹² The PV conversion efficiency was increased by 5% for the solar cell with KMgF₃:Sm (0.8 mol%).⁴⁹³ This PV composite resulted in a spectral response in the short wavelength region <500 nm due to the broad and strong f–d transition bands in KMgF₃:Sm. It was emphasized that thin disc crystal of KMgF₃:Sm placed on top of CdTe/CdS did not effect FF and V_oc, because the wavelength conversion changes only the distribution of incident photon flux to connect directly with the generation of carrier densities and results in I_sc enhancement without changing the diode properties.⁴⁹³

To improve the performance further, device fabrication involving nanostructure materials based on nanopillars, nanowires, nanotubes and nanorods are explored. The solar cell with quantum confinements in both window and absorber layer showed a V_oc and J_sc of 112 mV and 10 nA cm⁻² for a light density of 2.22 mW cm⁻².⁴⁹⁴ Interestingly, J_sc showed a gradual increase with an increment in light intensity from 2.22–6.6 mW cm⁻² without change in V_oc. The low efficiency of this solar cell was attributed to intrinsic defects in CdS nanoparticles, as evidenced by both PL and Raman studies. Also, the large surface area of small nanoparticles resulted in substantial diffusion of Te from CdTe to CdS, affecting the junction properties. A new innovative structure with a single crystalline 3D n-CdS nano pillar embedded in polycrystalline p-CdTe exhibits a V_oc of 0.62 V and 6% efficiency without the use of antireflective coating or concentrators.⁴⁹⁵ The conversion efficiency monotonically increased with CdS nanopillar length (H). Interestingly, an efficiency of 0.4% was observed for H = 0. In such a case, only the top surface of CdS nanopillars will be in contact with the CdTe film and hence the small space charge region is obtained with a low carrier collection efficiency. Most of the carriers recombine in the CdTe film via non-radiative pathway at defect-rich GBs. By increasing H (640 nm), the space charge region is effectively increased with improved carrier collection efficiency. The deposited Au/Cu thin layer has a very low transparency (50%), which resulted in major optical losses and low performance.⁴⁹⁵ The application of CdS nanowires (CNW) embedded in an anodic aluminium oxide-AAO (device A) exhibited an efficiency of 6.5%, whereas the device fabricated only with CNW (device B) had 5.1%.⁴⁹⁶ For the device A, J_sc and V_oc marginally decreased with change in nanowire length from 200–100 nm, while a drastic decline was observed for device B (Fig. 43). The residues and foreign materials present in the gaps between nanowires of device B would cause shunting paths, accounting for its lower efficiency. The presence of AAO will cover the pinholes in CdS preventing the interaction of CdTe with ITO, resulting in low shunting paths. This novel device has following features: (i) the optical absorption edge of CNW lies at 480 nm instead of 512 nm (bulk CdS), which enhances the number of solar photons incident on CdTe absorption layer and increases the light generated current; (ii) CNW are embedded in insulating AAO with much a higher optical transmittance and enable CdTe to absorb more photons (the calculations revealed that 17% improvement in J_sc could be expected); (iii) CdS forms a junction with CdTe only at the top end of CNW. Thus the interface junction area will be typically small resulting in small I₀ and large V_oc.⁴⁹⁶ Though the efficiency for reported nanostructured devices are smaller than traditional solar cell designs, they are expected to surpass the Shockley limit when the technology matures and the physics behind the size quantization effects becomes more clear and deeper. The 3D configuration of the window layer can relax the materials requirements in terms of quality and purity, further lowering the costs. However, such materials cost reduction is partially offset by the device fabrication costs, including the anodisation steps and top contact formation.⁴⁹⁵

Fig. 43 Change in V_oc and J_sc for device A and B, as a function of nanowire length (reprinted with permission from ref. 496; copyright @ 2011 IOP Science).

10. Conclusion and future prospects

Due to the small quantities of materials required for their fabrication and their versatility to tune the desired properties of each layer, polycrystalline thin film p-CdTe/n-CdS heterojunction solar cells have become one of the promising contenders for industrial production. The efficiencies in a wide range of 6–20% are achieved with several strategies, such as varying the absorber/window layer thickness, doping the heteroatoms, different preparative methods, different front/back contacts, application of buffer layer and nanostructures, etc. (Table 14). In addition, a junction activation step with hazardous CdCl₂ is eliminated using non toxic Freon gas, making this heterostructure more environmentally benign.

Table 14 Improvement in CdTe/CdS solar cells via several modifications of individual components

Year	η (%)	Significant feature of CdTe/CdS solar cells	Ref.
1988	10.5	CdS surface was in situ cleaned which minimized the interface states	250
1993 & 1994	15.8	CdTe was deposited on CdS by CSS and doped graphite paste was used for ohmic contact	406, 407
1996	10	The efficiency was improved after CdCl2 treatment	375
1996	11.9	CdTe was deposited by MOVCD under Te-rich ambient	140
1997	15.4	Two step CdS formation was used with corning glass as substrate	426
1999	5.3	Mo foil was used as substrate	189
1999	8.9 & 10.6	CdTe was deposited via a low and high temperature CSS method, respectively	343
1999	14.6	Sb2Te3/Mo was used as back contact	274
2000	10.0	No antireflection coating, and CdS/Cd1−xZnxS was used as window layer	102
2001	>10.0	NiTe2 was used as back contact	466
2001	10.5	Large surface area of 1376 cm^2 thin film solar cell sub module	458
	8.4	Aperture area 5413 cm^2
2001	12.3	CdS window layer was grown using HVE technique	397
2001	14.1	CdTe was deposited via CSS at 630 °C and CdCl2 treatment was carried at 415 °C	351
2002	18	Both absorber and window layer were n-type	409
2003	7.4	Junction activation step with CdCl2 was more effective than CsCl and MnCl2	404
2003	11.0	Graphite carbon paste with 7 wt% carbon black powder was used for ohmic contact	459
2003	11.7	60 nm Cu2Te back contact was annealed at 180 °C to produce maximum efficiency	451
2003	12.0	CdS with optimal thickness of 85 nm was deposited by MOCVD	271
2003	12.0	Iodine doped CdTe was used as absorber layer	446
2003	14.0	0.4 μm of fluorine doped In2O3 was used as TCO	424
2004	7.06	Substrate was Mo foil with ZnTe:N as back contact	418
2004	8.3	Absorber layer Cd1−xZnxTe was electrodeposited with SbCl3 bath	249
2004	14.0	Radio frequency sputtered AZO was used as transparent front contact	419
2004	15.9–16.5	CdS:O was used as window layer and ZnSnOx was used as buffer layer	256
2005	11.0	2 nm dry Cu was used as back contact	228
2005	11.2	CdS window layer was grown by CSVT with growth time being 140 s	481
2005	14.0	Oxygen was doped into CdTe layer and ITO:F/SnO2 bilayer front electrode and Mo/Sb2Te3 back contact	444
2006	11.2	Ultrathin CdTe (0.7 μm) obtained by magnetron sputtering was used as absorber layer	120
2006	12.3	S/Cd ratio was 5 in CdS bath solution grown by CBD	479
2006	12.5	Back contact was Ag deposited on Cu-graphite layer	457
2007	5.7 & 5.0	Ultrathin bifacial solar cells for glass and contact side illumination respectively	477
2007	7.4	CdCl2 was deposited using MOCVD technique for the first time	303
2007	8.0	Bi (4 × 10^17 cm^−3) was doped inside the CdTe matrix	448
2007	10.3	Bifacial solar cells: front side illumination with ∼2.5 μm thick CdTe performed better compared to solar cell with CdTe ∼1.0 μm thickness	237
2007	12.9	Cu thickness of 10 nm was used as back contact	455
2007	20.0	Ultrathin CdTe (<3 μm) was used with ZnTe as back surface field	253
2008	6.55	CBD-CdS bilayers (120 + 40 nm) followed by CdCl2 treatment was used as window layer	427
2008	9.7	5 nm Cu thickness of Cu was used as back contact	452
2008	14.8	Junction activation was carried with HCF2Cl gas	393
2009	6.0	CdS nanopillars was used as window layer	495
2009	6.3 & 7.03	Inx(OOH, Sx)y/CdS double layer was used as window layer, with CdS thickness of 100 and 80 nm respectively	434
2009	11.42	Cd0.9Zn0.1S was used as window layer	429
2010	11.0	Mixture of nitric and acetic acid was used as etchants with Au back contact	173
2010	11.3	CSS-CdTe thickness was 5.63 μm	138
2010	12.2	MoOx (40 nm)/Ni was used as back contact	470
2010	>15.0	1 μm CdTe, 50 nm CdS, 100 nm ZnO buffer layer and 100 nm of BSR (ZnTe or Sb2Te3) was used in the cell structure	468
2011	4.17	Graphene front contact with ZnO was used as barrier layer	423
2011	6.5	CdS nanowires was used as window layer	496
2011	7.86	Boron doped graphene was used as back contact	460
2011	9.1	Cu particle doped 3D graphene was used as back contact	464
2011	9.63	CSS-CdS solar cells showed higher efficiency compared to CBD-CdS solar cells	59
2011	10.1	Bilayer CdS-bottom layer CSS-CdS and top layer CBD-CdS with ∼80 nm total thickness was used as window layer	59
2011	11.4	Cu/Mo back contact with ZnO buffer layer was used	454
2011	11.5	Cells treated and calcined with dry CdCl2 showed superior performance compared to wet CdCl2 treatment	319
2011	12.0	Both CdS and CdTe was fabricated by low temperature CSS method	395
2011	13.1	Sb2Te3/Au was used as back contact	467
2011	15.6 &15.4	AZO/i:ZnO layer was used as front contact with aluminosilicate and borosilicate glass substrates respectively	421
2012	6.6	CBD-CdS films were annealed in the presence of oxygen for 5 minutes prior to CdTe deposition	60
2012	6.8	Ultrathin CdTe (1.0 μm) was used as absorber layer and Cd1−xZnxS as window layer	121
2012	8.3 & 9.9	SiO2 was used as barrier layer for sodium diffusion and CdCl2 was carried at 350 and 400 °C respectively	243
2012	12.1	1D Cu nanowire/3D graphene was used as back contact	465
2012	11.5–12.9	MoOx/M (M = Ni, Mo, Cr, Al and Mg) was used as back contacts	473
2012	12.0	Cu2Te/Au back contact was used.	367
2012	12.1	Sprayed AZO was used as front contact	422
2012	14.0	Both CdS and CdTe were deposited by HVE at 165 and 350 °C, respectively	128
2012	14.0–14.6	Junction activation was carried with HCF2Cl gas and CdS was treated in oxygen atmosphere before CdTe deposition	392
2013	13.6	The copper was doped into CdTe matrix, in substrate configuration	416b

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Increasing the efficiency, reliability and life time of this device has been a focal point from two decades and yet the best efficiencies achieved to date are still far from the theoretical limit. Together with technological problems, progress towards improvement is suppressed by the lack of scientific knowledge about the processes occurring at various interfaces of the device. Inevitably, a number of interfaces between materials with different crystal structures and/or lattice constants cause complexity in device formation. The various failure mechanisms can be active simultaneously, making their identification and rectification difficult. As a result, fabrication processes are slowly approaching their limits and this is the main reason for only marginal improvement, despite the intensive efforts for the last two decades.

The reason for such slow progress appears to be lack of understanding of critical issues like: junction activation treatment, which changes the bulk, interfacial and grain boundary properties; the formation of stable back contacts; and impurities diffusion within the device. This complexity arises due to the influence of multiple parameters like: layer thickness; grain size; donor/acceptor profile; carrier generation rate; recombination dynamics at various interfaces; CdS–CdTe intermixing; quasi Fermi level distribution; band alignments among the interfaces; diffusivity of metal from the back contact; influence of barrier layer, if any; induced chemical reactions during processing, etc., on the solar cell performance. In addition, both CdS and CdTe are polycrystalline and hence their properties vary depending on precursor chemistry, growth conditions, technique and annealing ambient. Due to the difficulty of performing scientific study on randomly oriented polycrystalline thin films, massive research has utilized a semi-empirical approach that has hampered the advancement of fundamental understanding. From the literature, it can be concluded that device performance cannot be described by taking the properties of the component materials in their bulk form and applying junction theory.

Despite the intensified research, there is no rule of thumb for better performance, and reported mechanisms are often beyond intuition. As suggested by Kosyachenko et al.,⁴⁹⁷ resistivity, absorber layer thickness, non-compensated acceptor concentration and carrier lifetime should be ∼0.1 Ω cm, ≥20–30 μm, ≥10¹⁶ cm⁻³ and ≥10⁻⁶ s, respectively, to achieve a theoretical efficiency of ∼30%. In practice, an electrical barrier within the multilayer leads to efficiency loss. The limited conclusive information about the understanding of important relationships between the processing conditions and device characteristics further complicates the development of this novel device. Hence, systematic research is necessary to understand the apparent complexities in the cell structure and new innovative technologies and concepts are essential to solve the persistent challenges of CdTe/CdS photovoltaics.

Abbreviations

AZO	Aluminium doped ZnO
ALE	Atomic layer epitaxy
APCVD	Atomic pressure chemical vapor deposition
APCSS	Atmospheric pressure close space sublimation
BSR	Back surface reflector
CB	Conduction band
CSS	Close-space sublimation
CSVT	Close-space vapor transport
DLTS	Deep level transient spectroscopy
DFT	Density functional theory
GBs	Grain boundaries
ED	Electrodeposition
ECU	European currency unit
FF	Fill factor
FCA	Fluorescent coloring agent
HVE	High vacuum evaporation
IPCE	Incident photon to conversion efficiency
ITO	Indium tin oxide
i:ZnO	Intrinsic ZnO
LBIC	Light beam induced current
MBE	Molecular beam epitaxy
MOVCD	Metallorganic vapor chemical deposition
NIEL	Non ionization energy loss
V oc	Open circuit voltage
PV	Photovoltaic
PL	Photoluminescence
QE	Quantum efficiency
R s	Series resistance
I sc	Short circuit current
J sc	Short circuit current density
SIMS	Secondary ion mass spectroscopy
TCO	Transparent conducting oxide
VB	Valence band
VBM	Valence band maximum
VCd	Vacancies in cadmium or cadmium vacancies
XPS	X-Ray photoelectroscopy

Acknowledgements

One of the authors Dr S. Girish Kumar acknowledges financial support from the Dr Daulat Singh Kothari Post Doctoral Fellowship Cell and the Department of Physics, IISc, Bangalore for providing the research facilities.

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