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Issue 11, 2014
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Inverted process for graphene integrated circuits fabrication

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CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of −26 dB.

Graphical abstract: Inverted process for graphene integrated circuits fabrication

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The article was received on 30 Dec 2013, accepted on 02 Mar 2014 and first published on 04 Mar 2014

Article type: Paper
DOI: 10.1039/C3NR06904D
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Citation: Nanoscale, 2014,6, 5826-5830

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    Inverted process for graphene integrated circuits fabrication

    H. Lv, H. Wu, J. Liu, C. Huang, J. Li, J. Yu, J. Niu, Q. Xu, Z. Yu and H. Qian, Nanoscale, 2014, 6, 5826
    DOI: 10.1039/C3NR06904D

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