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Issue 23, 2016
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Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors

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Abstract

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal–oxide–semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

Graphical abstract: Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors

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Publication details

The article was received on 04 Feb 2016, accepted on 22 May 2016 and first published on 23 May 2016


Article type: Paper
DOI: 10.1039/C6NR01040G
Citation: Nanoscale, 2016,8, 12022-12028
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    Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors

    N. H. Van, J. Lee, D. Whang and D. J. Kang, Nanoscale, 2016, 8, 12022
    DOI: 10.1039/C6NR01040G

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