Dynamically reconfigurable artificial synapse transistors with organic heterojunctions for multifunctional neuromorphic applications

Abstract

Artificial synapses capable of neuromorphic computation are crucial for improving the processing efficiency of existing information technologies. Most of the current research on artificial synapses only simulates static synapse plasticity, and implementing bipolar artificial synapses with two modes of operation and dynamic reconfigurability remains challenging. In order to efficiently and flexibly simulate the complex behaviour of the human brain, an electret-based organic heterojunction synaptic transistor (EOHST) is designed in this paper. The transistor consists of pentacene and PTCDI-C₁₃ organic semiconductor films as the bipolar channel layer, with a polymer PVN as an electret functional layer. Owing to the combination of bipolar behavior and the charge trapping effect, the transistor can respond to identical gate pulses in different modes (excitatory and inhibitory), demonstrating a dynamically reconfigurable operational state that imitates different synaptic behaviors (potentiation and depression) of the biological nervous system in various modes. Using the Modified National Institute of Standards and Technology (MNIST) dataset images of handwritten digits, the EOHST-based neuromorphic system achieved recognition accuracies of 87.5% and 80% in its various modes. Additionally, by examining learning accuracies in different EOHST modes, the system simulated visual learning and memory processes across various emotional states. Finally, a digital logic processing system is designed to dynamically simulate AND/OR and NAND/NOR logic circuits at the same input voltage through excitatory and inhibitory modes. This dynamically reconfigurable bipolar transistor represents a significant advancement in the future development of neuromorphic computing.

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1. Introduction

Traditional von Neumann-based computing architectures require a physical separation of data transfers performed between processors and memories, which poses challenges in processing large amounts of complex data.^1,2 Conversely, the human brain's neuronal networks, connected by synapses, can efficiently process and store vast amounts of parallel information.^3,4 Therefore, artificial synapses that can mimic the parallel computational properties and versatility of synapses have been proposed and extensively studied as a promising approach for achieving high-speed and energy-efficient computing.^5,6 Organic field-effect transistors (OFETs) have recently garnered significant interest due to their advantages, such as cost-effectiveness, low process temperature, easy accessibility, flexibility, biocompatibility, and excellent performance tenability. These advantages make them suitable for potential applications in future electronic devices.^7–9 However, many OFET-based synaptic devices only capture unipolar charges,^10,11 significantly restricting their ability to modulate postsynaptic currents.^12,13 Ideally, synaptic transistors should capture charge carriers across different positions and energy levels, enabling efficient charge trapping and release for multi-level data storage.^14,15 For instance, D. Li et al. improved the charge injection efficiency and thus the optical response by incorporating an n-type semiconductor C₈-PTCDI between a p-type semiconductor C₈-BTBT and an electret layer.¹⁶ In addition, while most organic artificial synapses can only simulate static excitatory and inhibitory postsynaptic responses,^17,18 some synapses have synaptic responses that are not completely fixed and can be reconfigured between different synaptic responses through neuromodulators in the nervous system.^19,20 Research has consistently demonstrated that various neuromodulators play a pivotal role in these neural dynamics.²¹ For example, endorphins and associated opioid receptors in the central nervous system can act as the neuromodulator to modulate the neural activities in the pain pathway.^22,23 Note S1 (ESI†) illustrates the manifestation of dynamic remodeling in biological synapses and its significance. Reconfigurable artificial synapses, which regulate synaptic responses between different modes, are crucial for the development of artificial intelligence (AI) systems. However, there are still several hurdles to attaining this dynamic reconfigurability with simple single-gate transistors.²⁴ The reconfigurable bipolar transistors can be operated as either n-type or p-type based on the polarity control signal, and they can be dynamically configured in runtime.²⁵ All synaptic responses rely simply on the input gate signal, which is significantly different from previously reconstructed devices that depend on additionally modulated terminals.²⁴ However, to date, there have been few studies on dynamic reconfigurable synapses in organic field-effect synaptic transistors. Therefore, a dynamically reconfigurable bipolar organic synaptic transistor that produces considerably different responses to identical external environmental stimuli, to adapt to the complicated external environment, is highly desirable. Meanwhile, reconfigurable bipolar transistors are compatible with complementary metal oxide semiconductor (CMOS) logic and require fewer components in circuits compared to regular transistors. This is attractive for simplifying the fabrication and versatility of the circuits, making it a significant step towards promoting the development of the next generation of AI systems.^26,27

This paper presents the design of an electret-based organic heterojunction synaptic transistor (EOHST) composed of p-type organic semiconductor pentacene and n-type organic semiconductor PTCDI-C₁₃. The device utilizes poly(vinylidene fluoride-trifluoroethylene-chlorofluoroe-thylene) [P(VDF-TrFE-CFE)] as the dielectric layer and poly(2-vinylnaphthalene) (PVN) as the electret layer. PVN is chosen for its robust charge storage, while pentacene facilitates efficient charge transfer across electrodes, optimizing the transistor's responsiveness to electrical signals. Moreover, P(VDF-TrFE-CFE) is utilized for its high dielectric constant and low hysteresis, expanding its utility in OFETs. A clear “V” shaped hysteresis characteristic can be observed in the transfer curves of different gate voltage scanning ranges. Charge trapping in PVN, combined with switching between p-type and n-type layers in heterojunction channels, allows the transistor to respond to identical gate pulses in different modes (excitatory and inhibitory), thus demonstrating dynamically reconfigurable states with distinct synaptic behaviors (potentiation and depression). This reconfigurable property enables our artificial synapses to imitate some complex biological functions in future AI systems, including the recognition of varied external signals and their regulation under dynamic circumstances. Additionally, the device simulates various synaptic behaviors, such as short-term and long-term plasticity (STP/LTP), paired-pulse facilitation and depression (PPF/PPD), spike-rate-dependent plasticity (SRDP), and spike-number-dependent plasticity (SNDP). The long-term potentiation (LTP) and long-term depression (LTD) curves in excitatory and inhibitory modes have a low asymmetric non-linear factor (ANL) and normalized nonlinearity factor (α), which is beneficial for the recognition accuracy of the neural network. For the Modified National Institute of Standards and Technology (MNIST) dataset of handwritten digits (28 × 28 pixels), the simulated neuromorphic system built on EOHST achieved recognition accuracies of 87.5% and 80% in different modes, respectively. At the same time, based on the differences in learning accuracy in different modes of EOHST, the visual learning and memory processes of people in varying emotional states were simulated. Finally, a digital logic processing system is designed to dynamically simulate AND/OR and NAND/NOR logic circuits using excitatory and inhibitory modes with the same input voltage. This dynamic reconfigurable bipolar transistor represents a significant breakthrough in the future advancement of neuromorphic computing.

2. Experimental details

2.1. Device fabrication

We obtained P(VDF-TrFE-CFE) terpolymer from Piezotech-Arkema Corp., France, with a composition of 63.2/29.7/7.1 and PVN with a molecular weight of 175 000 from Sigma-Aldrich Trading Corp. These materials were dissolved in butyl acetate (BA) and chlorobenzene to concentrations of 6 wt% and 1 wt% respectively, and stirred for two hours to achieve homogeneity. Fig. S1 (ESI†) illustrates the fabrication process in detail. A 40 nm thick aluminum film was thermally evaporated onto glass substrates to create the gate electrode. The dielectric layer was formed by spin-coating the P(VDF-TrFE-CFE) solution onto the gate electrodes, followed by annealing at 120 °C for 120 minutes to remove residual solvents. The electret layer was created by spin-coating the PVN solution onto the P(VDF-TrFE-CFE) films, and then annealed at 100 °C for 60 minutes to eliminate remaining solvents. The achieved film thicknesses were 325 nm for P(VDF-TrFE-CFE) and 27 nm for PVN (Fig. 1g). The thickness of the PTCDI-C₁₃ thin film, which was vacuum-thermally deposited on the PVN film at a rate of 0.1 Å s⁻¹, was measured using precise quartz crystal detection methods and found to be 10 nm. Then, a 30 nm thick pentacene layer was deposited on the PTCDI-C₁₃ film at the same rate. Finally, 50 nm Cu films, forming the source–drain (S–D) electrodes, were deposited at 1 Å s⁻¹ using vacuum thermal evaporation and patterned with a shadow mask. The channel dimensions were 100 μm length (L) and 1000 μm width (W), as shown in an optical microscopy image of the EOHST presented in Fig. S2 (ESI†). For comparison, we also prepared PTCDI-C₁₃ film devices with thicknesses of 5 and 15 nm, respectively, and the preparation process was the same as described above.

Fig. 1 EOHST structure and film characteristics. (a) Schematic diagram illustrating the EOHST device structure. (b) SEM image of the EOHST cross-section. AFM image of (c) P(VDF-TrFE-CFE), (d) P(VDF-TrFE-CFE)/PVN, (e) P(VDF-TrFE-CFE)/PVN/PTCDI-C₁₃, and (f) P(VDF-TrFE-CFE)/PVN/PTCDI-C₁₃/pentacene. (g) The thicknesses of pentacene, PTCDI-C₁₃, PVN, and P(VDF-TrFE-CFE). (h) XRD spectra of PTCDI-C₁₃, pentacene and PTCDI-C₁₃/pentacene heterojunction thin films.

2.2. Characterization

The electrical properties of the device were measured using a semiconductor parameter analyzer (Keithley 4200A-SCS) under ambient conditions at room temperature. The cross-sectional image of the device was obtained by scanning electron microscopy (SEM)(JSM-7800F). The surface morphology and film thickness were analyzed using atomic force microscopy (AFM) (MFP-3D) in tapping mode. The surface potential of the device was investigated using a Kelvin probe force microscope (KPFM) and a Keithley 2450 precision source/measurement unit. The X-ray diffraction (XRD) patterns were recorded by using a Bruker D8 Advance diffractometer with Cu-Kα radiation (λ = 1.5418 Å). The simulations were conducted using the CrossSim platform, utilizing the MNIST dataset, which consists of images of digits categorized into 10 classes (0 to 9), with each image comprising 28 × 28 pixels. This dataset includes 60 000 images for training and 10 000 for testing. The simulations incorporated considerations of asymmetry, nonlinearity, G_max/G_min ratio, and cycle-dependent durability of the modeled synaptic device.

3 Results and discussion

3.1. Device structure and film characteristics

The synaptic transistors were constructed in a bottom-gate top-contact architecture. Fig. 1a displays a schematic of the EOHST and the chemical structures of essential materials utilized, including pentacene, PTCDI-C₁₃, PVN, and P(VDF-TrFE-CFE). The SEM image in Fig. 1b shows the EOHST with an independent layered structure and good interlayer contact. Fig. 1(c–f) displays the AFM images of different layers of thin films in EOHST on the glass substrate. The P(VDF-TrFE-CFE) thin film possesses a surface roughness measuring 2.49 nm, whereas the PVN thin film exhibits a smooth surface with a roughness of 1.23 nm. This research reveals that the PVN layer not only serves as an electret layer, but also has a certain passivation effect on the device. The flat surface topography is suitable for the application of gate dielectric in transistors and contributes to the production of high-quality semiconductor/dielectric interface features, thereby facilitating the growth of bipolar devices.^28–30 The PTCDI-C₁₃ film displayed a surface roughness of 4.11 nm, whereas the pentacene film showed a surface roughness of 7.96 nm. The well crystallized PTCDI-C₁₃ surface resulted in the relatively smaller grain size of pentacene, which forms the basis for its balanced ambipolar behavior. Moreover, the trap sites in the heterojunction/PVN bulk and the interfaces can also facilitate efficient charge trapping.³¹ The XRD results, as illustrated in Fig. 1h, compare the diffraction patterns of pentacene, PTCDI-C₁₃, and the heterojunction layer to ensure the coexistence of two materials in the heterojunction layer. The typical intense peaks of pentacene (2θ = 5.7°, 11.5°, and 17.3°), PTCDI-C₁₃ (2θ = 3.2°), and four characteristic peaks of the heterojunction layer were all observed at the corresponding positions, which was consistent with the previous findings.³²

3.2. Dynamically reconfigurable characteristics and electrical characteristics

Synaptic activity in biology is performed by connecting two neighboring neuron cells, including presynaptic, postsynaptic neurons, and the synaptic cleft. When a presynaptic neuron is externally stimulated, neurotransmitters enter the synaptic gap and are accepted by the receptors of the postsynaptic neuron, thus completing the transmission of information between neurons.³³Fig. 2a illustrates the structure of a dynamically reconfigurable synapse that is capable of modifying excitatory and inhibitory synaptic responses through the release of neuromodulators. Furthermore, it can elicit both potentiation and depression postsynaptic potentials by releasing various neurotransmitters.²² Here, the gate pulse is considered as the presynaptic signal and the drain current (I_DS) represents the synaptic weight in the form of the postsynaptic current (PSC). We investigated the impact of varying the thickness of the PTCDI-C₁₃ layer (5, 10, and 15 nm) in the heterojunction semiconductor layer on the charge transport properties of the devices. Our objective was to optimize this composition to achieve balanced ambipolar transistor performance. Fig. S3 (ESI†) illustrates the distinct transfer characteristics of these devices, highlighting the critical role played by the PTCDI-C₁₃ layer thickness in modulating charge transport within heterojunction semiconductor layers. As the content of PTCDI-C₁₃ increases, it transitions from hole-dominated mobility to a state of equilibrium between the hole and the electron mobility, and then gradually shifts towards electron-dominated mobility, exhibiting different storage windows. Relative to PTCDI-C₁₃ devices with thicknesses of 5 nm and 15 nm, devices with a thickness of 10 nm exhibited relatively balanced characteristics in terms of hole and electron transport. Fig. 2b displays the transfer characteristics of the device with a 10 nm PTCDI-C₁₃ layer, where different bidirectional gate voltage (V_GS) sweeping ranges of ±10 V, ±15 V and ±20 V were used. The I_DS was measured with a drain voltage (V_DS) of −5 V, exhibiting relatively balanced and typical bipolar behavior. The counterclockwise hysteresis and clockwise hysteresis were observed for the hole (p-channel) mode and electron (n-channel) mode, respectively, indicating the presence of both hole and electron trapping in the channel. The combined behaviors of trapping electrons and holes effectively regulate channel conductance, making it possible for the device to simulate an artificial synapse. The mobility (μ) of the EOHST can be obtained by fitting the linear transfer characteristic curve using eqn (1).where L and W represent the channel length and width, respectively, while C_i denotes the capacitance per unit area of the gate dielectric layer. The C_i of the composite gate dielectric layers was determined to be approximately 26 nF cm⁻² at a frequency of 1000 Hz, based on measurements from Al/P(VDF-TrFE-CFE)/PVN/Al, as shown in Fig. S4 (ESI†). The EOHST exhibited a relatively consistent μ value of ∼0.028 cm² V⁻¹ s⁻¹ for the p-channel mode and ∼0.039 cm² V⁻¹ s⁻¹ for the n-channel mode, respectively. Furthermore, the electrical characteristics of devices with different PTCDI-C₁₃ film thicknesses are statistically presented in Table S1 (ESI†). The results indicate that both hole and electron transport have the potential to construct high-performance transistors in EOHST compared to other devices. The ambipolar EOHST is further corroborated by the output characteristics displayed under negative V_DS (Fig. S5a, ESI†) and positive V_DS (Fig. S5b, ESI†) regimes at various V_GS values. Both in positive and negative V_DS regimes, the absolute I_DS values increased as the absolute V_GS values increased from 20 to 50 V, while for the absolute V_GS values increasing from 0 to 10 V, the absolute I_DS values became smaller, confirming the enhancement of electrons and holes in the heterojunction structure. Additionally, we investigated the variability between the devices, and Fig. S6 (ESI†) shows the I_DS–V_GS curves of five different devices on the substrate. The hysteresis window is basically consistent, indicating that our EOHST device has good uniformity.

Fig. 2 Reconfigurable characteristics of artificial synapses. (a) Schematic of a biologically reconfigurable synapse modulated by neuromodulators. (b) Hysteretic transfer characteristic curves, depicted across various gate voltage sweep ranges at a V_DS of −5 V. (c) Potentiation behavior induced by a positive pulse in excitatory mode. (d) Depression behavior induced by a negative pulse in excitatory mode. (e) Potentiation behavior induced by a negative pulse in inhibitory mode. (f) Depression behavior induced by a positive pulse in inhibitory mode.

Next, we investigated the basic synaptic plasticity of ambipolar artificial synapses in both excitatory and inhibitory response modes (Fig. 2(c–f)). In our devices, low-intensity positive and negative presynaptic signals (baseline voltage of ±5 V) were applied to the gate, inducing a relatively weak electric field. This field facilitates the capture of carriers within the semiconductor layer into traps in the PVN film, thereby altering the change of PSC, which simulates both excitatory and inhibitory synaptic response. The control signals were solely applied at the gate electrode, without involving any external modulating terminal, and the V_DS was maintained at −5 V. Our dynamically reconfigurable artificial synapses are capable of exhibiting diverse synaptic behaviors (potentiation and depression) when subjected to identical stimulus pulses in different modes (excitatory and inhibitory). The change in I_DS following the pulse, denoted as ΔI_DS, signifies potentiation behavior when ΔI_DS > 0 and depression behavior when ΔI_DS < 0. The potentiation behavior in the excitatory mode, as shown in Fig. 2c, was measured under a positive gate pulse of +11 V (with a baseline voltage of −5 V, pulse voltage of +11 V, and pulse width of 200 ms). This behavior mimics the excitatory postsynaptic potentials by releasing excitatory neurotransmitters in biological synapses. Conversely, Fig. 2d demonstrates the depression behavior in the excitatory mode, measured under a negative gate pulse of −11 V (with a baseline voltage of −5 V, a pulse voltage of −11 V, and a pulse width of 200 ms), analogous to inhibitory postsynaptic potentials linked to the release of inhibitory neurotransmitters. Fig. 2e and f further delineate the potentiation and depression behaviors in the inhibitory mode, observed under a negative pulse of −11 V (with a baseline voltage of +5 V, a pulse voltage of −11 V, and a pulse width of 200 ms) and a positive pulse of +11 V (with a baseline voltage of +5 V, a pulse voltage of +11 V, and a pulse width of 200 ms), respectively.

3.3. Work mechanism for different synaptic behaviors

For the potentiation behaviour in the excitatory mode, when a gate pulse (with a baseline voltage of −5 V, pulse voltage of +11 V, and pulse width of 200 ms) is applied to the control gate, it results in a four-stage variation in I_DS, which are delineated as stages I, II, III, and IV respectively (Fig. 3a). To elucidate the operational mechanism of the EOHST, Fig. 3b illustrates the inverted band bending caused by voltage variations at the gate terminal, which corresponds to the four-stage variation characteristic of I_DS. The pentacene and PTCDI-C₁₃ play key roles in facilitating bipolar charge injection, transport, and accumulation.^32,34 In order to better understand the charge-trap state and the charge distribution in channels, the operational mechanism is illustrated in Fig. 3c. Initially (stage I), the I_DS remains stable at approximately 12 nA. The gate pulse triggers an instantaneous increase in I_DS (stage II), while the subsequent decrease in I_DS indicates the termination of the gate pulse (stage III). Even after the pulse is released, some electrons in the heterojunction channel remain trapped by the PVN film. These trapped electrons effectively constitute a varied negative V_GS, which continues to modulate the heterojunction channel and leads to an increase in I_DS that characterizes potentiation behavior (stage IV).

Fig. 3 Ambipolar synaptic transistor under single pulse stimulation and corresponding work mechanism. (a) PSC exhibiting a four-stage variation characteristic under a positive gate pulse in the excitatory mode. (b) Schematic representation of the working mechanism and band diagram from stages I to IV. (c) An illustrative depiction of the charge-trap state and charge distribution in channels. (d) Distribution of contact potential difference in the heterojunction film measured using KPFM mode after applying gate biases of 0 V, −20 V, and +20 V. (e) Schematic of surface potential analysis of the device surface conducted via in situ KPFM experiment. (f) Potential distribution across the device surface.

As depicted in Fig. S7 (ESI†), for the depression behavior in excitatory mode, the initial I_DS is maintained at 18 nA (stage I). A gate pulse (with a baseline voltage of −5 V, pulse voltage of −11 V, and pulse width of 200 ms) leads to a rapid increase in I_DS (stage II) and simultaneously drives the transfer of induced holes in the heterojunction channel to the PVN films. Upon removal of the gate pulse, the elevated I_DS rapidly depletes (stage III), and the trapped holes in the PVN film do not immediately revert to their original state (effectively equivalent to a varied positive V_GS). Consequently, the I_DS decreases relative to its initial value, displaying depression behavior (stage IV).

Fig. S8 (ESI†) illustrates the potentiation behavior in inhibitory mode, observed under a gate pulse (with a baseline voltage of +5 V, pulse voltage of −11 V, and pulse width of 200 ms). At the initial state (stage I), the I_DS is maintained at 1.5 nA. When the gate pulse is applied, the increased number of holes in the channel leads to a significant increase in I_DS (stage II). Concurrently, the pulse facilitates the transfer of induced holes from the channel to the PVN film. Upon removal of the pulse, the I_DS rapidly diminishes due to its prior boost by the pulse (stage III). The trapped holes in the PVN film do not revert immediately, thus generating a weak internal electric field with positive polarity. This leads to I_DS stabilizing above its initial reference value, indicative of potentiation behavior (stage IV).

As illustrated in Fig. S9 (ESI†), the depression behavior in the inhibitory mode is achieved under a gate pulse (with a baseline voltage of +5 V, pulse voltage of +11 V, and pulse width of 200 ms). Initially, I_DS stabilizes at 6.9 nA (stage I). The application of the gate pulse prompts electron transfer from the heterojunction semiconductor to the PVN film, generating more holes in the channel and causing a substantial rise in I_DS (stage II). Upon removal of the pulse, the induced holes quickly revert to their original state (stage III), but the electrons transferred to the PVN film do not immediately return. The captured electrons form a weak internal electric field with negative polarity in the device, resulting in a decrease in I_DS that indicates depression behavior (stage IV). In summary, our EOHST exhibits both potentiation and depression responses under identical amplitude gate pulses, representing a dynamically reconfigurable modulation.

To further demonstrate the carrier-trapping capabilities associated with gate bias, we analyzed the ambipolar synaptic device featuring a heterojunction film in KPFM mode using a Keithley 2450 precision source/measurement unit, and the schematic architecture is demonstrated in Fig. 3e. In practice, as shown in Fig. 3d, when the sample bias was −20 V, the average surface potential of the film is −0.13 V, confirming that the heterojunction film was in a hole-trapping state. Conversely, at a sample bias of +20 V, the average surface potential is 0.22 V, confirming the presence of an electron-trapping state in the fabricated structure. The corresponding potential values extracted after applying different gate bias are shown in Fig. 3f. The initial average surface potential of the heterojunction film was approximately −0.06 V. A shift from +20 V to −20 V in sample bias results in a decrease in surface potential of about 0.35 V, indicating a significant change in the charge capture state of EOHST.

3.4. Synaptic behavior for dynamic reconfigurability

The pulse amplitude and width, which are considered as indicators of the intensity and duration of information, can regulate potentiation/depression behaviors in both excitatory and inhibitory modes.³⁵Fig. 4a and Fig. S10a (ESI†) display the potentiation/depression behaviors in the excitatory mode under different positive/negative gate pulses (ranging from 7 to 19 V with a step of 2 V/from −7 to −19 V with a step of −2 V). An increase in the extracted ΔI_DS, as shown in Fig. 4b, indicates that both potentiation and depression behaviors are enhanced by increasing the amplitudes of the input pulses. This enhancement can be attributed to the altered number of electrons and holes trapped in the PVN film. As the pulse amplitude increases, more electrons or holes are captured by the PVN film, facilitating the transition of PSC from STP to LTP. Fig. S10b and c (ESI†) demonstrates that in the inhibitory mode, both potentiation and depression behaviors are similarly affected by changing gate pulse amplitudes (ranging from −7 to −19 V with a step of −2 V/from 7 to 19 V with a step of 2 V). As shown in Fig. 4c, the increase ΔI_DS indicates that the potentiation and depression behaviors of potentiation and depression become more intense as the amplitudes of the gate pulses rise. This is attributed to the greater or lesser number of holes in the channel, resulting from an increased number of trapped electrons or holes. Furthermore, as illustrated in Fig. 4d and Fig. S11 (ESI†), the potentiation and depression behaviors in both modes are also influenced by pulse widths (from 0.4 to 2.4 s in increments of 400 ms). The escalation of both amplitude and width of pulses parallels the brain's mechanism of strengthening synaptic connections, which underpins the acquisition of experiences and formation of memories.³⁶ To assess the long-term plasticity of the EOHST, synaptic weight decay was measured over time. Weight changes were sustained for over ten minutes through multiple pulsed stimuli, indicating the nonvolatile properties of our synaptic devices (Fig. S12, ESI†).

Fig. 4 STP to LTP transition, PPF/PPD and SRDP behaviors of dynamic reconfiguration (a) Potentiation behaviors under different amplitude pulses in excitatory mode. (b) Variation of ΔI_DS with different amplitude pulses in excitatory mode. (c) Variation of ΔI_DS with different amplitude pulses in inhibitory mode. (d) Depression behaviors under different width pulses in inhibitory mode. (e) Variation of ΔI_DS with different width pulses in inhibitory mode. (f) Variation of ΔI_DS with different width pulses in excitatory mode. (g) PPF behavior in inhibitory mode. (h) PPF/PPD index in inhibitory mode. (i) PPF/PPD index in excitatory mode. (j) Depression behaviors induced by trains of 10 pulses at varying frequencies in excitatory mode. (k) The SRDP index as a function of frequency in excitatory mode. (l) The SRDP index as a function of frequency in inhibitory mode.

PPF and PPD behaviors are key forms of short-term synaptic plasticity, which are crucial for information processing in biological systems.³⁷ As demonstrated in Fig. 4g, the PPF behavior in inhibitory mode is elicited by applying two successive −11 V pulses at varying intervals (Δt). The ΔI_DS of the second pulse (A₂) exceeds that of the first (A₁) due to insufficient time for trapped holes from the first pulse to de-trap back to the PVN film before the arrival of the second pulse, thereby increasing the PSC. The PPF/PPD index (A₂/A₁), two indicators of presynaptic plasticity that evaluate the variations in synaptic response strength depending on the timing and behaviors of synapses, is defined as follows:

where Δt represents the interval between pulses, C₁ and C₂ denote the initial amplitudes, and τ₁ and τ₂ are the characteristic relaxation times for the two phases, respectively. When the interval Δt between pulses is short, some trapped carriers fail to return to the semiconductor layer channel before the initiation of the second pulse. These residual carriers, combined with those trapped by the second pulse, enhance the ΔPSC and thus increase the PPF index (Fig. 4h). Conversely, a longer pulse interval allows for the release of these trapped carriers back to the semiconductor layer channel before the second pulse, resulting in a lower PPF index. Similarly, the PPD behavior can be effectively simulated by applying a pair of +11 V pulses at varying intervals, as depicted in Fig. S13a and S14 (ESI†). The fitting results for PPF/PPD in inhibitory mode indicate that τ₁ is 52/16 ms and τ₂ is 439/331 ms. Fig. S13b and c (ESI†) illustrates that PPF/PPD behavior in the excitatory mode can be induced by two consecutive +11/−11 V pulses at varying Δt, where τ₁ and τ₂ for PPF/PPD are 62/21 ms and 414/590 ms. These relaxation times are comparable to those observed in biological synapses, which is a critical factor for understanding how biological systems encode temporal information.^38,39

Furthermore, our proposed EOHST implements a filtering function for signal processing, demonstrating that synaptic weight is continuously modified by SRDP.⁴⁰Fig. 4j and Fig. S15a (ESI†) illustrate the depression and potentiation behaviors in the excitatory mode, triggered by ten consecutive pulses at different frequencies. The SRDP index in PSC, calculated as I_n/I₁ × 100%, serves as an index for assessing the filtering characteristics of the device, where I₁ and I_n denote the PSC amplitudes of the first and last pulse, respectively. As depicted in Fig. 4k, the decrease in the SRDP index with frequency demonstrates the device's low-pass temporal filtering capability for inputs of varying polarity in excitatory mode. In the inhibitory mode, as shown in Fig. S15b and c (ESI†), PSC amplitude can be modulated by applying consecutive pulses at varying frequencies. Fig. 4l shows that the SRDP index under negative amplitude pulses increases with stimulation frequency, indicating high-pass filtering characteristics. Similarly, the SRDP index also decreases with frequency, indicating low-pass filtering characteristics for positive amplitude continuous pulses. These findings confirm that the ambipolar EOHST can differentiate signals of different polarities under various stimulus frequencies, thereby enhancing information processing efficiency. Additionally, as illustrated in Fig. S16 (ESI†), SNDP was demonstrated in both modes. This capability underscores the potential of the EOHST to emulate complex neuronal activities in response to various stimulus frequencies.

3.5. Neuromorphic computing and visual learning in different emotional states

Using the back-propagation algorithm and assessing higher linearity and symmetry in LTP and LTD through testing proves to be a viable approach for image recognition and replication. Specifically, this method utilizes handwritten digits from the MNIST dataset in versions of 64 pixels (8 × 8) and 784 pixels (28 × 28) to evaluate recognition accuracy,^40,41 as seen in Fig. 5a. Note 1 describes the quantification of synaptic weights and the implementation of back-propagation using a three-layer network (with one hidden layer) simulated in “CrossSim”. As depicted in Fig. 5b, synaptic weights are updated through matrix operations using a crossbar switch array. The accuracy of recognition in these hardware neural networks is significantly influenced by α and ANL associated with LTP/LTD. Consequently, achieving optimal training pulse responses with relatively low ANL and α_{p, d} is essential for attaining excellent recognition accuracy in hardware neural networks. These parameters are calculated using the following formulas:⁴²here, α_p and α_d denote the nonlinearity factors of the experimental data for potentiation and depression, respectively. and represent the median conductance values measured along the directions of potentiation and depression, respectively. G_max and G_min designate the maximum and minimum conductance values, respectively.

Fig. 5 Neuromorphic computing and different emotional learning process simulation. (a) and (b) A schematic diagram of a hardware neural network utilizing the back-propagation algorithm. (c) PSC modulation demonstrated through the application of designed step-voltage positive pulses and negative pulses. (d) Development of recognition accuracy across training epochs for 28 × 28 pixels handwritten digital images in the excitatory mode. (e) Confusion matrix for the electrically stimulated neural network. (f) PSC modulation achieved by applying designed step-voltage negative pulses and positive pulses. (g) Development of recognition accuracy across training epochs for 28 × 28 pixels handwritten digit images in the inhibitory mode. (h) Confusion matrix for the electrically stimulated neural network. (i)–(j) Simulation of the effects of emotions on learning and memory processes, emulating digit recognition.

Fig. 5c shows the rise and fall of the PSC in the excitatory mode of our synaptic device under the designed step-voltage stimulation. Accordingly, ten cycles of alternating 50 positive (ranging from 12 to 16.9 V in increments of 0.1 V, each lasting for 200 ms) and 50 negative (ranging from −10 to −12.45 V with a step size of −0.05 V, each lasting for 200 ms) gate pulses were obtained under a baseline voltage of −5 V (Fig. S17a, ESI†). Under the stimulation of these gate pulses, relatively low values were obtained for ANL and nonlinearity (α_p = 0.044, α_d = 0.007, ANL = 0.19). The recognition accuracy in hardware neural networks was significantly improved by these parameters. The recognition accuracies of the large (28 × 28 pixels) and small (8 × 8 pixels) versions of handwritten digits from the MNIST dataset exceed 87.5% and 90%, respectively (Fig. 5d and Fig. S18a, ESI†), which outperform those of most reported OFETs.^43,44 Next, we summarize the key parameters of recently published bipolar artificial synapse devices in Table S2 (ESI†). The network's classification effectiveness is demonstrated by a confusion matrix (Fig. 5e), which compares the computational results with a labeled test set, displaying accurate classifications for specific numbers along the diagonal.⁴⁵ After training, the test inputs are accurately categorized, with number “1” achieving the highest accuracy (1124 correct classifications) and number “5” having the most misclassifications (738). In addition, Fig. 5f shows the simulated LTP and LTD cases in inhibitory mode, where a PSC with a baseline voltage of +5 V is realised by alternating 50 negative pulses (ranging from −4 to −16.25 V with a step of −0.25 V, each lasting for 200 ms) and 50 positive pulses (ranging from 2 to 6.9 V with a step of 0.1 V, each lasting for 200 ms). Nonlinear analysis in this mode yielded values of α_p = 0.038, α_d = 0.87, and ANL = 0.21. The repeatability of the EOHST after 10 LTP and LTD cycles in the inhibitory mode is documented in Fig. S17b (ESI†). The recognition accuracy for large and small images reached 80% and 90%, as shown in Fig. 5g and Fig. S18b (ESI†). The classification results of the confusion matrix were similar to those in the excitatory mode, with number “1” maintaining the highest accuracy (1124), while “5” had the lowest correct classification (876).

In psychology, it is recognized that emotions have a significant influence on learning and memory processes.⁴⁶ The EOHST-based reconfigurable synapse was utilized to simulate human visual learning and memory under various emotional states. Based on the difference in learning accuracy across different modes, it can be defined that the higher the accuracy of the hardware learning network, the better the learning performance. The excitatory mode of the device is comparable to a person in a positive emotional state, while the inhibitory mode simulates a negative state. It is evident that individuals tend to learn more efficiently and retain information longer in a positive mood, while learning is slower and forgetfulness occurs more quickly in a negative mood within the same educational environment.^47,48Fig. 5i and j depict the correlation between the selected learning times and the resultant image mappings. These figures demonstrate a clear correlation between the timing of training images and the intensity of visualized pixels. The variations in channel conductance from the LTP/LTD curves directly affect the training results. These figures also demonstrate the simulation of emotional impacts on learning and memory by showcasing the recognition of the numeral “8”. In a positive mood, individuals achieve higher learning efficiency, resulting in clearer retention of the numeral “8” after the learning process. Conversely, a negative mood only yields a vague impression of “8”. Overall, this experiment highlights that individuals tend to learn and retain information more effectively when they are in a better mood, as vividly demonstrated by the EOHST-based reconfigurable transistor.

3.6. Dynamic reconfigurable digital logic processing system

In traditional computing architectures of the past, the physical separation between data processing and storage resulted in high energy consumption and significant delays in data transmission.⁴⁹ Therefore, the ability to perform logical processing and store the results in situ is highly advantageous in order to minimize data migration.⁵⁰ We have designed a dynamically reconfigurable system that integrates the storage logic functions of both AND/OR and NAND/NOR gates. As shown in Fig. 6a, gates G₁, G₂ and G_m are used for input signal, while gate G_m controls the switching between different logic gates in the system. Fig. 6b outlines a schematic of this dynamically reconfigurable logic processing system. When the system is operational, +11 V and −11 V pulses represent the two input signals received by the system. The artificial synapse generates specific post-synaptic potentials under the influence of these stimuli, with the baseline voltage settings of −5/+5 V dictating the system modulated signals for different logic functions (AND/OR and NAND/NOR). These modulating signals also determine whether our synaptic transistor exhibits excitatory or inhibitory response mode. Our system is capable of displaying various synaptic behaviors to identical gate pulses, depending on the selected response mode. Individual logic circuits are reconfigured by toggling between excitatory or inhibitory modes without altering the input signals. Fig. 6c demonstrates the system in an analog AND/OR logic state in excitatory mode (baseline voltage = −5 V). When the G_m input is a negative gate pulse (−11 V, 200 ms), the “AND” logic is simulated. In this scenario, the output current remains below 6.2 nA when G₁ = G₂ = “0”, signifying a logical “0”. Similarly, logic “10” and logic “01” generate a small current under 6.2 nA. Conversely, when both V_G1 and V_G2 are at 11 V, corresponding to logic “11”, a high output current level (>6.2 nA) indicative of a logic “1” is achieved. Transitioning the logic function from an “AND” to an “OR” gate involves altering the G_m input to a positive gate pulse (+11 V, 200 ms). Fig. 6d additionally demonstrates the effective implementation of “NAND” and “NOR” logic in our devices, showcasing the versatility and adaptability of this innovative system.

Fig. 6 Dynamic reconfigurable logic processing system. (a) Schematic illustration of the EOHST device utilized in the dynamically reconfigurable logic system. (b) The schematic of a dynamically reconfigurable logic processing system. (c) Configuration of signal input and output for AND/OR logic in the dynamically reconfigurable logic system. (d) Configuration of signal input and output for the NAND/NOR logic in the dynamically reconfigurable logic system.

4. Conclusions

In summary, we developed an organic synaptic transistor based on a PVN electret using p-type organic semiconductor pentacene films and n-type organic semiconductor PTCDI-C₁₃ films. The device exhibits distinct “V” shaped hysteresis characteristics in the transfer curves across different gate voltage scanning ranges. This balanced bipolar behavior, combined with an effective charge trapping mechanism, enables the transistor to respond to the same gate pulses in various modes (excitatory and inhibitory), displaying dynamically reconfigurable operational states that manifest different synaptic behaviors such as potentiation and depression. Moreover, the device successfully simulates various synaptic behaviors. The LTP/LTD curves in both excitatory and inhibitory modes exhibit low ANL and nonlinearity, significantly enhancing the recognition accuracy of hardware neural networks. Based on the differences in learning accuracy in different modes, the visual learning and memory processes of people in different emotional states were simulated. Additionally, a digital logic processing system was designed to dynamically simulate AND/OR and NAND/NOR logic circuits using the same input voltages across excitatory and inhibitory modes. This dynamically reconfigurable bipolar transistor marks a significant advancement in neuromorphic computing, offering new pathways for creating more efficient and adaptive computational architectures.

Data availability

Data will be made available on request.

Conflicts of interest

There are no conflicts to declare.

Acknowledgements

This work was financially supported by the National Natural Science Foundation of China (62204135 and 12374088), and the Natural Science Foundation of Shandong Province (ZR2021QF046 and ZR2023MA006). The authors would like to thank Shiyanjia Lab (https://www.shiyanjia.com) for the SEM and XRD tests.

Notes and references

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Footnote

† Electronic supplementary information (ESI) available. See DOI: https://doi.org/10.1039/d4tc04363d

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