Toward AI-ready hardware: review of single-crystal halide perovskite FET fabrication and performance

Abstract

This article explores the latest developments in single-crystal halide perovskite field-effect transistors (FETs), focusing specifically on methods to mitigate ion migration and achieve stable operation at room temperature. Following the discussion on the interconnections between dimensionality, lattice softness, and defect statistics, we proceed to examine the methods of solution- and vapor-phase growth that yield layers free of grain boundaries and characterized by a minimal presence of mobile vacancies. The examination of composition tuning, spacer-cation engineering, and interface passivation strategies is conducted to assess their effectiveness in increasing the activation barrier for ionic drift while maintaining electronic transport integrity. Dielectric selection and contact metals are discussed. This review presents a mechanism-focused framework that links crystal dimensionality, ion migration regulation, and device geometry into practical design principles for stable single-crystal perovskite devices. The comparison of device structures, such as coplanar, floated, and vertical architectures, illustrates how field orientation and channel thickness influence the relationship between lattice polarization and carrier accumulation. This analysis outlines a feasible way for converting perovskite FETs to viable, energy-efficient logic, sensing, and photonic circuits suitable for production. The ongoing integration of crystal design and interface engineering is anticipated to address existing stability issues and accelerate the commercial use of flexible and wearable technologies.