Energy-efficient transistors: suppressing the subthreshold swing below the physical limit

Abstract

With the miniaturization of silicon-based electronic components, power consumption is becoming a fundamental issue for micro–nano electronic circuits. The main reason for this is that the scaling of the supply voltage in the ultra-large-scale integrated circuit cannot keep up with the shrinking of the characteristic size of conventional transistors due to the physical limit termed “Boltzmann Tyranny”, in which a gate voltage of at least 60 mV is required to modulate the drain current by one order of magnitude. Accordingly, to solve this problem, several new transistor architectures have been designed to reduce the subthreshold swing (SS) to lower than the fundamental limitation, thus lowering the supply voltage and reducing the power consumption. In this review, we first analytically formulate the SS, summarize the methods for reducing the SS, and propose four new transistor concepts, including tunnelling field-effect transistor, negative capacitance field-effect transistor, impact ionization field-effect transistor, and cold source field-effect transistor. Then, we review their physical mechanisms and optimization methods and consider the potential and drawbacks of these four new transistors. Finally, we discuss the challenges encountered in the investigation of these steep-slope transistors and present the future outlook.