Mass transport and grain growth enable high thermoelectric performance in polycrystalline SnS

Abstract

In polycrystalline SnS, the presence of grain boundaries inherently restricts the improvement of electrical performance, primarily owing to the reduced carrier mobility. In this work, we employ grain boundary engineering to synergistically modulate carrier and phonon transports in SnS through manipulation of mass transport dynamics linked to ramping and holding time-dependent grain evolution during pressure-assisted sintering. The pressure ramping process synergistically modulates grain distribution (grain boundary) and promotes mass transport (defect concentration), thereby jointly strengthening grain boundary and point defect phonon scatterings that reduce lattice thermal conductivity (κlat) by ~30%. During the subsequent holding stage, optimized grain size evolution minimizes grain boundary potential barriers, reducing carrier scattering while elevating carrier mobility to ~30 cm2 V-1 s-1. Hall measurements and phonon frequency calculations corroborate the contributions of point defects and grain boundaries to κlat reduction, while microstructural characterization observations confirm that grain size optimization serves as the primary contributor to enhanced carrier mobility. Ultimately, the optimal sintering sample yields a low κlat of ~1.2 W m-1 K-1 at 303 K and a maximum ZT of ~ 0.8 at 873 K. Our findings highlight the feasibility of high performance polycrystalline SnS through grain boundary engineering, demonstrating its potential for cost-competitive and high energy-efficient thermoelectric applications.