Mengmeng
Li
a,
Felix
Hinkel
a,
Klaus
Müllen
*a and
Wojciech
Pisula
*ab
aMax Planck Institute for Polymer Research, Ackermannweg 10, 55128 Mainz, Germany. E-mail: pisula@mpip-mainz.mpg.de; muellen@mpip-mainz.mpg.de
bDepartment of Molecular Physics, Faculty of Chemistry, Lodz University of Technology, Zeromskiego 116, 90-924 Lodz, Poland
First published on 30th March 2016
In recent years organic field-effect transistors have received extensive attention, however, it is still a great challenge to fabricate monolayer-based devices of conjugated polymers. In this study, one single layer of poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) is directly dip-coated, and its self-assembly is precisely tuned from nanofibers to granular aggregates by controlling the dielectric roughness on a sub-nanometer scale. The charge carrier transport of the monolayer transistor exhibits a strong dependence on the dielectric roughness, which is attributed to the roughness-induced effects of higher densities of grain boundaries and charge trapping sites as well as surface scattering. These results mark a great advance in the bottom-up fabrication of organic electronics.
The surface properties of the dielectric, including chemical composition, surface energy, surface viscoelasticity, and especially surface roughness critically affect the semiconductor film microstructure and charge carrier transport in OFETs.10–13 Early studies demonstrated that the charge carrier mobility of pentacene thin films (50 nm) was strongly dependent on the dielectric roughness, which could be explained by the “roughness valley” theory.14 It was also reported that a dielectric root-mean square roughness (Rms) greater than 0.5 nm severely inhibited the molecular order of poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT, ∼20 nm) so that the charge carrier mobility was significantly reduced.15 In spite of these findings, the precise control of the self-assembly and charge carrier transport of conjugated polymer monolayer transistors has not yet been achieved.
Previously, we proposed an effective solution method to precisely tune the Rms value of the SiO2 surface on a sub-nanometer scale by which the intrinsic role of the interfacial order of organic semiconductors on the charge carrier transport was successfully revealed.16 In the present study, a donor–acceptor copolymer, poly[2,6-(4,4-bis(2-ethylhexyl)-4H-cyclopenta[2,1-b:3,4-b′]-dithiophene)-alt-4,7-(2,1,3-benzothiadiazole)] (PCPDTBT, Fig. 1), is processed into a monolayer by dip-coating which is a known technique to deposit organic semiconductors in a well-defined manner.17–19 Dielectrics with sub-nanometer roughness (S1–S4) are employed to kinetically control the self-assembly of this conjugated polymer monolayer. It is found that a high Rms induces an obvious energy barrier for the polymer chain mobility, so that long-range ordering is severely disrupted. Moreover, the charge carrier transport exhibits a roughness-dependent behavior, and the hole mobility is dramatically decreased from 5.08 ± 0.67 × 10−4 to 1.01 ± 0.22 × 10−4 cm2 V−1 s−1 with increasing Rms from 0.19 to 0.39 nm. Therefore, with the assistance of the sub-nanometer dielectric roughness, the precise control of a conjugated polymer monolayer is successfully achieved from both aspects of self-assembly and charge carrier transport.
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Fig. 1 Schematic illustration of the device configuration. The top is the chemical structure of PCPDTBT, and the bottom is the sub-nanoscale dielectric roughness. |
The dielectric roughness plays a critical role in the microstructure of organic semiconducting layers. Most previous studies reported the use of dielectrics with a roughness in the nanometer range by which the molecular order was severely destroyed in the entire film.14,15 In contrast, we found that roughness within a sub-nanometer scale allows the precise tuning of the self-assembly of organic semiconductors in monolayers.16 This sub-nanometer roughness is obtained by spin-coating a hydrolyzed tetramethyl orthosilicate (TMOS) solution on silicon wafers. This spin-coated layer is annealed at high temperature resulting in the formation of a 10 nm-thick SiO2 layer on the silicon wafer. The preparation details are described in the Experimental section. In comparison with a native oxide layer of the commercial silicon wafer (300 nm), the capacity change due to the slight thickness increase (∼10 nm) can be neglected. In this way, the dielectric roughness can be precisely modified from Rms = 0.19 to Rms = 0.39 nm (S1–S4, Table S1†). The Rms of the bare SiO2 substrate is ∼0.2 nm that is similar to the value of S1. It has been already proven that the conjugated polymer deposited on the bare SiO2 substrate exhibited an identical morphology and device performance to the one on S1.16
S1 has the smoothest surface with a Rms value of 0.19 nm, which is a little smaller than that of the commercial silicon wafer (∼0.2 nm). As determined by AFM, the PCPDTBT monolayer deposited on S1 is also composed of nanofibers with a 10 nm diameter which is identical to that on the silicon wafer (Fig. 2a, b and 3a, e). The charge carrier transport of the PCPDTBT monolayer is quantitatively evaluated by fabricating OFET devices. A top-contact bottom-gate configuration is employed based on the following considerations (Fig. 1). Firstly, top-contact transistors usually show a higher mobility than devices with a bottom-contact architecture,20c,d and this difference is even more pronounced for ultrathin films.20e The higher contact resistance in the bottom-contact device is attributed to a lower contact area between source/drain (S/D) electrodes and the semiconductor layer.20f Secondly, the bottom-contact transistor often leads to a poor morphology around the S/D electrodes bearing a detrimental influence on the charge carrier transport.20f The device fabrication is described in detail in the Experimental section. Before OFET measurement, the PCPDTBT monolayer is annealed at 120 °C for 30 min to remove the residual solvent. This posttreatment rarely has an influence on the microstructure of the deposited polymer monolayers.16 On the other hand, the specific transfer and output plots of the polymer monolayer on S1 exhibit a typical linear/saturation behavior, as shown in Fig. 4a and e. At a gate voltage (VGS) of −80 V, the drain current (−IDS) reaches 0.2 μA. The saturation mobility in holes (μh) of this monolayer transistor is 5.08 ± 0.67 × 10−4 cm2 V−1 s−1, with the maximum value of 6.42 × 10−4 cm2 V−1 s−1. It is worth pointing out that no field-effect characteristics were observed for the single layer of organic semiconductors in many cases.17,18,21 In addition, it must be emphasized that this μh value is not optimized and is underestimated because (i) no special surface treatment for the dielectric is applied, such as the use of self-assembled monolayers (SAMs) to reduce the trapping sites for charge carriers; (ii) the mobility extraction from transfer plots is carried out for a fully covered monolayer which is not the case for S1. The on/off ratio of the monolayer on S1 is around 103.
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Fig. 4 (a–d) Transfer curves of PCPDTBT monolayers dip-coated on S1–S4 and (e–h) are the corresponding output curves. In the transfer plots a source–drain voltage (VDS) of −80 V is applied. |
Increasing Rms to 0.27 nm (S2) does not lead to a significant change in the morphology. The nanofiber based monolayer is still obvious, as determined by the AFM height and phase images (Fig. 3b and f). The monolayer on S2 exhibits a hole mobility of 3.65 ± 0.13 × 10−4 cm2 V−1 s−1 and an on/off ratio of 102–103 (Fig. 4b and f). In comparison with the monolayer on S1, the μh value is reduced by 28%, which can be attributed to two aspects. Firstly, more trapping sites are induced by a higher Rms so that the charge carrier transport is decreased. Secondly, the surface scattering on charge carriers is intensified, hindering the movement of charge carriers along the working channel.14,22 With a further increase in the dielectric roughness to 0.30 nm (S3), the chain mobility of the conjugated polymer is continuously decreased, which results in a lower propensity to self-assemble (Fig. 3c and g). Consequently, the hole transport of the PCPDTBT monolayer gradually deteriorates with a charge carrier mobility of 3.40 ± 0.59 × 10−4 cm2 V−1 s−1 (Fig. 4c and g). The output characteristics in Fig. 4f and g reveal a nonlinear behavior of IDS at a low VDS indicating contact resistance and charge injection limitation.23,24
When a dielectric with a higher Rms value (S4) is utilized to deposit the PCPDTBT monolayer, the long-range ordering of PCPDTBT is significantly hindered, with a transition of the polymer self-assembly from an ordered (nanofibers) to a disordered microstructure (granular aggregates) (Fig. 3d and h). This transition originates from the insufficient chain mobility of the conjugated polymer which cannot overcome the roughness-induced barrier and is hampered in the self-organization into nanofibers.25 The monolayer on S4 reveals not only a much poorer organization, but also more grain boundaries resulting in a low μh value of 1.01 ± 0.22 × 10−4 cm2 V−1 s−1. This decline in hole mobility correlates well with the decrease in −IDS by approximately one order of magnitude from 0.2 to 0.03 μA (Fig. 4d and h). Furthermore, the transfer curve at a low VGS exhibits a more obvious trapping effect as well as a higher turn-on voltage. In addition, both transfer and output characteristics of the monolayer on S4 indicate a stronger effect of contact resistance and charge injection limitation.17
The roughness-dependent behavior of the charge carrier mobility is summarized in Fig. 5a. It can be clearly seen that the hole mobility is reduced with increasing the value of Rms, which is in good agreement with the reported “roughness valley” theory.14 Besides the increased density of charge trapping and surface scattering induced by a higher Rms, the molecular order is another factor responsible for the 5-fold decline in the charge carrier transport, as shown in Fig. 5b. In contrast to the highly organized monolayer on a smooth dielectric such as S1, the molecular self-assembly is severely inhibited by the roughness-induced barrier (S4). This leads to a poor molecular ordering and more grain boundaries, and finally as a consequence hinders the transport of charge carriers. It is worth noting that the decrease in mobility is less than one order of magnitude in spite of significant changes in the film microstructure. This is reasonable because the long polymer chains are effective to bridge the ordered domains providing sufficient pathways for charge carriers.26,27 Additionally, the bridging effect of polymer chains may contribute to the unchanged on/off ratio and threshold voltage, as shown in Table S3.†26,27
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Fig. 5 (a) Relationship between hole mobility and dielectric roughness. (b) Illustration of the molecular order on smooth (S1) and rough (S4) dielectrics. |
Therefore, the precise control over the self-assembly and charge carrier transport of conjugated polymer monolayers is successfully achieved with the assistance of the sub-nanometer dielectric roughness. It is still a big challenge to fabricate working transistors based on a polymer monolayer.17,18,21 In spite of the hole mobility of 10−4 cm2 V−1 s−1 in this study, these results mark a great advance in the bottom-up fabrication of organic electronics, especially for conjugated polymers. Most importantly, this study provides further evidence for the possibility of kinetically controlling the self-assembly and charge carrier transport of conjugated polymer monolayers. Therefore, the sub-nanometer dielectric roughness prepared by our method can be considered as a promising tool for interfacial engineering in the field of organic electronics. In this way, the self-assembly and charge carrier transport in a monolayer can be precisely tuned.
Footnote |
† Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr01082b |
This journal is © The Royal Society of Chemistry 2016 |