Nanoscale surface engineering of a high-k ZrO2/SiO2 gate insulator for a high performance ITZO TFT via plasma-enhanced atomic layer deposition

Abstract

We investigated a high dielectric constant (k) gate insulator (GI) based on the tandem structure of ZrO₂ and SiO₂ to optimize a high performance oxide thin-film transistor (TFT). We analyzed tandem structures with various SiO₂ thicknesses to simultaneously achieve higher ZrO₂k values and better SiO₂ interfacial properties for the In–Sn–Zn-oxide (ITZO) TFT. The TFT exhibited significantly enhanced operational characteristics at a specific SiO₂ thickness compared to the GI structures of only ZrO₂ or SiO₂. We determined the mechanism involved in this improvement by adapting various chemical analysis methods. The optimized tandem-structured GI achieved device stability under positive-bias-and-temperature stress test conditions. Consequently, we evaluated the GI optimization criteria for the development of high performance TFTs. We determined the optimized tandem structure properties with k value, effective mobility, subthreshold swing, and hysteresis of 17.4, 27.7 cm² V⁻¹ s⁻¹, 0.17 V dec⁻¹, and 0.11 V, respectively, for 8 nm SiO₂ on ZrO₂.