Rear textured p-type high temperature passivating contacts and their implementation in perovskite/silicon tandem cells

Silicon solar cells based on high temperature passivating contacts are becoming mainstream in the photovoltaic industry. Here, we developed a high-quality boron-doped poly-silicon hole contact. When combined with a co-processed phosphorus-doped poly-silicon electron contact, high-voltage silicon bottom cells could be demonstrated and included in 28.25%-efficient perovskite/Si tandems. The active area was 4 cm2 active area and the front electrode was screen-printed.


Fabrication details
HTPC bottom cells development: Symmetrical samples were first realized on n-and p-type wafers to assess the potential of the passivating contacts on both wafer polarities and to optimize the tunnel oxide growth.For that purpose, planar float zone (FZ) n-type and textured FZ p-type wafers (4") were used with a thickness of ~190 µm and a resistivity of ~2 Ω•cm.After standard wafer cleaning, a ~1.2 nm-thick SiO x layer was grown by UV-O 3 exposure.On n-type wafers, a phosphorus-doped silicon layer with few %at of carbon (SiC x (n)) with a thickness of 35 nm was symmetrically deposited by plasma enhanced chemical vapor deposition (PECVD).On p-type textured wafers, a boron-doped silicon carbon (SiC x (p)) film with a thickness of 45 nm (on flat) was symmetrically deposited by PECVD.Both layers were annealed in a tube furnace at 850°C, typically with a dwell time of 15 min.After annealing, SiN x :H was deposited by PECVD, followed by firing at 800°C in an inline furnace.After stripping of the SiN x :H in HF, ITO was deposited by sputtering through a hard metallic mask to define the contact geometry used for contact resistance (ρ c ) measurements.For solar cell fabrication, we used FZ n-type and p-type wafers (4") that are single-side textured with a thickness of ~190 µm and a resistivity of ~2 Ω•cm.After standard wafer cleaning and SiO x growth, SiC x (p) was deposited on the rear textured side and SiC x (n) on the planar front side.Same annealing, firing, and SiN x processing steps as for the symmetrical test samples were applied.
Perovskite top cell deposition and tandem processing: 2-terminal PK/Si HTPC tandem cells were prepared on rear-side textured bottom cells.A thin, 10 nm, ITO recombination junction was deposited by sputtering through a shadow mask on the front SiC(n).The hole transport layer consisted in a Self-Assembled Monolayer of Me-4PACz deposited by spin-coating from a 1 mM solution in ethanol, followed by an annealing at 100°C for 10 min.Subsequently a solution of SiO 2 nanoparticle dispersed in ethanol was deposited on top of the SAM by spin-coating to improve the wetting of the perovskite ink. 1,2The perovskite (PK) absorber was deposited via spin-coating following an anti-solvent route similar to that described by B. A. Kamino et al. 3 .An electron transport layer (ETL) stack of LiF/C60 was thermally evaporated on top of the perovskite, followed by atomic layer deposition (ALD) of a SnO x buffer layer (~10 nm).A 65 nm-thick ITO contact was then sputtered through a shadow mask.Finally, a low-temperature screen-printed Ag metallization was applied to finish the front contact and ~100 nm of LiF was thermally deposited as the antireflective coating.All cells were processed on full 4" Si bottom cells.The active area of the tandems is defined by the size of the electrodes.

Device characterization
A Sinton WCT-120 system was used to measure the minority carrier lifetime (τ eff ) and to determine the implied open circuit voltage (iV OC ) of the bottom cells.Spatial homogeneity of the passivation was observed using photoluminescence imaging (PLI).Transfer length measurements were used for ρ c measurements.
Illuminated JV curves were recorded on a large-area class A+A+A+ solar simulator from WACOM using a two-light source (xenon and halogen).The solar simulator light intensity was verified with an externally calibrated reference cell to match the 1-sun AM1.5G equivalent intensity.The spectral balance was then checked by means of two filtered externally calibrated cells to ensure proper balance between the two sub-cells of the tandem.All measurements were done using a four-point method.All cells were measured on a metallic vacuum chuck with an active temperature control set to 25°C.Cells areas were masked with laser cut aperture masks whose opened areas were optically measured.All cells were measured from 1.9 V to -0.2 V and from -0.2 V to 1.9 V with a scan rate of ~191 mV/s.Maximum power point tracking was performed using an in-house tracking algorithm which actively modifies the voltage.
External quantum efficiency measurements were made using a custom setup made in house.The calibration of the EQE was made using an externally calibrated cell.EQE measurements for the cells were made at a chopping frequency of approximately 230 Hz.Blue and red light biases were used to saturate the top and bottom cells, respectively.

Large area tandem
A large area tandem was realized using the same type of bottom HTPC cell.For this, the top cell was deposited following the same procedure described above.The larger active area was simply defined by using a large area shadow mask for the deposition of the front ITO contact, followed by the screen printing of a full area metallization.The total active area is 57.4 cm 2 .

Figure S2 .
Figure S2.Picture of a large area tandem on a 4" wafer.The active area is 57.4 cm 2 (left).JV curve and MPP tracking (inset) of a corresponding tandem device (right).

Table S1 :
Selection of non-SHJ 2T tandems reported to date