Numerical simulation of lead-free vacancy ordered Cs2PtI6 based perovskite solar cell using SCAPS-1D

In recent years, vacancy-ordered halide double perovskites have emerged as promising non-toxic and stable alternatives for their lead-based counterparts in optoelectronic applications. In particular, vacancy ordered Cs2PtI6 has emerged as a star material because of its high absorption coefficient, band gap of 1.37 eV, and long minority carrier lifetime. Despite substantial experimental research on this new class of material, theoretical simulations of their device properties remain scarce. In this work, a novel n-i-p device architecture (FTO/SnO2/Cs2PtI6/MoO3/C) is theoretically investigated using a solar cell capacitance simulator (SCAPS-1D). Theoretical investigations are carried out in order to optimize the device performance structure by varying the perovskite and selective charge transport layer thickness, absorber and interface defect density, operating temperature, back contact, series and shunt resistance, respectively. The optimized device showed an impressive power conversion efficiency (PCE) of 23.52% at 300 K, which is higher than the previously reported values. Subsequent analysis of the device's spectral response indicated that it possessed 98.9% quantum efficiency (QE) and was visibly active. These findings will provide theoretical guidelines for enhancing the performance of Cs2PtI6-based photovoltaic solar cells (PSCs) and pave the way for the widespread implementation of environmentally benign and stable perovskites.


Introduction
2][3][4] In just over a decade, the PCE has dramatically increased from 3.3% to 25.7% due to the synergistic optimization of device interfaces.Full industrialization of HPSCs, in spite of having achieved a PCE of over 25% is trammeled by two main issues: Pb toxicity and instability.][7][8][9][10] Consequently, it would be highly advantageous for device lifetimes and environmental and health considerations regarding production and reprocessing to seek out non-toxic and stable perovskites that sustain high efficiency.][13][14][15][16][17][18][19][20][21] Finding stable, non-toxic, and highly efficient perovskites has proven to be an enormous problem to date.In recent years, A 2 BX 6 (A]Cs; B]Te, Sn, Pt, Ti; X]I) double perovskites have garnered the attention of numerous researchers.These leadfree double perovskites demonstrate good stability and appropriate band gaps, making them viable candidates for future solar cell applications.As one of the most extensively studied vacancy-ordered halide double perovskites, Cs 2 SnI 6 is a defect version of the three-dimensional (3D) CsSnI 3 perovskite with half of the Sn atoms in the Sn-centered octahedron absent.In the fabrication of solar cells, the inefficiency of Cs 2 SnI 6 is a problem.Cs 2 SnI 6 -based solar cells have an efficiency of approximately 1.5%, while Cs 2 SnI 4 Br 2 -based solar cells with mixed halides have an efficiency of 2.025%.
Cs 2 PtI 6 is one of the intriguing materials in the A 2 BX 6 class.Cs 2 PtI 6 is an ideal option for PSCs due to its higher carrier mobility, higher absorption coefficient (4 × 10 5 cm −1 ), narrow band gap (1.37 eV), and dynamically stable structure. 22With a tolerance factor of 0.97, it is able to have a highly consistent cubic structure, hence increasing its stability.It is stable under harsh conditions, including high temperatures, UV light, and high humidity. 23It could serve as an appropriate substitute for perovskite-containing lead due to its oxidation resistance, high atomic number, and stability beyond non-toxicity.Cs 2 PtI 6 is a highly advantageous photovoltaic material due to all of these qualities.
Unfortunately, systematic simulation and device modeling for the properties of Cs 2 PtI 6 perovskite, which are essential for their optoelectronic devices, are rarely investigated, resulting in subpar device performance.To further improve the performance of Cs 2 PtI 6 -based PSCs, it is required to construct a band structure that minimizes charge recombination while enhancing carrier separation and transport.For this objective, device simulation is used to gain a comprehensive understanding of the relationship between the properties of materials and performance parameters.Using SCAPS-1D, a novel n-i-p device architecture (FTO/SnO 2 /Cs 2 PtI 6 /MoO 3 /C) is theoretically investigated in this work.Theoretical investigations were conducted to optimize the performance structure of the device by varying the thickness of the perovskite and selective charge transport layer, the absorber and interface defect density, the operating temperature, the back contact, the series and shunt resistance, respectively.At 300 K, the improved device demonstrated an outstanding PCE of 23.52%, which is greater than the previously reported gures.These ndings will provide theoretical recommendations for boosting the performance of Cs 2 PtI 6 -based PSCs and pave the way for the broad adoption of environmentally friendly and stable perovskites.

Theoretical simulation
For our numerical simulations, we used SCAPS-1D soware version 3.3.10.In SCAPS-1D a total of seven layers, along with different front and back contacts, could be employed as input.
One can analyze J-V characteristics, ac characteristics (C-f and C-V), device efficiency (h), open circuit voltage (V oc ), ll factor (FF), short circuit current density (J sc ), spectral response (QE) of device using SCAPS-1D.The simulations are based on three equations: Poisson's eqn (1) and continuity equation for holes and electrons eqn (2): where j is electrostatic potential, n and p are electron and hole concentrations, 3 o is vacuum and 3 r is relative permittivity, N D and N A are donor and acceptor doping density, r n , r p are electrons and holes distribution, where G is generation rate and R is recombination rate, J p and J n are holes and electron current densities.Carrier transport occurs according to dri and diffusion equations: In order to achieve a higher level of efficiency, the hole transport layer (HTL) and electron transport layer (ETL) must have band gap edges that correspond with the VBM and CBM of the active layers.Fig. 1 and 2 illustrate the band gap alignment of MoO 3 , SnO 2 , and Cs 2 PtI 6 , as well as the back and front device contacts.The lowest unoccupied molecular orbital (LUMO) of SnO 2 (ETL) is in excellent alignment with the conduction band of Cs 2 PtI 6 .Likewise, the highest occupied molecular orbital (HOMO) of MoO 3 (HTL) is well-aligned with the valence band level of an absorbing material.
Table 1 displays the input parameters for FTO, SnO 2 , Cs 2 PtI 6 , and MoO 3 derived from the literature.The work functions of front contact (FTO) and back contact (carbon) are 4.4 eV and 5.0 eV, respectively.Thermal velocity of both holes and electrons is 1 × 10 7 (at 300 K).For all defects, defect type is taken as neutral, characteristic energy is 1.0 eV, energetic distribution is single.Defect density for both interfaces is 1 × 10 13 , capture cross-section of electrons and holes is 1 × 10 18 .All simulations were performed under AM 1.5 spectra, constant illumination 1000 W m −2 , working temperature 300 K, shunt resistance 4200 U cm 2 and series resistance 1 U cm 2 .

Effect of HTL thickness
To ensure that the same number of charge carriers reach terminals instantaneously with a low recombination probability, the thickness of the HTL is generally higher than that of the electron transport layer.In general, the recombination rate increases as the HTL's thickness decreases.Fig. 3 illustrates the impact of HTL thickness on device properties.Here, MoO 3 thickness ranged from 20 to 100 nm.Both V oc and J sc increased with increasing MoO 3 thickness (Table S1 †), reaching saturation at 32 nm with a maximum of 26.163 mA cm −2 and 1.14 V, respectively.Both PCE and FF increased with increasing thickness until reaching a maximum value, aer which they reduced till reaching a constant value.
When the HTL thickness is too thin, current leakage and low shunt resistance can occur, resulting in a lower FF. 28In our case, it decreased aer reaching the highest FF value of 80.44% at 22 nm.It could be because increasing HTL thickness increased series resistance, causing the FF to drop to 75.74% at 60 nm before remaining unchanged. 28At 24 nm, the maximum efficiency of 23.13%, V oc of 1.118 V, J sc of 26.158 mA cm −2 , and FF of 79.105% was obtained.Thus, the optimum HTL thickness of 24 nm was utilized for our subsequent devices.

Effect of absorbing layer thickness
In designing a solar cell, the thickness of the perovskite is crucial because it directly affects the device parameters.Because electron-hole pair generation occurs in the absorbing layer, increasing thickness increases incident light absorption and generates more electron-hole pairs.This increases the device's   PCE, but only up to a certain point, aer which efficiency degrades.In this case, the perovskite thickness should not exceed the carrier diffusion length; otherwise, recombination and back contact recombination density would increase.The inuence of absorbing layer thickness on PCE, J sc , V oc , and FF is shown in Fig. 4 and Table S2 †.Here, the Cs 2 PtI 6 thickness was varied from 100 nm to 1000 nm.J sc increased as perovskite thickness increased.Because Cs 2 PtI 6 has a higher absorption coefficient (4 × 10 5 cm −1 ), 22 increasing thickness allows more light to be absorbed, resulting in more electron-hole pair generation.Although the length of charge carrier diffusion in these perovskites is also longer, these electron-hole pairs can reach the corresponding electrodes to generate power. 29The J sc at 680 nm reached a maximum of 30.37 mA cm −2 before  decreasing.These ndings are consistent with previously reported data. 30CE also increased as the thickness increased, but only up to 400 nm, where the maximum efficiency of 23.8% is observed, and then it decreased.As a result of a higher absorption coef-cient, a higher number of charge carriers are generated, resulting in the maximum possible increase in efficiency.
Following this optimal thickness, PCE decreased.Despite the higher level of electron and hole generation, the perovskite thickness exceeds the carrier diffusion length of electrons and holes, resulting in increased recombination rates and decreased efficiency.When thickness increases, so do pinholes, cracks, and traps, resulting in a decline in PCE.V oc increased with perovskite thickness until it reached a maximum of 1.11 V at 260 nm, aer which it dropped precipitously.V oc is dened as: where n is an ideality factor, q is the electrical charge, T is temperature, k is the Boltzmann constant, I o is the dark saturation current, and I L is light generated current.V oc is affected by cracks, pinholes, and other layer defects and is dependent on surface morphology.The absorber layer is relatively thinner during the early increase in V oc , resulting in a lower recombination rate.Furthermore, as the length of the diffusion carrier increases, so does the value of the dark saturation current.This slower recombination rate eventually leads to a higher concentration of carriers, which raises the lightgenerated current I L .However, as the thickness of the absorbing layer continues to increase, the recombination rate, along with I o , increases, causing the V oc to fall abruptly and squarely. 29The FF relates to charge route resistance and represents the efficiency with which holes and electrons transit the cell without loss. 31,32As the perovskite's thickness increased, the ll factor decreased.FF decreased from 78.3% at 100 nm to 43.29% at 1000 nm as the thickness increased.

Effect of ETL thickness
The dependence of solar cell properties on ETL (SnO 2 ) was studied by varying the thickness of the electron transport layer from 10 nm to 100 nm (Table S3 †).To prevent incident photons from being absorbed and producing electron-hole pairs in the electron transport layer, it is common to practice keeping the ntype layer (ETL) thinner than the equivalent p-type layer (HTL).
ETL is also kept thinner to allow incident photons to pass through to the absorber and HTLs beneath it.The inuence of ETL thickness change on cell metrics is depicted in Fig. 5.By increasing ETL thickness, no improvement in cell metrics was observed.PCE, V oc , J sc , and FF were 23.52%, 1.11782 V, 26.95 mA  cm −2 , and 78.076% at 10 nm, and 23.49%, 1.11780 V, 26.93 mA cm −2 , and 78.078% at 100 nm, respectively.With the increase in ETL thickness, the change in V oc was insignicant (from 1.11782 V to 1.11780 V, a loss of just 0.0017%), indicating that by varying the thickness of SnO 2 ETL, charge carrier leakage at the interface is limited.When the thickness of a device grows, fewer electron-hole pairs are formed, and charge carrier recombination occurs, resulting in a drop in overall device efficiency.Our optimal device has an ETL thickness of 10 nm, with PCE of 23.52%, J sc of 26.95 mA cm −2 , V oc of 1.1178 V, and FF of 8.076%.

Perovskite (absorber) layer defect density
The optoelectronic properties of an absorbent layer are highly dependent on its preparation method, thickness, and analysis methodologies.Furthermore, defects in the system could change the optoelectronic properties.Defects were introduced into the absorbent layer to make our device appear more realistic.The defect density ranged from 10 14 -10 20 cm −3 .Fig. 6 depicts the effect of Cs 2 PtI 6 defect density on cell parameters.The recombination rate increases and all cell characteristics decrease as the number of cracks and pinholes increases due to an increase in N t .An efficiency of 26% was observed with a defect density of 1 × 10 15 cm −3 .We chose a defect density of 1 × 10 17 cm −3 for our device, which yielded an efficiency of 23.5% (Table 2).Material defects must be reduced in order for the device to be effective, and it must be smooth and free of cracks.

Effect of interface defect density
Due to a mismatch in the crystallographic structures of the ETL, HTL, and absorbing layer, interfaces with a plethora of dislocations could form, hence reducing junction quality and triggering recombination.The defect density was varied between 10 12 cm −3 and 10 18 cm −3 to explore the global impact of interface defect density on cell performance.Fig. 7 depicts the impact of interface defect density on cell characteristics.There was no signicant change in PCE and V oc when the defect density of the ETL/perovskite layer (SnO 2 /Cs 2 PtI 6 ) was varied (Table S4 †).However, with the increase in the interface defect density of the HTL/perovskite layer (MoO 3 /Cs 2 PtI 6 ), the efficiency and V oc drastically degraded (Table S5 †).The cell's PCE decreased from 23.8% at 10 12 N t to 19.04% at 10 18 N t .V oc tumbled by 23%, from 1.156 V to 0.888 V.
As N t increases, there is no discernible change in J sc .It only decreases when the prevalence of interface defects increases.By increasing the N t of the HTL/P layer to 10 18 cm −3 (from 26.94 mA cm −2 to 26.62 mA cm −2 ), J sc decreased by 1.19%.Both interfaces have an effect on the ll factor.The ll factor decreased from 78.08% to 77.08% when ETL/perovskite defects increased.In the case of the HTL/perovskite layer, the defect density increased from 76.42% to an all-time high of 81.2% at N t 10 15 cm −3 , before decreasing to 79.90% at defect density 10 18 cm −3 .We have selected a defect density of 10 13 cm −3 for both device interfaces.

Effect of temperature
Temperature has a direct effect on hole mobility, electron mobility, and carrier concentration, all of which affect cell performance. 33The device's performance was investigated at temperatures ranging from 290 K to 400 K. Eqn (5) shows the effect of temperature on V oc : 34 where V oc is open circuit voltage, K is Boltzmann constant, q is the electronic charge, n is ideality constant, T is temperature, J o is reverse saturation current and J sc is current density.It has been observed that with the increase in the operating temperature, reverse saturation current density increases, and V oc decreases exponentially. 35Fig. 8 and Table S6 † depict the effect of temperature on device performance.All cell metrics degraded with each increase in temperature.V oc decreased from 1.12295 V at 290 K to 1.02557 V at 400 K.The FF decreased from 78.31% to 69.98%.There was no discernible change in the device's current density.It decreased by 0.09% from 26.9536 to 26.9282 mA cm −2 .The device's PCE fell from 23.7% to 19.0%.As the temperature rises, the phonons are triggered, increasing charge carrier scattering, this modies the material's conductivity.As a result, overall performance declined.For our device, we have chosen an optimal working temperature of 300 K where PCE is 23.52%, V oc is 1.11782 V, J sc is 26.9519 mA cm −2 and FF is 78.07%.

Effect of resistance on device parameters
Device performance is immensely inuenced by both series and shunt resistance.Series resistance is due to interfaces, back and front contact, and resistance to ow of current while R sh is the aereffect of reverse saturation current.Both high R sh and low R s are likely to deliver better device performance.The effect of R s and R sh on device parameters was studied by altering values between 0.01-50 U cm 2 and 10-10000 U cm 2 .Eqn ( 6) can be used to understand the effect of resistance on device performance: 34 where I sc is short circuit current, R sh is shunt resistance, R s is series resistance, I L is light induced current, and I O is reverse saturation current.According to the above equation, when series resistance increases, short circuit current will decrease.This would have a direct effect on the device's efficiency and FF.The impact of series and shunt resistance on device parameters is seen in Fig. 9. PCE and FF drop as R s increases, but J sc is only affected at higher R s levels and V oc is unaffected.At R s 0.01 U cm 2 , a PCE high of 24.1% is measured.PCE dropped to 6.03% as the value of R s increased from 0.01 to 50 U cm 2 .Similar to PCE, the ll factor decreased from 79.9% to 25.57% (Table 3).The initial increase in resistance had little effect on the J sc , but at 50 U cm 2 , it decreased from 26.959 mA cm −2 to 21.068 mA cm −2 .In case of R sh , both PCE and FF increased with an increase in R sh but only at low R s , V oc isn't much affected by R sh while J sc increased with increase in R sh .These ndings are consistent with those of other researchers.Hence, for improved device performance, the series resistance should be kept low while shunt resistance should be kept high.

Quantum efficiency studies
Quantum efficiency (QE) is the probability that an incident photon will transfer an electron to the device's external circuit.Yet, this property is independent of the incident spectrum.Fig. 10 demonstrates the effect of absorbing layer thickness on quantum efficiency for wavelengths between 300 and 900 nm.QE increased with increasing perovskite thickness up to a maximum of 98.9% before declining.At 100 nm, the QE was 70%.At 400 nm, the concentration increased from 91.6% at 200 nm to 98.85%.A further increase in thickness did not result in a signicant increase in QE, as QE at 500 nm was already 98.9%.QE decreased to 86.1% at 1000 nm as thickness rose further.In the range of 354-550 nm, high quantum efficiency was observed.As its thickness increased, its wavelength range changed towards longer values.Maximum QE was observed at the same wavelength (354.5 nm) for perovskite thicknesses between 100 nm and 600 nm, however as thickness increased, this wavelength shied to longer wavelengths.The high QE of perovskite is due to its high absorption coefficient (4 × 10 5 cm −1 ). 22This study demonstrates that Cs 2 PtI 6 is optically active and may have additional applications in photovoltaics.

Effect of back contact on device parameters
The back contact of solar cells is essential to their performance because it absorbs electrons from the absorbing layer.For     We have reported the design optimization of an ecologically friendly, lead-free planar Cs 2 PtI 6 solar cell using MoO 3 as the HTL and SnO 2 as the ETL (Table 5).Our research demonstrates that MoO 3 (HTL), Cs 2 PtI 6 , and SnO 2 have a considerable effect on device performance.The impact of varying the defect densities of the interface and absorber layers demonstrated that these parameters are crucial for device performance and that fewer defects are necessary for improved device performance.It was determined that series resistance had little inuence on V oc but a substantial effect on PCE, FF, and J sc .Effect of shunt resistance showed that both PCE and FF increase with an increase in R sh (at low R s ), V oc isn't much affected by R sh while J sc increases with an increase in R sh .In addition, the effect of temperature on the device's functionality revealed that lower temperatures led to improved performance.The material's spectral response revealed that it was active.Cu, Ni, Ag, Fe, Go, and C were employed as back contacts, with C's work function of 5.0 eV being the best.The optimal device was the n-i-p device with the structure FTO/SnO 2 /Cs 2 PtI 6 /MoO 3 /C with a PCE of 23.52% (V oc of 1.118 V, J sc of 26.95 mA cm −2 , FF of 78.08%).

Fig. 8
Fig. 8 Influence of changing operating temperature (290-400 K) on parameters of cell configuration FTO/SnO 2 /Cs 2 PtI 6 /MoO 3 /C (a) PCE and FF, (b) V oc and J sc , (c) a comparison of J-V curves of device at different temperatures.

Fig. 9
illustrates the effect of the back contact work function on the device's properties.Cu, Ni, Ag, Fe, GO, and C were used as back contact materials in our device.As work function increased, efficiency grew, beginning at 13.14% with Cu as the back contact and reaching a high of 23.52% with carbon as the back contact.The other cell metrics likewise improved when the back contact's work function increased.As the work function of the back contact increases, the barrier height for charge carriers at the back contact decreases, leading to an overall improvement in cell characteristics.Table 4 compares cell properties to the work function of the back contact (Fig. 11 and 12).

Fig. 11
Fig. 11 Device performance as a function of back contact work function for cell configuration FTO/SnO 2 /Cs 2 PtI 6 /MoO 3 /C (a) PCE and FF, (b) V oc and J sc , (c) J-V curve of device with different back contacts.

Table 1
Input parameters for materials used in the device architecture FTO/SnO 2 /Cs 2 PtI 6 /MoO 3 /C

Table 3
Solar cell parameters at different values of series resistance R S (U cm 2 ) for configuration FTO/SnO 2 /Cs 2 PtI 6 /MoO 3 /C

Table 4
Solar cell parameters at different values of back contact work function (eV) for configuration FTO/SnO 2 /Cs 2 PtI 6 /MoO 3 /C oc (V) J sc (mA cm −2 ) FF (%) PCE (%) ohmic contact with the HTL or the absorber layer, a high work function is necessary.

Table 5
Performance comparison of our work and preceding work on Cs 2 PtI 6 based PSCs