Fully in situ Nb/InAs-nanowire Josephson junctions by selective-area growth and shadow evaporation

Josephson junctions based on InAs semiconducting nanowires and Nb superconducting electrodes are fabricated in situ by a special shadow evaporation scheme for the superconductor electrode. Compared to other metallic superconductors such as Al, Nb has the advantage of a larger superconducting gap which allows operation at higher temperatures and magnetic fields. Our junctions are fabricated by shadow evaporation of Nb on pairs of InAs nanowires grown selectively on two adjacent tilted Si (111) facets and crossing each other at a small distance. The upper wire relative to the deposition source acts as a shadow mask determining the gap of the superconducting electrodes on the lower nanowire. Electron microscopy measurements show that the fully in situ fabrication method gives a clean InAs/Nb interface. A clear Josephson supercurrent is observed in the current–voltage characteristics, which can be controlled by a bottom gate. The large excess current indicates a high junction transparency. Under microwave radiation, pronounced integer Shapiro steps are observed suggesting a sinusoidal current–phase relation. Owing to the large critical field of Nb, the Josephson supercurrent can be maintained to magnetic fields exceeding 1 T. Our results show that in situ prepared Nb/InAs nanowire contacts are very interesting candidates for superconducting quantum circuits requiring large magnetic fields.

Here, we provide additional information of the 3-step electron beam (e-beam) lithography fabrication process of the pre-patterned Si substrate for the specially designed selective growth of the InAs NWs. Images obtained with scanning electron microscope (SEM) after the second and third step are presented in Figure S1. An array of 3 µm wide squares with a pitch of 10 µm defined in the 20 nm SiO 2 layer covering Si(100) substrate is shown in Figure S1 (a). The patterned SiO 2 layer is used as a mask for etching in the Si (100) substrate 300 nm deep square-shaped troughs with Si(111) facets. Such a trough looks like in Figure S1 (b). The final result of the substrate preparation is illustrated in Figure S1 (c): pairs of 80 nm wide holes are etched in the SiO 2 layer covering adjacent Si(111) facets of a trough. Finally, a focus ion beam (FIB) cross-sectional cut of such a hole on the Si (111) facet is depicted in Figure S1 (d).
1 Electronic Supplementary Material (ESI) for Nanoscale Advances. This journal is © The Royal Society of Chemistry 2021

Issues related to the substrate preparation and nanowire growth
During the development of the substrate preparation various issues occurred. Resist sticking problems (cf. Figure S3 (a)) have been tackled by treating the SiO 2 surface with O 2 plasma (power 200 W, flow 300 SCCM) and using HMDS baked at 130 • C before spinning the resist. Oxide irregular growth on different Si facets together with not optimised etching parameters are the causes of the parasitic growth shown in Figure S3 (b). By growing a sufficiently thick oxide on Si (100) and Si (111) facets, i.e. 18 nm and 25 nm, respectively and adjusting the RIE and HF etching parameters this problem could be resolved. In order to prevent stunted nanowire growth (cf. Figure S3 (c)), a moderately high As flux of 3.5×10 −5 torr was used during the nanowire growth. If the dose for e-beam writing is too high, the holes in the SiO 2 layer are getting too large. This results in the growth of two nanowires per hole, as can be seen in Figure S3 (d). To avoid this, the e-beam writing parameters have been varied to find the right doses.

Randomly grown nanowires
As a proof of concept for growing in-situ Nb/InAs nanowire Josephson junctions, the InAs nanowires were also grown randomly on Si(111) facets. The processing is less elaborated, since it does not require the preparation of holes in the oxide covering Si(111) facets. Instead of thermal oxidation, after processing the troughs, the Si substrate is oxidized using a H 2 O 2 solution for 120 sec. The obtained oxide contains pin holes necessary for the nucleation of the nanowires. Since this is an uncontrolled growth process, the nanowire Josephson junction can be obtained if two InAs nanowires grow in the right geometrical configuration to realize the Nb shadow deposition on one of the nanowire (cf. Figure S4).

TRANSMISSION ELECTRON MICROSCOPY
As seen in Figure S5 (d) and similar to the previous observation related to Al half-shells [S3], a single Nb grain (which is larger than ∼15 nm) can grow beyond the length of a typical polytypic region, assuming that the amorphisation takes place later through solid diffusion (also note that the crystal phases of InAs is not visible in its < 1100 > zone axis, which was used to image the Nb layer more clearly. Hence, a comparison with the image in Figure S5 (a), which is imaged in the < 1120 > zone axis and typical of defect density has to be made, in order to gauge polytypic segment lengths). This extended growth of Nb beyond the polytypic segment size could be due to the nucleation-and-expansion type growth process of metal grains or Nb growth being driven by factors other than those related to surface and interface [S4]. However, the possibility of the rough micro-facets formed by ZB inclusions leading to more nucleations (and hence smaller grain size) cannot be discounted [S5].

DIFFERENTIAL RESISTANCE AND SUBGAP FEATURES
In Figure S6 the differential resistance is shown as function of the voltage across the junction for a gate voltage of V g = 7 V. For voltages below 0.3 mV, multiple sub-gap features are visible which can be attributed to multiple Andreev reflections. Additionally, a double peak feature is observable around 0.7 mV. The latter could be either a signature of multiple Andreev reflections, too, or the superconducting gaps of the Nb shell, the NbTi contacts or 6 some kind of hybridized electronic mixture of both materials. Owing to the low junction resistance in the normal state, we did not bias with currents resulting in a voltage drop corresponding to twice the gap of Nb because the large current would burn the device.
Thus, we did not reach a range in the differential resistance which would allow us to extract the gap energy of Nb. Figure S6. Voltage-dependent differential resistance trace for a gate voltage of V g = 7 V.