Perceiving the temperature coe ﬃ cients of carbon-based perovskite solar cells †

Perovskite solar cells (PSCs) have emerged in a “ cat ﬁ sh e ﬀ ect ” of other established photovoltaic technologies with the rapid development of high-power conversion e ﬃ ciency (PCE) and low-cost fabrication. Among various kinds of PSCs, organic hole transport layer (HTL)-free carbon - based PSCs (c - PSCs) have been considered as the most promising devices due to their excellent stability. However, temperature becomes one of the crucial factors in determining the pace of PSC commercialization. Temperature stress at the interface between the perovskite ﬁ lm and the charge transport layer is an essential factor in determining the performance of c-PSCs. This work assesses the correlation between the temperature coe ﬃ cient ( T C ) and di ﬀ erent photovoltaic parameters for HTL-free c-PSCs. To evaluate di ﬀ erent photovoltaic parameters of the c-PSC as a function of temperature, two di ﬀ erent testing approaches namely under steady temperature ( S T ) and transient temperature ( T T ) conditions have been considered across a wide temperature window (5 – 75 (cid:1) C) under 1 Sun 1.5 AM. Here T T testing involves subjecting a single c-PSC to a continuous temperature treatment, whereas S T testing consists of speci ﬁ c temperature treatment of an individual c-PSC. The maximum e ﬃ ciency achieved at 25 (cid:1) C for T T testing devices is (cid:3) 14.5%, which is (cid:3) 11% higher than that of S T testing devices (PCE (cid:3) 13%). Moreover, the e ﬃ ciency temperature coe ﬃ cient (ETC) for S T testing was found to be 3.5 (cid:4) 10 (cid:5) 2 (5 (cid:1) C # T # 25 (cid:1) C) and (cid:5) 2.1 (cid:4) 10 (cid:5) 2 (25 (cid:1) C # T # 75 (cid:1) C), whereas the ETC values of T T testing devices were +2.5 (cid:4) 10 (cid:5) 2 (5 (cid:1) C # T # 25 (cid:1) C) and (cid:5) 1.8 (cid:4) 10 (cid:5) 2 (25 (cid:1) C # T # 75 (cid:1) C), respectively. The outcome of temperature stress transmitting through di ﬀ erent interfacial layers was further investigated by thermal imaging of T T devices. On the other hand, X-ray di ﬀ raction and scanning electron microscopy structural analyses were performed to understand the e ﬀ ect of thermal stress on the overall performance of S T devices. It has been observed that T C values obtained under T T testing conditions are reversible, whereas in the case of S T testing the T C values are irreversible which shows degradation of the device.


Introduction
Perovskite solar cells (PSCs) with their cutting-edge technology have been universally elevated as an economically and environmentally feasible renewable technology option in place of regular and traditional solar cell technologies for addressing the global challenges in the area of energy generation and climate change. 1,2 From initial development to use of carbon as a counter electrode, extensive studies have been done in this eld, and to date, the highest photo-conversion efficiency (PCE) achieved for PSCs has been 25.2%. [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19] Engineering of interfaces and grain boundary of the perovskite layer can further help to enrich the PSC eld towards more stable, reliable and enhanced PCE generating devices. Despite this massive development, there are issues related to upscaling, toxicity, and stability of performance that restrict the commercialization of PSCs. 2,20 Due to the cost-effectiveness, environmental superiority, abundance, and excellent photo-electrochemical catalytic activity, carbon plays critical roles in the charge transport layer, as well as the counter electrode utilizing different polymorphs like carbon nanotubes, fullerene, graphite, and graphene. [21][22][23] Carbon polymorphs as charge transport materials produced the highest PCE of 21.1% whereas as electrode materials for holeselective layer-free devices, they were able to provide the highest PCE of 16.26%. 24,25 With the potential of achieving even higher efficiencies and very low production costs, c-PSCs have become commercially attractive.
However, temperature is one of the most crucial external factors that inuence the photovoltaic performance and stability of PSCs. Temperature strongly inuences physical parameters, like charge diffusion in the layers and/or recombination reactions of the generated electrons in the device. 26 To date, studies on temperature-dependent c-PSCs are a limited and less-explored area of research compared with numerous studies on improving the PCE and stability of c-PSC devices. There are few studies on temperature-dependent PSCs, which suggest a maximum PCE around room temperature with successive performance curtailment under higher or lower temperature conditions. [27][28][29][30] Most of the studies reveal the accumulation of ions at selective interfacial contacts during temperature stress. This further signies evaporation of additives in the hole transport layer (HTL) as the reason behind such performance decline of a PSC device. 31,32 In this regard, our study aims to investigate and understand the role of temperature coefficients (T C ) of c-PSCs using photovoltaic parameters such as short circuit current (J SC ), open-circuit voltage (V OC ), ll factor (FF) and power conversion efficiency (PCE) in visualizing the commercialization of solar cells. 33,34 Therelativechangeof a temperature-dependent parameter corresponding to the change of temperature is known as the temperature coefficient of that parameter. 35 T h ep h y s i c so ft e m p e r a t u r ec o e fficients (T C )ofsolarcellssuggestsastrongdependencyofV OC and J SC on temperature, as the balance between charge carrier generation and recombination can be affected by temperature. 34 Also, the temperature dependency of bandgap shi plays a vital role along with the incident spectrum in affecting the cell parameters. 36 Extensive research on performance variation with temperature to pin-point the temperature coefficient and deducing the origin of interfacial damage needs to be done for c-PSCs. It has been observed that for the three most widely commercialized thin-lm solar cells namely a-Si, CdTe and copper indium gallium selenide, the T C values are negative. 37,38 Although, they are highly effective in large scale operation. A negative T C value normally implies that with the increase of temperature, the parameter of interest will decrease, which can affect the performance of solar cells in a hot climate. Again a positive T C value indicates that the increase of temperature will increase the performance, which can impact the performance of the device in a cold climate. 39 In contrast, reports on T C value evaluation are less explored for PSCs. The commercialization of PSCs highly depends on the T C values of the devices because PV cells in the ground are operated at lower or higher temperatures relative to standard test conditions (STC, the temperature is taken as 25 C), depending on the environment, leading to changes in the average PCE, as reported for silicon solar cells. 33,34,[40][41][42][43] Under different climatic conditions, the yearly average temperature varies signicantly from the STC. 44 On the earth's surface, e v e r yl o c a t i o nu s u a l l yu n d e r g o e sad a i l y( i n2 4h o u r s ) temperature variation of $5to10 C or sometimes more than that. 45,46 In areas where the variation is $5 Co rl e s si n2 4 hours, it is possible that the performance of the devices can be different from places where the variation is 10 C or more due to inherent properties of materials like specic heat capacities. 47,48 Ac h a n g eo f1 0 Cc a ns i g n i cantly vary the performance of PSC devices, and detection of T C values is inevitable in this scenario. This kind of temperature variation can disrupt the instantaneous thermal equilibrium between different materials depending on specic heat capacity and thermal conductivity. 49 Therefore, in this work, steady temperature (S T ) and transient temperature (T T ) temperature conditions are introduced to understand their effect on the interface between the CH 3 -NH 3 PbI 3 perovskite lm and the charge transport layer and on the performances of c-PSCs in the temperature range of 5 Cto 75 C. Here S T and T T terms are designated depending on conditions of experimentation. Characterization of a particular device at different temperatures starting from 5 Ct o7 5 Ci s termed as T T testing, which could be more realistic for everyday temperature variation of $10 C on the earth's surface. On the other hand, keeping different devices at different temperatures (i.e. a particular device was kept at a particular temperature) in the 5 Ct o7 5 C range for examination is called S T testing, which could be more realistic for everyday temperature variation #5 C for a long time. Observations indicate a clear spectrum of T C values of different photovoltaic parameters for the rst time, along with the probable reasons behind signicant performance variations. This nding will be relevant for industrial applications in both single-junction and tandem architectures for c-PSC devices in future.

Results and discussion
Crystal growth via the solvent exchange method to develop c-PSCs Crystal growth via the solvent exchange (CGSE) method turns out to be an effective one-step approach for the fabrication of organic hole-conductor-free carbon-based perovskite solar cells with superior device performance. 50 At the same time, the roomtemperature solution processing fabrication method allows us to develop crystalline, scalable and rapid perovskite thin lms with no further heat-treatment. Unencapsulated c-PSCs investigated here had the conventional n-i-p structure of FTO/ compact TiO 2 /mesoporous TiO 2 /mesoporous Al 2 O 3 /WO 3 incorporated carbon. The MAPbI 3 precursor solution was drop-cast and spin-coated from the top of the counter electrode. Crystal growth via solvent exchange (CGSE) was then applied for roomtemperature deposition of the perovskite thin lm, as shown in Fig. 1. The details of the device fabrication process have been described in the Experimental section.
Testing approaches to determine the temperature coefficient In order to determine the T C values, the devices fabricated were tested under two different conditions namely S T and T T . S T testing devices were placed at a particular temperature for 2 days before any further characterization. For example, at low temperature like 5 C, it was kept in a chamber where the surrounding temperature was 5 C and similarly at other temperatures without interference from factors like moisture and air. In contrast, for the T T testing, a single device was placed at each particular temperature using a covered vacuum temperature controller to maintain surrounding temperature (system under vacuum to avoid air and condensation) for $1 hour ($30 min to reach the required temperature and then kept at that temperature for $30 min) for performance evaluation. A schematic of the testing details has been given in Fig. 2.
Thermal, X-ray diffraction and microstructural analyses of c-PSCs The S T devices were further investigated using scanning electron microscopy (SEM) and powder X-ray diffraction (XRD). In contrast, thermal imaging was introduced to characterize the devices under T T testing conditions. The SEM and XRD pattern of the fabricated c-PSCs under four different S T testing conditions of 5 C, 25 C, 45 C and 65 C, respectively, are shown in Fig. 3, where signicant changes have been observed for different interfacial layers associated with the PSC device. S T devices were maintained at a particular temperature for two days before executing the respective characterization. For thermal images, as shown in Fig. 3, the T T testing devices were prepared as follows. At rst the c-TiO 2 layer was deposited over the entire uorine-doped tin oxide (FTO) coated glass surface, and aer sintering and cooling, this layer was taped from every  side to reduce the surface aperture area of the next layer. In this way, successively the surface aperture area of every layer was reduced from its preceding ones to monitor the thermal imaging of the individual layer. Aer that, the devices were kept at a particular temperature with a covered vacuum temperature controller to maintain a similar temperature surrounding the device. Starting from the ambient conditions, for each settemperature, 30 min was allowed to attain the set-temperature, and then it was kept for $30 min in order to capture the thermal images. This is how top surface thermal images of different layers separately can be obtained to record the temperature prole of the layers. Usually, the environmental temperature is variable (may be minor) throughout the day, which should affect the instantaneous thermal equilibrium of different materials due to their inherent properties. Similarly, the thermal images captured for the c-PSC can predominately correlate with outdoor circumstances where different layers could not be in instantaneous thermal equilibrium all the time. Fundamentally, different materials have different heat capacities which will have an effective inuence on the disruption of the thermal equilibrium of different layers of real-world PSC devices. Thermal images at a specic temperature exhibit the nature of interfacial layers under different temperature stress. At a lower temperature, the FTO layer maintains 5 C, whereas the compact-TiO 2 layer remains at around 5.7 C. On the other hand, m-TiO 2 and m-Al 2 O 3 layers maintain a temperature of 6.2 C and 7 C, respectively. The carbon layer connes the maximum amount of temperature, which is reected in the thermal images of around 8.5 C. It can be predicted that the temperature difference of m-TiO 2 , m-Al 2 O 3 and the carbon layer can promote ion migration in this low-temperature region relative to a system in equilibrium. 29 In this scenario, analysing the SEM image and XRD pattern of the devices kept at 5 C can clarify S T behaviour. XRD data suggest the formation of PbI 2 and some other intermediates at $5 C. The degradation from CH 3 NH 3 PbI 3 (MAPbI 3 ) to PbI 2 is most likely accompanied by a chemical reaction under thermal stress. 51 On the other hand, SEM points towards spill-over of PbI 2 through m-TiO 2 and m-Al 2 O 3 layers, as shown by the arrow in Fig. 3b. The spill-over is only possible due to in situ layer formation at the interfaces of the deposited layers, causing unrecognizable layer separation in the device architecture (Fig. 3b). In Fig. 3c, the XRD analysis also suggests the formation of PbI 2 , which triggers the spill-over, and it will affect the photovoltaic performances of devices to a great extent. At 25 C, the separated layers of the c-PSC are quite distinct, as shown in Fig. 3d-f. Prominent layer distinction was also observed in SEM, as shown by colours in Fig. 3e and also the XRD data suggest the formation of a stable perovskite having major peaks at 14. 10 , 23.47 , 28.42 , and 30.89 corresponding to the (110), (211), (220), and (310) planes of CH 3 NH 3 PbI 3 , respectively. Interestingly, at 25 C, the corresponding thermal image ( Fig. 3d) exhibits insignicant variation among the layers. It has also been suggested that the small amount of excess PbI 2 in perovskite inuences the morphology and increases the size as well as uniformity of perovskite crystals by the solvent engineering method. 52 On increasing the temperatures from 25 C, major variations of thermal proles on different layers were not signicantly observed at 45 C for T T devices. Analysing S T devices at 45 C, minimal defects in both the SEM and XRD have been depicted, as shown in Fig. 3h and i, respectively. At 45 C, the formation of low intense intermediate phases observed from the corresponding XRD study further indicates the conation of carbon and m-Al 2 O 3 layers as observed from the SEM image (Fig. 3h). Stepping up for much higher temperature from 45 Cto65 C, the pattern observed ( Fig. 3j-l) was similar to that of the low temperature one for S T devices. The thermal image of the T T testing device at 65 C indicates a relatively higher temperature of m-TiO 2 and m-Al 2 O 3 than the carbon layer, which claries faster ion migration within those layers as observed at the low temperature. 21 The thermal images were reversible as lowering of temperature made a similar trend for T T testing. The SEM image at 65 C signies the factor responsible for the emergence of an interstitial layer of S T devices, Fig. 3k. This in situ layer exfoliates through other layers leading to degradation of the device performance. This may be due to the formation of an in situ intermediate structure in the interstitial position affecting the temperature transfer process, which can be conrmed by further characterization. Regarding T T devices, it is interesting to note that for all the temperature variation cases, the carbon layer possesses a relatively perceptible temperature compared to other layers of the concerned device. The effect of heating from the bottom surface, i.e. from the glass/FTO surface is therefore interpreted as an essential factor as the device is not inuenced by any other external factors such as light and moisture. Fundamentally, thermal conductivity dictates the effective transfer of heat, and as the top layer, the carbon suffers from less instantaneous heating. Besides, the carbon electrode has graphite in a large amount, and previous reports show that graphite has a low thermal conductivity in a high-temperature region. 53 Also, the role of specic heat capacities of materials is highly signicant to maintain the temperature of the layers. From available data, it was found that the specic heat capacities of other layers are lower than that of the carbon layer (having carbon black and graphite mainly) which produces this kind of behaviour. [54][55][56] It can be one more potential reason behind this kind of thermal imaging response. Again, in a very low-temperature surrounding, the temperature dissipates very slowly from the carbon material, as shown in Fig. 3. The lower thermal conductivity of other layers along with specic heat capacity of the carbon electrode could be the reason behind this kind of signicant physico-chemical response at low temperature. Materials with higher specic heat capacity have to lose a higher amount of heat energy to change their temperature during the cooling effect, which can be the primary reason for the lowtemperature behaviour of the carbon electrode. 57 Further study of other intermediate temperature states of S T devices has been shown in Fig. 4. The SEM images of S T devices at 15 C, 35 C, 55 C and 75 C illustrate the effect of temperature on the microstructural behaviour of the devices. The combination of layers can be seen clearly at 55 C, and at the same time, a signicant amount of degradation can be observed at very high temperature. The spill-over of the degraded material was observed in the FTO coating at 75 C. The corresponding energy dispersive X-ray (EDX) elemental colour mapping images indicate the extent of the Pb and I formation followed by their proliferation across the different layers of the devices, as shown in Fig. 4.

Photovoltaic performance of c-PSCs under S T and T T conditions
In order to understand the correlation between material characterization data and the photovoltaic parameter aspect of c-PSC devices regarding their real-world performances, the photovoltaic parameters were carefully monitored for both the S T and T T devices in the temperature window of 5 Ct o7 5 C. For evaluating the performance of the as-prepared c-PSCs under ambient conditions, the current density vs. voltage (J-V) characteristic measurements were performed under 1 Sun AM 1.5 (100 mW cm À2 ) in the temperature range of 5 Ct o7 5 C with an increment of 10 C considered as S T condition. The recorded J-V characteristic parameters are further compared in Table 1. Interestingly, starting from 5 to 25 C there was a steady increase in the device PCE, followed by a maximum PCE achieved as 13.1% at 25 C. Aer that, a decline of PCE was noticed up to 40 C, and from 45 to 75 C, the PCE dropped down extensively. Poor performance at higher temperatures is expected due to the degradation of MAPbI 3 , but the initiation of degradation and its impression on the different layers are still uncovered and need to be addressed. 28,29 Fig. 5a and b describes the major J-V characteristics and power density plots at four signicant temperatures of the S T devices, respectively, whereas the overall J-V characteristic plot recorded for S T variations has been shown in Fig. S1a and b, ESI. † The variation of photovoltaic performances was measured for a set of ve devices at each temperature, as shown in Fig. S2, ESI. † In addition, the external quantum efficiency (EQE) curves of c-PSCs exhibited a broad peak over the range of 300-800 nm with a maximum value of $90% for the devices at 25 Ca t a wavelength of 450 nm showing high charge collection efficiency in devices as shown in Fig. 5c and S1c, ESI. † It has been observed that the EQE values are relatively lower at a lower or higher temperature compared to 25 C. Higher values of EQE signify higher charge carrier collection for the solar cell and a slow charge recombination process. 58 Further, the integrated J SC for samples at different temperatures was evaluated from the overlap integral of the IPCE spectra, and values are given in Table S1, ESI. † The average integrated J SC values of c-PSCs at different temperatures are almost similar to the J SC values obtained from the J-V analysis. Further, electrochemical impedance spectroscopy (EIS) studies encourage us to understand the transport properties at different interfaces of layers in the S T c-PSC device. The Nyquist plot with an equivalent circuit diagram of the considered c-PSCs was recorded in the dark at 0.8 V bias from 10 mHz to 1 MHz, as shown in Fig. 5d and S1d, ESI. † In the circuit diagram (inset of Fig. 5d), R S represents the series resistance, which includes the resistance of FTO and the carbon counter electrode. R rec is the charge transfer resistance at the perovskite/carbon interface. 59 In Fig. 5d, the large parabola in the high-frequency region implies higher transportation and exchange resistance from the perovskite to the carbon counter electrode, which will inuence the ll factor as reected from J-V characterization. Again, higher values of R S should diminish the efficiency, and depending on temperature variation R S values can be observed from Table S1, ESI. † Despite the S T observation, a c-PSC device can withstand a wide range of temperatures. In order to understand the instantaneous behaviour of the photovoltaic performance, a c-PSC device was further employed for T T testing. In this case, the performance of the c-PSC devices was also examined in the same way in the temperature range of 5 to 75 Cw i t ha ni n c r e m e n to f5 C. Similarly, the temperature was allowed to decrease from 75 to 5 Cand t h ed a t aw e r er e c o r d e da ta ni n t e r v a lo fe v e r y5 C. The overall tuning of the temperature window was repeated twice on the same c-PSC device. The obtained reversible nature of parameters of the champion device is given in the ESI (Fig. S5 †). It has been observed that the PCE was reduced by $10% during the transition from high to low temperature. However, the PCE regained almost its initial value when the device was heated back from low temperature. This particular behaviour signies a negligible effect on the T C . The maximum PCE of 14.4% was observed at 25 C( F i g .6 a ) , and then a consistent decrease in PCE was reected during stepping up or stepping down to higher and lower temperatures, r e s p e c t i v e l y .F i g .6 aa n dbd e s c r i b et h em a j o rJ-V characteristics and power density plots at four signicant temperatures of the T T devices, respectively. The performance of all other temperatures is given in Fig. S3a and b, ESI. † The continuous temperature change may have triggered some internal modications in the devices, which can be responsible for this phenomenon. The variation of performances was measured for a set of ve devices at each temperature, as shown in Fig. S4, ESI. † EQE data of T T c-PSCs exhibited a broad peak over the range of 300-800 nm with amaximumvalueof$90% for the device at 25 Catawavelength of 450 nm indicating a higher rate of charge collection efficiency in devices as shown in Fig. 6c and S3c, ESI. † From the overlap integral of the IPCE spectra, integrated J SC values were evaluated, and values are mentioned in Table S2, ESI. † Besides, the corresponding EIS measurements of T T d e v i c e sa r es h o w ni nF i g .6 da n dS 3 d , ESI, † which reect a similar nature of data obtained from J-V characterization. The R S and R rec values, as recorded from EIS analysis, are mentioned in Table S2, ESI. † The photovoltaic performances under both S T and T T conditions show the inuence of interface passivation on the operating temperature of PSCs. The energy barrier, the defects or charge or ion accumulation at perovskite-transport material interfaces, ions in perovskite or charge transport layers, and charge mobility in charge transport layers determine not only the charge collection efficiency but also have a signicant impact on the hysteresis. 60 Though the interfacial layers avoid the direct contact of the perovskite lm with metal electrodes, the inherent mobile iodide ions in the perovskite lm can easily diffuse across the interfacial materials to react with the electrode due to the minimal activation energy for their migration.

Evaluation of T C from the S T and T T testing devices
The temperature coefficients quite delineate the behaviour of the c-PSC's photovoltaic parameter function of the temperature. Determination of the temperature coefficient (T C ) of these two types of testing for c-PSC devices applying the generalized linear relation becomes very much essential for a better understanding of the temperature-performance correlation in realworld condition as mentioned in the following equations (eqn (i)-(iv)) 34,41 where J TC is the temperature coefficient of current density, DJ is the difference of short-circuit current density at a particular temperature with respect to the reference temperature (reference temperature is 25   temperature with respect to the reference temperature, P ref is the power density at the reference temperature, and DT is the temperature difference between device temperature and reference temperature. Using eqn (i)-(iv) quite a remarkable trend was obtained in the T C values for S T and T T processes. The variation of obtained T C values at specic temperature isshowninFig.7and8,forS T and T T methods, respectively. A clear distinction of the average T C values is acquired for S T and T T processes, as shown in Table 3. The average T C values of current density for S T and T T conditions have signicant discrimination from each other. In the case of the T T process, the current density increases from 5 to 35 C, but for S T testing, theincreaseoccursupto25 C. T C values of other parameters for two different scenarios seem to be close. However, these variations lead to signicant differences in the PCE and other parameters of devices under two different testing conditions, as shown in Tables 1 and 2. Also, the conditions are entirely different in these two testing states, which makes T C values more signicant. Moreover, the T C values resulting from T T testing conditions are reversible, whereas S T testing devices do not show such behaviour, hence resulting in faster degradation.
Besides, the temperature-dependent T C exhibits interesting features under various photovoltaic parameters, and  temperatures as shown by three-dimensional (3D) representation plots in Fig. 9 and 10. The gures dictate a similarity in T C as reported for other traditional solar cells only in the hightemperature region (negative T C ) but not at temperatures below STC (positive T C for the c-PSC), which can make them a more front runner for commercialization. 22 The difference in T C plots of S T and T T testing is fascinating as well for real-world performance analysis. During the T T testing (Fig. 8), the stabilized T C values show that the T T c-PCSs are more suitable in those parts of the world where temperature variation throughout the day is very high. On the other hand, S T temperature conditions can notably be considered in those parts where the variation of weather in a day is very low throughout a particular season. Moreover, the lower T C value for a c-PSC makes it a suitable candidate for a multi-junction solar cell.

An overall analysis of c-PSCs under S T testing conditions
It is now highly relevant to realize the variation of T C values or rather the performances with in-depth analysis, for which further investigation was performed to recognize the probable origin concerning the associated layers of the device. The MAPbI 3 actually controls the device performance, and further its stability. 61 Thus, it is crucial to investigate the role of MAPbI 3 across the different layers of the c-PSC under thermal stress. In order to understand such effects, three different sets of lms were prepared on an FTO glass namely (a) spin-coated m-TiO 2 and MAPbI 3 , (b) spin coated m-Al 2 O 3 and MAPbI 3 , and (c) screen printed carbon and spin coated MAPbI 3 under S T conditions.
The XRD patterns at 5 C and 65 C for Al 2 O 3 based lms exhibit quite distinct characteristics, as shown in Fig. S6, ESI. † It has been observed that at the low temperature the appearance Table 3 Average values of temperature coefficients for S T and T T testing devices in different temperature ranges (NA: not applicable) Average temperature coefficient of power density max (Â10 À2 )  of unwanted PbI 2 is less pronounced compared to the higher temperature. Besides, PbI 2 tends to cover the Al 2 O 3 layer to some extent, which eases the exfoliation of PbI 2 formed in the interstitial position. On the other hand, for the m-TiO 2 coated samples, it was found that the extent of PbI 2 formation at both high and low temperatures is quite truncated, as shown in   Again, for the carbonbased layer, a substantial amount of information was obtained to understand the low efficiencies at temperatures 5 C and 75 C for the S T devices. The XRD pattern suggests the formation of an intermediate state by the interaction of carbon and perovskite or a degraded perovskite due to thermal treatment, as shown in Fig. 11. This further leads to more extensive degradation of MAPbI 3 . The appearance of the PbI 2 phase facilitates increased exfoliation through the layer of the c-PSC. The combination of a newly formed unrecognizable intermediate and formation of PbI 2 severely damages the performances of devices at very high and low-temperature regions. The SEM images also defended the formation of an intermediate phase with carbon, as shown in Fig. S8, ESI. † At 25 C, the SEM image (Fig. S8c, ESI †) shows a prominent surface structure, but dissimilarity can also be observed with temperature variation. On the other hand, the SEM analysis indicates that a rapid change occurred at 15 C and 45 C for the S T devices. The results suggest the initialization of intermediate formation, which points towards a rapid decrease in efficiency at those temperatures. On, the other hand, extrinsic accumulation of I À plays a great role in exfoliation through Al 2 O 3 and TiO 2 layers. The extent of degradation is greater when MAPbI 3 interacts with Al 2 O 3 rather than TiO 2 . This elucidates the predominant spill-over of perovskite through the Al 2 O 3 layer in the S T testing devices. The interaction of the carbon layer and perovskite greatly inuences the device performance via the formation of intermediates, and as a whole, the interface of carbon and Al 2 O 3 is expected to initiate perovskite deformation. At temperatures above 45 C and below 15 C for S T testing, "pinhole structures" are created, which clearly veries inter-molecular interaction leading to intermediate formation for devices as shown in SEM (Fig. S8, ESI †). 32 The XRD pattern, as shown in Fig. 11, further conrms the formation of such intermediate structures between carbon and MAPbI 3 upon exposure to different temperatures for more than a day. The heat produced by high temperature also initiates the chemical decomposition of the MAPbI 3 lm. In this case, the interfacial layers have the direct contact of the MAPbI 3 lm with the electrode, and the inherent mobile halide ions in the perovskite lm can easily diffuse across the interfacial materials to react with the electrode due to the minimal activation energy for their migration. The heat generated at high temperature was also reported to cause migration of metal atoms into PSCs, leading to the degradation of the devices. 61 At the same time, corrosion occurring from the active carbon and Al 2 O 3 layer by either the iodide in the perovskite lm or the decomposed byproduct such as volatile I 2 and HI has also become a signicant concern for high-temperature stress for the operation of the PSC. Temperature stress can produce thermal exfoliation of the layers as observed from different temperature-based SEM analyses, as obtained from Fig. 3. Exfoliation decreases the reachable aperture area of the layers concerned, which accordingly retards the performance of devices. However, the degradation of the device performance of PSCs has also been observed at a lower temperature for S T testing. It is observed that at low temperatures the orientation of the methylammonium cation in MAPbI 3 is xed because of hydrogen bonding between the NH 3 groups and the framework iodide atoms. This acts as the driving force for the observed deformation of the PbI 3 À framework and further adopting a staggered formation. As the temperature is increased the thermal motion of the cation increases and the NH-I interactions weaken. 61 It seems that, in general, the growth of metal oxide might give rise to the lowering of interface quality. This might be related to the presence of surface defects in metal oxides, which lead to high interface recombination. 62 Also, there will be a slight inuence of surrounding moisture and air, although the devices were kept inside a chamber of xed temperature. It was suggested that excess PbI 2 in MAPbI 3 could help to passivate defects at surfaces and grain boundaries and a small amount of residual PbI 2 in perovskite helps to reduce charge recombination and improves the V OC and FF. 59 As a result, the devices do not lose their V OC under thermal stress, indicating the PCE loss is mainly restricted to the J SC . This kind of materialistic interface dependent performance variation with respect to temperature is highly demanded for real-world application of c-PSCs. The discussions mentioned above have been further schematically described in Fig. 12.
An overall analysis of c-PSCs under T T testing conditions T T testing signies the unique effects of temperature variations on a particular device. The presence of a temperature gradient between the layers signicantly inuenced the performance. The perovskite can become chemically unstable at temperatures well below its decomposition conditions due to the temperature gradient. 21 Migration of mobile ions by the inuence of temperature stress (majorly iodide ion) is responsible for PSCs' unique and prominent properties, although the large-scale trapping of electrons cannot be ruled out. [63][64][65] Most of the studies suggest that, with temperature, the mobility of transient ions increases, which leads to the accumulation of ions at interfacial contacts of the perovskite and other layers. As the work function of the HTL and ETL differsfromeachother,thisdifference creates a built-in eld, which drives the migratory ions. Temperature variation can reduce the built-in eld, which eventually can increase the extent of ion migration. Thus, the excess mobility of ions leads to accumulation of ions at interfaces. Accumulation of ions reduces current generation due to the increase in the recombination process at interfaces by increasing bandgap defects or electrostatic traps. [66][67][68][69] Data obtained from EIS (Fig. 6) conrm high charge recombination resistance pointing towards the hike in the recombination process for the T T study. The role of crystal lattice disruption of perovskite (tetragonal to cubic) at a temperature higher than 50 C cannot be neglected, which signicantly reduces the performance of T T devices. 70 On the other hand, the thermal expansion coefficients of different materials used can signicantly disrupt the interconnectivity of layers, increasing the interfacial defects. 70 The variation of performance at low temperature may be the result of this expansion factor. Also, the effect of low charge diffusion cannot be neglected at low temperature, which can reduce performance. 71 A correlation between S T and T T observations can be drawn from this experiment. It is explained earlier that intrinsic ion migration and accumulation may be the reason behind the performance loss of T T devices. Because of thermal stress on the T T devices, defect states may occur followed by creation of interstitial vacancies. 64 Iodide ions could dri across the interface, and enter the vacant positions. The intermediate formation in S T devices could have originated from the intrinsic behaviour of T T devices. However, the exact nature of the intermediate phase needs clarity leading to research that is more intensive. To the best of our knowledge, we are the rsttoreporttheT C aspect of carbon-based PSCs. It is anticipated that temperature can signicantly inuence the photovoltaic parameters of the device. The way of temperature treatment is further indicative of the c-PSCs' photovoltaic behaviour, which has been depicted in terms of T C for the real-world condition. In this study, we propose that the average T C values should closely agree with the observed trend of this study for any c-PSC or rather any PSC. The challenge is the development of advanced high-temperature resistant PSCs, and modules based on novel architectures and/or processes, which can tackle efficiency limitations while improving cost-effectiveness.

Conclusions
In conclusion, we have investigated the temperature coefficient (T C ) of carbon-based perovskite solar cells (c-PSCs) in two determining ways namely under steady temperature (S T ) and transient temperature (T T ) conditions across a broad temperature window from 5 to 75 C. These explorations provide new insights into a PSC by means of T C analysis based on corresponding different photovoltaic parameters. Highly noticeable performance in short circuit current, open-circuit voltage, ll factor, and power conversion efficiency of the devices as a function of temperature was observed, leading to distinct T C values separately for the S T and T T cases. Instantaneous behaviour is pronounced in the case of T T devices leading to rapid changes due to ion migration and accumulation at interfaces across the c-PSC device. We have observed that the T C value becomes higher for S T testing devices compared to T T , which is further explained by various interfacial layer physicochemical studies. The T C values derived from T T testing conditions are reversible, whereas the irreversible T C value of S T testing shows degradation of the devices. Effect of temperature on the different interfacial layers of the c-PSC and their correlation with the photovoltaic performances have been further established. The XRD and SEM microstructural analyses further suggested that the extent of perovskite degradation was greater at the Al 2 O 3 -perovskite interface due to the thermal stress. The observed dual characteristics of T C for a c-PSC in a low and hightemperature region attract future research interest for its largescale real-world condition testing. Future studies will be further required to investigate whether other architectures of PSCs or other organo-metal halide perovskites are more robust to the T C parameter variation. The temperature-dependent surface features of the perovskite also highlight the role of the interfacial interaction associated with the different layers in the photovoltaic performance of the solar cells. We assume that further research about the origin of thermal stress on various interfacial layers might help in reducing the photocurrent loss, thereby increasing the likelihood of successful outdoor application of PSCs.

CH 3 NH 3 PbI 3 synthesis and c-PSC device fabrication
Fabrication of c-PSCs was adopted from our earlier reported article with slight modication using the 'crystal growth via solvent exchange' (CGSE) method for better performance. 65 In short, sequential deposition of compact TiO 2 (c-TiO 2 ), mesoporous TiO 2 (m-TiO 2 ), mesoporous Al 2 O 3 , and WO 3 incorporated carbon was performed on a uorine-doped tin oxide (FTO) glass substrate. The perovskite precursor (MAPbI 3 ) solution was drop-cast, followed by spin coating, and then the CGSE method was deduced from previous literature. 50 CGSE stands out as an effective one-step approach for the fabrication of organic holeconductor free carbon-based perovskite solar cells with superior device performance. At the same time, the roomtemperature solution processing fabrication method allows us to develop crystalline, scalable, and rapid perovskite thin lms with no further heat-treatment. In the CGSE process, coated FTO glasses were immersed in a diethyl ether (DEE) bath for 1 hour at room temperature instead of thermal annealing. During the CGSE process, the NMP soluble MAPbI 3 precursor is exposed to DEE, and the NMP solvent is extracted selectively because NMP is highly miscible in DEE. This triggers the crystallization of MAPbI 3 perovskite in areas devoid of NMP, which spreads rapidly to cover the entire area as NMP is completely extracted by DEE. A schematic diagram has been mentioned, which illustrated the CGSE process as shown in Fig. 1. The as prepared devices were kept under dry and dark conditions for three days to obtain a uniform growth of perovskite crystals. Finally, the c-PSCs were subjected to further characterization and measurements. The prepared c-PSC devices were divided into two groups before further characterization under S T and T T conditions (Fig. 2). S T resembles separate devices kept at different temperatures and T T indicates that a particular device has been tested under variable temperature conditions. S T devices were again classied into sub-groups depending on temperature rather in the case of T T devices, where there were no sub-groups.

Material characterization
The infra-red (IR) camera shots (thermal images) were taken with aF L I RT 4

Data availability statements
The data that support the plots within this paper, and other ndings of this study are available from the corresponding author upon reasonable request.

Conflicts of interest
The authors declare no conicts of interest.