Double cascade dressed MOSFET from doped Eu3+and Pr3+ in a host YPO4

In this paper, we study double cascade dressed optical metal oxide semiconductor field-effect transistor (MOSFET) by exploiting enhancement and suppression for mixed-phase (hexagonal + tetragonal) of Eu3+:YPO4 and different phases (hexagonal + tetragonal and pure tetragonal) of Pr3+:YPO4 crystals. We report variation of fine structure energy levels in different doped ions (Eu3+ and Pr3+) in the host YPO crystal. We compared multi-level energy transition from a single dressing laser with single level energy transition from double cascade dressing lasers. Gate delay facilitates multi-energy level dressed transition and is modeled through a Hamiltonian. Based on the results of double cascade dressing, we have realized MOSFET for logic gates (inverter and logic not and gate) with a switching contrast of about 92% using a mixed phase of Pr3+:YPO4.


Introduction
In the last few decades, scientists have shown increased interest in widening the knowledge of rare earth ions doped in crystals due to the potential applications in optical devices [1][2][3][4][5] and quantum computing. 6 Since Eu 3+ and Pr 3+ ions are more sensitive to the site symmetry and its surrounding crystal-eld of the host material than other crystal ions, 7,8 it can be achievable to get such kinds of potential application in YPO 4 crystals. The crystal structure of YPO 4 has two polymorphic forms, tetragonal (T-) and hexahedral (H-) phases. [9][10][11][12] The slight variation of local structure will bring signicant changes in the optical properties.
In theory, the tetragonal (T) phase of crystal is more structurally symmetric than the hexahedral (H) phase in Eu 3+ and Pr 3+ ions because of a more atomic-like system. 13 In our experiment, a mixed contribution of T phase (more) + H phase (less) of crystal at low power performed better because of good transmission of information for the crystal T phase. The atomic density has a great inuence on the number of splitting, which is relative to the dressing effect in atomic-like media. 14,15 The observation of Autler-Townes (AT) splitting effect of FL spectrum induced by self or external elds and the polarization dependence of FL signals in Pr 3+ :Y 2 SiO 5 has been reported. 16 Wen et al., realized optical switch and amplier from dressing suppression and enhancement inmulti-order uorescence (FL) and spontaneous parametric four-wave mixing (SP-FWM) in Pr 3+ :Y 2 SiO 5 . 17 Controlled correlation and squeezing in Pr 3+ :Y 2 -SiO 5 to yield correlated light beams has also been investigated. 18 Transition between the bright and dark states can modify the non-linear behaviour of crystal on singly-and doubly-dressed four-wave-mixing (FWM) processes. 19 Diamond nitrogenvacancy (NV) center were studied to realize optical transistors and hybrid switch. 20,21 Eu 3+ :YPO 4 and Pr 3+ :YPO 4 crystals have been congured to observe second-order FL signals.
In this paper, we study the energy level transition of europium doped YPO (Eu 3+ :YPO 4 ) and praseodymium doped YPO (Pr 3+ :YPO 4 ) crystals with different phases using dressing lasers. By changing different parameters of single and double laser (power, detuning, and gate delay), we observed the dressed energy level transition from single to multi-level with a single laser; and single-level using double laser. Each sample responded based on their ions structure and phase symmetry in the host YPO crystal. In contrast to single multi-level dressing, double cascade dressed single level energy transition outputs are robust and are observed to be of special interest because of half peak with half suppression dip. These kinds of results are very important for realizing metal oxide semiconductor eldeffect transistor (MOSFET).

Basic theory
In this experiment, both samples were held separately during the experiment running in a cryostat (CFM-102) with a temperature of 77 K. Fig. 1(a) shows a ne structure and a hyperne structure of host material YPO 4 . The Eu 3+ :YPO 4 has two states, named ground state 7 F 1 and excited state 5 D 0 . Under the action of the crystal eld of YPO 4 , the ground state 7 F 1 is split, which is ne-structure levels. Fig. 1(b) shows the simplied energy-level diagram of Eu 3+ doped YPO 4 (Eu 3+ :YPO 4 ) and Pr 3+ doped YPO 4 (Pr 3+ :YPO 4 ) crystal. Fig. 1(c) shows the schematic diagram of the experimental setup. Two dye lasers (narrow scan with a 0.04 cm À1 line width) are pumped by an injection-locked single-mode Nd:YAG laser (Continuum Powerlite DLS 9010, 10 Hz repetition rate, 5 ns pulse width), which are used to generate the pumping elds E 1 (u 1 , D 1 ) and E 2 (u 2 , D 2 ) with frequency detuning of D i ¼ U mn À u i , where U mn is the corresponding atomic transition frequency between levels |mii and |ni. u i (i ¼ 1, 2) is the laser frequency. Arrangements of two photomultiplier tubes (PMT1-2) are used to detect the generated Stokes (E S ), anti-Stokes (E AS ) , and FL composite signals ( Fig. 1(c)). The pumping eld E i (where i ¼ 1, 2) excites the sample and is reected eld E 0 i from the surface of Eu 3+ :YPO 4 into its original with a small angle q between them. The spectral signals are obtained by scanning laser frequency, while timedomain signals are obtained by xing laser frequency. Fig. 1(d) and (e) show dressed energy level, through which SP-FWM process congured in the lambda level system. Fig. 1(e) SP-FWM in a two-level system.
In Fig. 1 where d 1 ¼ G 10 + iD 1 , G i ¼ Àm ij E i /ħ is the Rabi frequency, G ij is the transverse decay rate and m ij is the electric dipole moment between levels |ii and |ji the lifetime of FL is given as G FL ¼ G 10 + G 11 . The temporal intensity of FL, given as I(t) ¼ r (2) 11 exp(ÀG FL t). In a two-level system (shown in Fig. 1 20ðASÞ , respectively, can be written as The lifetime of the Stokes/anti-Stokes signal can be written as G S/AS ¼ G 00 + 2G 20 . In L-type three-level system(shown in Fig. 4(c)), taking into account the self-dressing effect of E 1 and the external-dressing eld E 2 , the third-order nonlinear density matrix elements of E S and E AS are given by r 12 Þ, respectively. The dressed density matrix elements, in this case, are given as follows The lifetime of the Stokes/anti-Stokes signal can be written as G AS ¼ G 10 + 2G 20 . Similarly, fourth-order FL r (4) FL in L-type system via the pathway r Therefore, the intensity of the measured FL signal can be described as Owing to the interaction of the coupling eld, the homogeneous linewidth broadening of the measured for FL is given as Experimental results and discussion in gate delay is demonstrated in Fig. 2(c) and (d); corresponds to change in different energy levels of Fig. 2(a) and (b). The bright to dark states are shown in Fig. 2(e) for illustration purpose based on single laser and single-level dressing. In Fig. 2(a1 and  a3), the spectral signal recorded at PMT2 is composed of second-order FL (r (2) 11 ) and SP-FWM (r (3) 10(S/AS) ), thus making a compo E 0 1 site signal (r (2) 11 + r (3) S ) at PMT2. Composite signal is by produced E 1 and E 0 1 ðk s ¼ k 1 þ k 0 1 À k AS Þ along with FL at PMT2, and Fig. 2(b1) is similar to PMT1. In comparison with Fig. 2(a1), FL dominates in Fig. 2(b1) due to the focused detection. Physically, Hamiltonian is at |1i a frequency reference point (dark state) in Fig. 2(e). Using this equation of Hamiltonian H|G 1AE i ¼ l AE |G 1AE i, one can get the split energy When gate delay is changed from 200 ns to 2 ms, the dip appears in Fig. 2 (2). When the gate delay is at 2 ms and 10 ms, the dip also appears in Fig. 2(b2 and b3). This phenomenon can be explained by E 1 falling on dark states, which splits into two bright states (|G 1+ i and |G 1À i) and one dark state (|1i), likewise the case in Fig. 2(a2). Signal linewidth is decreased from gate delay 200 ns to 10 ms. in Fig. 2(a1 and a3) due to SP-FWM r (3) S in r (2) 11 + r (3) S . At the gate delay of 2 ms, the intensity of the spectral signal is decreased. So, only the intensity noise signal is obtained in Fig. 2(a4). The single dressing effect of E 1 is different at PMT1 or PMT2 by changing gate delay at medium power. Comparing recorded spectral intensities at PMT1 and PMT2, PMT1 has more FL due to detection through confocal lens, demonstrating broader line width and relatively obvious single laser dressing.
Here, an optical MOSFET based logic inverter or "not" gate has been realized through the results of Fig. 2(a) and (b). The model of the MOSFET logic inverter gate is shown in Fig. 2(f), where E 1 is input signal (analogous to the gate voltage and gate current of MOSFET) and Y is the output of the MOSFET. To realize the logic inverter or not gate function of the MOSFET, when the input of the MOSFET E 1 performs off-state, the output of the MOSFET Y performs on-state as a spectral peak in Fig. 2(a1) and (a3) (likewise Fig. 2(f1)). Here in Fig. 2(a1) and (a3), the output of the MOSFET Y satises the logical output condition 1. The spectral intensity of output spectral signal (offstates) in Fig. 2(a2) responses like MOSFET inverter as a suppression dip (Fig. 2(f2)). The MOSFET inverter as a suppression dip performs off state in Fig. 2(a2) (likewise Fig. 2(f2)), and it satises the output Y of the MOSFET inverter with logical 0 condition. The logic inverter or not gate contrast can be dened as C ¼ (I off À I on )/(I off + I on ), where I off is the light intensity at the off-state and I on is the light intensity at the onstate. The switching contrast C is about 75% from Fig. 2(a2)-(a3). Compared with Fig. 2(a2)-(a3), the logic inverter, or not gate contrast in Fig. 2(b1)-(b2) is similar, and the contrast is almost 78% from Fig. 2(b1)-(b2). The speed of the MOSFET inverter gate is 3 ms and 12 ns from Fig. 2(a1)-(a2) and from Fig. 2(b1)-(b2), respectively. Fig. 3(a1-a4) and (b1-b4) shows spectral intensities of output signals measured at PMT2, when E 1 is xed at low power (1 mW) and high power (8 mW), respectively. Signal linewidth is also decreased from gate delays of 200 ns to 20 ms in Fig. 3(a1,  a3) and (b1, b4) due to r (3) S . But signal linewidth in Fig. 3(b1-b4) at 8 mW is wider than that of in Fig. 3(a1-a4) at 1 mW due to multi-energy level dressed split at higher power by single dressing laser (Fig. 3(e)). However, at focused PMT1, the FL demonstrated the robust behaviour affected by dressing laser and gate delay dependency of multi-energy levels. It should be noted that the multi-level energy splitting is caused by E 1 only, whereas, higher gate delay act as assisting to dressing parameter, which opens up a window for multi-energy level dressing, causing splitting as the two phases are closely packed in mixedphase symmetry of Eu 3+ :YPO 4 . In principle, gate delay facilitates E 1 eld dressing, which excites (|1i and |2i) and splits them into four bright states and two dark states, as illustrated in Fig. 3(e). In comparison with Fig. 2(e), two dark states |1i and |2i in Fig. 3(e) are different from one dark state |1i. So one can say that |G 1AE i of |1i and |G 1AE i of |2iform four bright states from a single dressing E 1 when facilitated by gate delay. Physically, when the laser power of E 1 is high, dressing |G 1 | 2 /d 1 is increased suggested by eqn (1). By looking at Fig. 3(b3) at 20 ms, one can say laser dressing is assisted by gate delay to produce one small sharp peak, which comes by combining bright states (|G 1À i of |1i and |G 1+ i of |2i), and two dips (|1i and |2i) from Fig. 3(e). One dip is shown in Fig. 3(a2 and b2), this phenomenon can be explained likewise Fig. 2(a2, b2 and b3). The interpretation of this peak in Fig. 3(a1, a3, b1 and b4) is same as in Fig. 2(a1, a3  and b1). Therefore, when the gate delay is increased at low power, the single dressing appears in Fig. 3(a3). At high power, dressing assisted by gate delay shows in Fig. 3(b2 and b3).
The MOSFET logic inverter or not gate performs on state, and it satises the output Y of the MOSFET inverter's logic 1 condition in Fig. 3(a1) and (b1). The output of the MOSFET Y performs off-state when it satises the logical output 0 condition in Fig. 3(a2) and (b2). So, MOSFET logic inverter or not gate is realized from Fig. 3(a1)-(a2) and from Fig. 3(b1)-(b2), where the inverter contrast C is about 72% and 80%, respectively.
In Fig. 4(a1-a4), when gate delay is changed to 600 ms from 200 ms, the effect of double cascade dressing of E 1 and E 2 is getting obvious in Fig. 4(a2 and a4). The double dressing of E 1 and E 2 fall in dark states, which splits into three bright states (|G 1+ i, |G 2À+ i and |G 2ÀÀ i) demonstrating three visible peaks and two dark state (|1i, |G 1À i) corresponding to two dips in Fig. 4(a2 and a4), as suggested by Fig. 4(d). These dips and peaks are suggested by double cascade dressing |G 1 | 2 /(G 01 À iD 1 ) + |G 2 | 2 /(G 00 + iD 2 ) due to dressing suppression conditions D 1 ¼ 0, D 2 ¼ G 1 from eqn (6). Fig. 4(a1 and a3) shows that by increasing gate delay from 200 ns to 2 ms AT splitting area varies from plan to deep. As dressing E 1 plays a major role in Fig. 4(a1), while dressing E 1 plays more role than dressing E 2 in Fig. 4(a3). In Fig. 4(b1-b7), when E 1 (594.8 nm) is shined by changing power from 2 mW to 8 mW and scanning E 2 from 570-610 nm with 8 mW of power, similar trend of three visible peaks and two dips are gradually observed from Fig. 4(b6 and b7). AT splitting area varies from plan to deep by increasing power from 3 mW to 6 mW. The more obvious dressed energy level appears in Fig. 4(b2-b5) due to dressing E 2 of high power. Comparing these two phenomenon of obtaining SP-FWM from suppressed dip of FL using gate delay in Fig. 4(a1-a5) and changing powers in Fig. 4(b1-b7), one can nd the stronger double cascade dressing with more tetragonal and less hexagonal phase of Eu 3+ :YPO 4 at 20 ms due to symmetry in Fig. 4(b6 and b7). Dressing effect of E 1 and E 2 in terms of AT splitting is obvious by changing gate delay and power in Eu 3+ :YPO 4 . Therefore one can characterize such a phenomenon obtained in Fig. 2(a2, b2 and b3), Fig. 3(b3) and Fig. 4(a2, b6 and b7) as single dressing, multi-energy level  dressing by single laser assisted by gate delay and double cascade dressing in Eu 3+ :YPO 4 , respectively.
Here, we have realized the optical logic NAND gate. The model of optical logic NAND gate is shown in Fig. 4(e). When E 1 power is 2 mW, the intensity input spectral signal satises the logical condition (0,0) of the NAND gate, so the output spectral signal performs as on state (logical output 1) in Fig. 4(b1). When E 1 power is increasing gradually from 2 mW to 4 mW, output spectral signals perform as on state in Fig. 4(b2-b3) and here, the input condition of a logical NAND gate can be (0,1) and (1,0) for realization. When E 1 power is 6 mW, the intensity output spectral signal satises the logical input condition (1,1) of the NAND gate, and the output spectral signal performs as an off state (logical output 0) in Fig. 4(b5). Our experiment results are dened on state and off state by the NAND gate contrast, respectively inverter contrast. Here, C is 86% from Fig. 4(b1-b3) to (b5).
In Fig. 5(a1), the time-domain signal has little adiabatic population than Fig. 5(a2), because of double cascade dressing from E 1 and E 2 . At resonant excitation in Fig. 5(b1 and b2), one can say that the adiabatic population is maximum at a resonant point in Fig. 5(b1) and comparatively less in Fig. 5(b2) because of a single dressing of E 2 . By looking at Fig. 5(c1 and c2), less adiabatic expansion has found for resonant and off-resonant E 1 at 77 K. Signal linewidth is also decreased from the gate position 500 ns to 5 ms in Fig. 5(d1 and d3) or (e1 and e3) due to stokes of SP-FWM r (3) S . In the crystal eld of YPO 4 :Pr 3+ , the (2J + 1) degeneracy is partly split, and the J ¼ 0, 1, 2, 3, 4, 5, 6 levels split into 1, 2, 4, 5, 7, 8, 10 irreducible representations, respectively. Under this symmetry ( 1 D 2 and 3 H 4 ), two transition levels are allowed. 19 Fig. 5(e2) shows double cascade dressing at low power due to dressing suppression conditions D 1 ¼ 0, D 2 ¼ 0 from eqn (6). Double cascade dressing of E 1 and E 2 is more obvious than that of E 1 at low power or even by changing gate delay in Pr 3+ :YPO 4 . By comparing Pr 3+ and Eu 3+ , at low power, the double cascade dressing effect in Pr 3+ :YPO 4 (in Fig. 5(e2)) is stronger than Eu 3+ :YPO 4 (in Fig. 4(b2)).
Here in Fig. 5, optical logic NAND gate has been realized, respectively Fig. 4. In Fig. 5(e1), spectral signal performs output on state (logical output 1) from the input logical (0,0) condition of optical logic NAND gate, as shown in the model in Fig. 4(e). In Fig. 5(e2), spectral signal performs output off state (logical output 1), and it can satisfy the input logical (1,1) condition of optical logic NAND gate, as shown in the model in Fig. 4(e).
Here, contrast C is 88% (from Fig. 5(e1)-(e2)) as gate delay changed from 1 ms to 1.5 ms. Fig. 6(a1-a4) shows the gradual and bit weak trend of the FL signal. By comparing Fig. 5 and 6 at low power, one can say that dressing effects observed in the tetragonal phase and mixedphase (less tetragonal with more hexahedral) of Pr 3+ :YPO 4 are different, which can be explained from different site symmetry. Here, we have realized the optical logic NAND gate. When output spectral signals are obtained at gate delays 200 ns, 600 ns, and 1 ms at low power of E 1 and E 2 in Fig. 6(a1-a3), spectral signals are performed as output on state (output 1) of the optical logical NAND gate. For realizing the output logical NAND gate, input conditions can be (0,0), (0,1) and (1,0) respectively Fig. 6(a1-a3). When output spectral signal is at gate delay 1.5 ms at low power of E 1 and E 2 in Fig. 6(a4), NAND gate performs off state (output 0) and it can satisfy the input condition of logical (1,1) for the NAND gate. Our experiment result dened the NAND gate contrast as C is 92% as gate delay changed from 200 ns to 1.5 ms in Fig. 6(a1) and (a4).

Conclusions
In summary, we demonstrated and compared single dressing based multi-level energy dressing assisted by gate delay and  double cascade dressing based single energy-level transition in Eu 3+ :YPO 4 and Pr 3+ :YPO 4 crystals. We observed that at low power, a single dressing effect in Pr 3+ :YPO 4 was stronger than Eu 3+ :YPO 4 , while the double cascade dressing effect was stronger in Eu 3+ :YPO 4 . Based on the outputs, logic gates (inverter and logic not and (NAND) gate) were realized by gate delay and power of laser elds. Such a detailed comparison of Eu 3+ and Pr 3+ doped in YPO 4 can be of potential utility in nonlinear and quantum optics for quantum gates.

Conflicts of interest
There are no conicts to declare.