Optimized single-layer MoS2 field-effect transistors by non-covalent functionalisation

Field-effect transistors (FETs) with non-covalently functionalised molybdenum disulfide (MoS2) channels grown by chemical vapour deposition (CVD) on SiO2 are reported. The dangling-bond-free surface of MoS2 was functionalised with a perylene bisimide derivative to allow for the deposition of Al2O3 dielectric. This allowed the fabrication of top-gated, fully-encapsulated MoS2 FETs. Furthermore, by the definition of vertical contacts on MoS2, devices, in which the channel area was never exposed to polymers, were fabricated. The MoS2 FETs showed high mobilities for transistors fabricated on SiO2 with Al2O3 as top-gate dielectric. Thus, gate-stack engineering using innovative chemistry is a promising approach for the fabrication of reliable electronic devices based on 2D materials.

Besides the challenges in synthesis, one of the major issues in fabrication of reliable devices with monolayer TMDs is control over the surface chemistry. Due to their monolayer nature the properties of 2D materials depend strongly on the environment. Adsorbates lead to doping via charge transfer, resulting in significant changes in the electrical properties. This effect is exploited in chemiresistors or ChemFETs for chemical sensing. 29,30 Furthermore, most monolayer TMDs are unstable and degrade under ambient conditions due to oxidation by water and/or oxygen. 31,32 This leads to deteriorated performance of FETs due to hysteresis and undefined doping. Therefore, it is important to passivate the 2D channels of devices for their stable operation. High- materials are considered to be excellent passivation layers and gate insulators. In general, they are suitable for low leakage and low power logic devices due to the high dielectric constant. 33 Furthermore, high- materials improve carrier mobility by reducing Coulomb scattering for nanostructures 34 or increasing the effective gate electric field. 35 Al2O3 is one of the most commonly used high- materials, often deposited using trimethylaluminum (TMA, Al(CH3)3) and an oxidation agent, water or ozone, by atomic layer deposition (ALD). However, the basal planes of 2D nanosheets, such as graphene or MoS2, do not react with TMA due to the lack of dangling bonds or surface hydroxyl groups. [36][37][38][39] Thus, the formation of a seeding layer is required to perform ALD on the clean surface of 2D van der Waals crystals. We have shown that when perylene bisimides are deposited from the liquid phase onto graphene they form self-assembled monolayers (SAMs). 40,41 Specifically, -COOH and -OH units of the molecule react with TMA and promote the nucleation. 33,42,43 The same noncovalent functionalisation route was adopted for TMD layers, 44 wherein the perylene bisimide functional layer served as a stable seeding layer for Al2O3 deposition via ALD.
In this study we fabricated top-gated FETs with functionalised CVD-grown MoS2. The perylene bisimide functional layer is used as a seeding layer for Al2O3 deposition, fabricating fully encapsulated MoS2 FETs. We compared the devices fabricated by two different process flows. In both cases the electrical integrity of the TMD is maintained. Furthermore, the influence of polymer residue on device performance could be quantified.

MoS2 Growth
MoS2 samples were grown in a micro cavity in a two-zone CVD furnace at 700°C as described previously. 26 The samples were grown directly on SiO2/Si (300 nm thick SiO2, highly p-doped Si) substrates with MoO3 and sulfur as solid precursors.

Device Fabrication
Back-gated MoS2 FETs: The source/drain electrodes on MoS2 flakes were patterned by electron beam lithography (EBL), with electron beam resist (PMMA -A4, MicroChem) which was spin-coated onto the sample. EBL was performed using a Zeiss Supra 40 with a Raith EBL kit. After baking at 180 °C and developing with a MIBK:IPA (1:3) solution, the metal electrodes (Ti/Au, 5 nm/50 nm) were deposited by sputtering using a Gatan Precision Etching and Coating System (PECS).
Top-gated MoS2 FETs Type 1: Directly after the MoS2 growth, perylene bisimide dissolved in aqueous buffer solution was deposited on the sample. Source/drain electrodes were defined by EBL as described above. The metal electrodes (Ti/Au, 5 nm/50 nm) were deposited by using an electron beam evaporator (Temescal FC-2000). After lift-off, a 34 nm thick Al2O3 layer was then deposited on the MoS2 channel region which was defined by EBL, using ALD (TP01, ATV Technology) with TMA and H2O precursors at 80°C . The Al2O3 thickness was measured by atomic force microscopy (AFM) as shown in Figure S1(a). Finally, the top-gate metal electrode (Ti/Au, 5 nm/50 nm), patterned by EBL, was sputtered (Gatan Precision Etching and Coating System).
Top-gated MoS2 FETs Type 2: Directly after the MoS2 growth, perylene bisimide dissolved in aqueous buffer solution was deposited on the MoS2. Subsequently, a 16 nm thick Al2O3 layer was deposited onto the samples by ALD at 80°C with TMA and H2O as precursors. The height profile of the first ALD-grown Al2O3 layer measured by AFM is shown in Figure S1(b). PMMA (A4, MicroChem) was then spin-coated on the Al2O3 layer and source/drain electrodes were defined by EBL. After development, the exposed Al2O3 layer was removed by 2.38% Tetramethylammonium hydroxide (TMAH) solution in H2O at 55°C, creating a vertical contact hole (VIA). Then metal electrodes (Ti/Au, 5 nm/50 nm) were deposited by electron beam evaporation, followed by lift-off. In order to prevent the possible leakage of the gate dielectrics during electrical measurements, an additional 24 nm of thick Al2O3 was deposited onto the gate region. The AFM height profile of the second ALD Al2O3 thickness is shown in Figure S1(c). In a subsequent step, the top gate electrode was defined by EBL and the gate metal electrode (Ti/Au, 5 nm/50 nm) was sputtered, followed by lift-off.
Raman spectroscopy was performed by using LabRam ARAMIS IR2 (HORIBA JOBIN YVON) and a WITec Alpha 300R using a 532 nm laser as excitation source. Thicknesses of Al2O3 and MoS2 were measured using AFM (MFP-3D, Asylum Research). The topographic images of the MoS2 surface were measured by AFM (Park Systems Park XE100). Scanning electron microscopy (SEM) imaging was done using a MIRA3 (TESCAN). Electrical measurements were conducted on a JANIS probe station connected to a Keithley 2612A source meter unit under vacuum (top-gated FETs: ~3.7 Torr, back-gated FETs: ~2.3•10 -4 Torr) at room temperature. The substrate was connected to the ground during the electrical measurement of the top-gated FETs. The CVD growth yields randomly distributed, monolayer MoS2 regions, e.g. flakes, which are mostly triangular in shape and extend over several micrometers. In Figure 1 typical results of CVD-grown MoS2 on SiO2 are presented. In Figure 1(a) a SEM image of the triangular shaped MoS2 is shown. AFM measurements confirmed the monolayer nature of the triangular regions, as shown in Figure 1(b) and (c). A Raman spectrum of an as-grown MoS2 flake is shown in Figure 1(d), the in-plane (E') and out-of-plane (A'1) peaks occur at 383 and 403 cm −1 , respectively, which is consistent with monolayered MoS2. Some bilayer and/or multilayer formation also can take place in the seeding regions of the flakes as shown in the inset of Figure 2 To reveal the electrical properties of the CVD-grown MoS2, flakes were contacted by EBL-defined electrodes as shown in figure S2(a). Using the substrate as the back gate, a FET with an MoS2 channel was defined as schematically shown in the inset of figure S2(a). The FET shows on/off ratios with an order of 10 3 , and the average field-effect mobility of the device is 0.66 cm 2 /Vs for forward sweep and 0.79 cm 2 /Vs for reverse sweep. These relatively low mobility values can be attributed to the scattering of carriers at the surface and the SiO2 substrate. 45 In order to improve the performance, FETs in which the MoS2 channel is encapsulated and the channel has a top-gate electrode, separated by a high- oxide for effective modulation, can be fabricated. The gate dielectric deposition is ideally realised in a nondestructive and scalable manner by ALD. However, generally ALD on clean 2D van der Waals materials is challenging, due to the absence of seeding sites such hydroxyl or carbonyl oxides. 39 Figure 2(a). The step height between monolayer and substrate is approximately 0.34 nm. The MoS2 lies on average lower than the SiO2 substrate, and the monolayer surface is very rough. This is attributed to inhomogeneous and imperfect deposition of Al2O3 on the monolayer. Evidently, on the monolayer MoS2 some Al2O3 island growth has taken place, but no continuous, complete coverage is reached. The step height between multilayer and substrate is approximately 1.3 nm, and this is close to the thickness of bilayer MoS2. This indicates that in the multilayer region Al2O3 growth took place. Also, Al2O3 deposition can be seen at the edges of the monolayer MoS2 flakes resulting in high step at the edge of the MoS2 flake. This is attributed to a higher abundance of reactive site such as dangling bonds and defects at the edges of MoS2 layers acting is anchor sites for the deposition of Al2O3. 44 Figure 2(b) shows an AFM topography image of an ALD-Al2O3 layer on a perylene bisimide-covered MoS2 flake with 45 cycles of TMA/H2O at 80 °C. In contrast to Figure 2(a), the Al2O3-MoS2 surface in Figure 2(b) is uniform and lies higher than the SiO2 substrate. Thus, the perylene bisimide layer acts as a seed for ALD growth, resulting in a homogenous and continuous Al2O3 layer. Figure 2(d) shows the line profiles of Figure 2(b) from the MoS2 flake to the substrate. The step height between monolayer and substrate is approximately 1.75 nm, and this exceeds the monolayer thickness. The additional thickness is attributed to the perylene bisimide layer. Thus, the perylene bisimide functionalisation allows the ALD of dielectrics on clean dangling-bond-free TMD surfaces. Having optimized the dielectric deposition, we investigated the viability of our non-covalent functionalisation to optimize the gate-stack formation of 2D material FETs. The process flow to yield fully encapsulated top-gated MoS2 FETs (device type 1) is shown in the schematic Figure 3(a). It follows the standard device fabrication processes with E-Beam resist (PMMA) deposition directly onto the whole substrate; however in our case the PMMA was deposited after deposition of the perylene bisimide ( Figure  3(b)). Source/drain electrodes were patterned by EBL and deposited by evaporation. After lift-off, the Al2O3 gate dielectric was deposited on the entire MoS2 channel region defined by EBL. This was followed by the deposition of the top gate electrode, after another lithographic step. An optical image of one device is shown in Figure 3(c). Raman spectroscopy was used to confirm the presence of MoS2 monolayer and perylene SAM after completion of the gate stack. Figure 3(d) shows the peaks at positions at ~384 cm -1 and 401 cm -1 for the completed device, corresponding to the E' and A'1 modes of MoS2, respectively. Furthermore, the spectra exhibit several peaks in the region of 1300 cm -1 to 1600 cm -1 typical for perylene bisimide. This underlines the remarkable stability of the perylene SAM, it withstands the polymer removal with acetone and the ALD process. Figure 4(a) shows the IDS-VDS output characteristics at various top-gate voltages (VTG) of device type 1. The SiO2 substrate of the device was grounded during all measurements, reducing possible capacitive coupling between top-and back-side dielectrics. 49 Linear behavior is observed at each VTG, which indicates that the integration route yields good contacts and that the perylene bisimide layer does not significantly affect contact properties between MoS2 and the electrodes. Figure 4(b) shows the typical IDS-VGS transfer characteristics of device type 1. This exhibits a counter clockwise hysteresis. The reverse sweep of the top-gate voltage, VTG, exhibits a higher conductivity compared with the forward sweep of VTG. The counter clockwise hysteresis can be attributed to the positive mobile charges in Al2O3. 50,51 In the forward VTG sweep, positive mobile charges in Al2O3 move to the Al2O3/(perylene bisimide)/MoS2 interface. In the reverse VTG sweep, the positive mobile charges located near the MoS2 surface induce an additional electrical field, and this leads to a lower threshold voltage (VTH) and increases current. Additionally, we compared transfer characteristics between two back-gated MoS2 FETs, with and without a perylene bisimide layer on the MoS2 channels. As shown in figure S2(c) and (f) of the Supporting Information, both devices show a similar hysteresis trend, indicating that the perylene bisimide layer does not play an important role in the observed hysteresis. Sub-threshold swing is 283 mV/decade for the forward sweep and 214 mV/decade for the reverse sweep. The field-effect mobility (FE) is calculated by the transfer characteristic using the following equation: (1) where CAl2O3 denotes gate dielectric capacitance, gm denotes transconductance, VDS denotes drain-source voltage, L denotes channel length, and W denotes channel width. The channel shape does not often correspond to a rectangle, and thus the channel width is obtained by dividing the total channel area by the channel length. The FE of the device is 21.4 cm 2 /Vs for the forward sweep and 33.4 cm 2 /Vs for the reverse sweep. The red line in Figure 4(b) indicates the gm of the device. The slope of drain/source current significantly increases until the gm reaches a peak, and then decreases when VTG increases. However, the device exhibits an intriguing second gm peak for the forward VTG sweep (blue-circled region) which is consistent with a small hump in the transfer characteristics at the same VTG. Such second gm peak was also observed at various VDS (Figure 4(d)) in four out of five samples. Interestingly, as shown in Figure  4(e), the second gm peak appears at the similar VTG (~16 V) in all four samples regardless of VDS, indicating that there is a common reason for the second gm peak with reproducibility. Similar signatures in the transfer characteristics were observed in SOI MOSFETs, 52-56 polysilicon thin film transistors, 57 and gate injection GaN-based transistors. 58 Even in the case of previous studies of SOI MOSFETs, which are more optimized than the MoS2 FETs studied here, the origin of additional transport carriers varied depending on the device structure and materials. Thus, the origin of second gm peak cannot be exactly determined at this stage. However, as shown in Figure 4(b), a slight increase in current was observed at VTG of the second gm peak. As discussed in previous studies, 52-58 the injection of additional transport carriers could be considered as one of the reasons for the second gm peak. In the case of device type 1 the leakage current (see Figure 4(f)), obtained by measuring the IDS at VDS =0 V under a VTG sweep, can be ruled out as a source of the additional carriers, since it is too low to affect the transfer characteristics. The devices can be expressed using an equivalent circuit model, composed of a main transistor connected to a parasitic transistor in parallel, as shown in the inset of Figure 4(e). In the equivalent circuit model, the threshold voltage of the main transistor differs from that of the parasitic transistor. The second gm peak value is small compared to the first gm peak, as shown in Figure 4(b). This is because the current   generated after the parasitic transistor turns on is low. Thus, the second gm peak can be preliminarily attributed to the presence of polymer residue that acts as a parasitic transistor. A second more advanced process flow avoiding any contact of the channel region with polymer resist was developed. As shown in Figure 5(a), for device type 2 we deposited the Al2O3 layer on the whole substrate directly after perylene bisimide functionalisation. The source/drain electrodes were patterned by EBL, effectively creating contact holes by wet etch of the Al2O3 layer with an etch stop on the MoS2. This realisation of vertical interconnects (VIAs), with metal evaporation to contact 2D materials is an important step to their successful integration. Importantly, this process flow has an advantage that the MoS2 channel is never in contact with polymer resist. The presence of perylene between the Al2O3 and the MoS2 was confirmed by using Raman spectroscopy. The spectra were taken after device fabrication was completed. Like device type 1, the typical signatures for MoS2 at ~385 cm -1 and 405 cm -1 and perylene at 1300 cm -1 to 1600 cm -1 are observed as shown in Figure 5(c). In Figure 6(a), the output characteristics of device type 2 are shown. They exhibit a linear behavior like device type 1, indicating that the contacts between the monolayer MoS2 and electrodes, which were defined by VIA etching and filling, were well established. This is an important achievement for the integration of 2D materials. Figure 6(b) shows transfer characteristics and transconductance of the device. A counter clockwise hysteresis appears, similar to the device type 1. Sub-threshold swing is 255 mV/decade for the forward sweep and 224 mV/decade for the reverse sweep. The FE of device was extracted to be 22 cm 2 /Vs for the forward sweep and 48.7 cm 2 /Vs for the reverse sweep. Unlike device type 1, the second gm peak was not observed in device type 2, as shown in red line of Figure 6  The main difference between device type 1 and 2 is that in the latter case the functionalized MoS2 channel was not in contact with the resist during the fabrication. It is well known that resist residues can remain on the film surface after development and lift-off processes. To investigate this, the MoS2 surface was characterized by AFM during fabrication. Figure 7(a) shows the functionalized MoS2 surface after the development of the polymer resists during the fabrication of device type 1 (step 2 in Figure 3(a)). A relatively rough surface with a root-mean-square (RMS) roughness of 0.54 nm was observed. This roughness is likely due to polymer residues which remain in the channel area. In contrast, the functionalized MoS2 surface after wet-etching of the contact area (step 3 in Figure 5(a)) of the device type 2 appears to be relatively flat (RMS roughness = 0.30 nm). Both the RMS and average values of the surface roughness of device type 1 clearly exceed those of device type 2. Thus one can deduce that while type 1 devices have polymer residues on the surface of the channel, type 2 devices have a relatively clean interface to the top gate dielectric. Thus we can tentatively attribute the second gm peak to the polymer residue in the channel area in device type 1, however additional experiments are required to analyze the exact mechanisms that cause the second gm peak.

Results
To investigate the influence of resist residues on the device performance, five samples were fabricated and compared for each device type. Threshold voltage, mobilities and contact resistances of the devices are summarized in Figure 7(c), (d) and (e). Device type 1 (34 nm) and 2 (40 nm) has different Al2O3 thickness. Even applying same gate voltage, gate electric field is different depending on dielectric thickness. As considered to gate electric field, threshold voltage was multiplied by CAl2O3. As shown in Figure 7(c), the hysteresis (VTH,reverse-VTH,forward) of device type 2 (0.0235 VFm -1 ) increased by 26% compared to device type 1 (0.0187 VFm -1 ). During the second deposition of Al2O3 of device type 2, interface states would form between the first and second ALD-Al2O3 layers and the overall quality of the Al2O3 of device type 2 would get worse, leading to large hysteresis compared to device type 1. As shown in Figure 7(d), the average FE of device type 1 is lower than that of device type 2. In particular, the average FE of the device type 2 (32.3 cm 2 /Vs) for the reverse sweep increased by 61% compared to device type 1 (20.1 cm 2 /Vs). This can be tentatively assigned to increased surface roughness and remote charge scattering. As shown in Figure 7(a), the functionalized MoS2 surface of device type 1 has resist residues in the channel area, unlike device type 2. Even though the resist residues may not directly adhere to MoS2 due to the perylene SAM, it can increase the surface roughness and act like a fixed charge inside the gate stack. This latter disturbance can cause scattering by remote surface scattering. 59,60 Further studies are needed to understand why the FE of both device types is more pronounced in the reverse sweep than in the forward sweep in Figure 7(d). The effect of resist residues on the contact resistance of the device was also investigated. As shown in Figure 7(e), in the high VTG region in Figure 4(b) and Figure 6(b), the current is saturated due to the influence of contact resistance (Rs). Rs is extracted by using an equivalent circuit model with a resistor serially connected to the transistor as shown in Figure 7(f). Rs is obtained by using the graphical method 61 and the following equation: (2) At VDS=1 V, the Rs along each sweep direction was calculated by using the transfer characteristics. Different channel widths (W) were considered for each device, and the width was multiplied by Rs. The distribution of the RsW of device type 1 and 2 is shown in the Figure 7(e). The average RsW of device type 2 (0.95 m) for forward sweep reduced by 8% compared to device type 1 (1.03 m), and the average RsW of device type 2 (1.02 m) for reverse sweep reduced by 11% compared to device type 1 (1.15 m). This strongly suggests that the absence of polymer residues in the source and drain contact regions reduces the contact resistance, but the effect of polymer residues on mobility exceeds that of the contact resistance. In

Conclusion
In this study, top-gated FETs with CVD-grown MoS2 were fabricated. A non-covalent perylene bisimide functionalization was used to facilitate ALD of Al2O3 as a dielectric and passivation layer. Perylene bisimide was simply deposited on MoS2 by drop-casting at room temperature. Furthermore, we were able to define vertical contacts to the MoS2 channels, yielding fully-encapsulated MoS2 FETs. Perylene bisimide was non-destructively attached to MoS2 and led to improved device performance as revealed by surface characterization and electrical measurements. The field-effect mobility for the MoS2 FETs was found to be 48.7 cm 2 /Vs. Thus our work suggests that non-covalent functionalisation is a viable strategy to fabricate devices with monolayer 2D materials. Additionally, we investigated the effect of resist residues on field-effect mobility and contact resistance. This study represents a significant step towards the fabrication of reproducible TMD-based devices, with interface engineering for passivation and dielectric deposition and contact formation as well as better understanding of the effects of polymer residues.