5 nm Gate length field-effect transistors based on monolayer α-In2X3 (X = S, Se, Te)

Abstract

Recently, α-In₂X₃ (X = S, Se, and Te) two-dimensional (2D) ferroelectric semiconductors have emerged as a research focus due to their ferroelectricity. However, the potential of their semiconductivity for future field-effect transistors (FETs) remains unclear. Herein, this work quantifies the performance limit of 5 nm gate length (L_g) monolayer (ML) α-In₂X₃ double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) and compares the performance of these devices with non-underlap (non-UL) and symmetric underlap (UL) configurations, using first-principles quantum-transport simulation. For the devices with non-UL configurations, the α-In₂S₃ MOSFET demonstrates both the highest on-state current (I_on) and the lowest subthreshold swing (SS). Meanwhile, the α-In₂Se₃ MOSFET shows a low SS, and the α-In₂Te₃ MOSFET shows a high I_on. Due to the influence of effective mass and bandgap energy, n-type ML α-In₂S₃ and α-In₂Te₃ MOSFETs demonstrate superior I_on compared to their α-In₂Se₃ counterparts. For the devices with UL configurations, the I_on of all ML α-In₂X₃ DG MOSFETs can meet the International Technology Roadmap for Semiconductors (ITRS) high-performance (HP) and low-power (LP) standards for 2028. Moreover, all ML α-In₂X₃ DG MOSFETs achieve ideal SS with the aid of the UL. These results indicate that ML α-In₂X₃ is a viable candidate for future MOSFET channel materials.