Residual stress modulation as a pathway to reliable multilevel 3D NAND flash storage

Abstract

Three-dimensional (3D) NAND flash memory achieves high density through the vertical stacking of memory cells. However, increasing the number of stacked layers induces significant residual stress, which adversely impacts both structural integrity and electrical characteristics of 3D NAND devices. Thus, effective analysis and management of residual stress in 3D NAND are required. This study employs a Sentaurus technology computer-aided design (TCAD) simulation to examine the effect of residual stress on the reliability of charge-trap 3D NAND. The results show that increasing the compressive stress in the charge-trap nitride (CTN) layer improves data retention through band-edge modulation. To utilize these effects, we propose the insertion of a stress engineering layer (SEL) between the poly-Si channel and surrounding oxide filler. The SEL increases the compressive stress within the CTN layer. Thus, the retention degradation can be reduced. The proposed SEL technique demonstrates the potential to improve the reliability of 3D NAND flash memory by modulating residual stress.