Raised or Recessed? Finding the Optimal Gate Architecture for Improving the Static Performance of Graphene Transistors

Abstract

As silicon CMOS technology approaches its scaling limits, graphene offers a compelling alternative as the active material channel in transistors due to its high carrier mobility and atomically thin profile, which provide strong electrostatic control and promise high-performance analog applications. However, roadblocks such as device-to-device variation, high contact resistance, poor dielectric interfaces, and non-uniform graphene quality have limited the adoption of graphene field effect transistors (GFETs). Hence, further investigations are required for mitigating these issues at a material, e.g., by improving graphene transfer, and device level, e.g., by finding an appropriate gate architecture. In this work, we directly compare two GFET structures through a controlled, side-by-side process split to evaluate the impact of gate stack architecture: raised vs. recessed buried local gate, in which both structures use hBN as the gate dielectric. Benchmarking is performed in terms of device performance and device-to-device variation. While the top-performing devices remain similar across the two proposed structures, significant statistical differences are seen in terms of device performance and yield in the two populations studied. A total of 256 identical devices from each gate architecture are electrically tested and characterized for a statistically significant comparison. The most significant difference is seen in the Dirac voltage, which is reduced from 1.2 V to 0.7 V with the recessed architecture, making it more suitable for low-power analog applications. Average hole mobility increases from 3,383 cm 2 V -1 s - 1 to 4,794 cm 2 V -1 s -1 , and device yield increases from 54.4% to 65.1%. Physical analysis, which includes spectroscopy and hysteresis measurements, indicates that these improvements are due to the proposed planarized gate architecture and reduction of interface defects. This study shows that direct statistical comparison studies of process conditions can help identify favorable process conditions to improve the manufacturability of graphene-based transistors.