Single-layer HfN2: symmetric scaling behavior in CMOS transistors

Abstract

Efficient operation of complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) requires good symmetry between NMOS and PMOS transistors to ensure fast signal processing and logic operations. However, most research focuses on whether individual NMOS or PMOS devices meet the requirements of the International Technology Roadmap for Semiconductors (ITRS), with rare discussion on the symmetry of the quality factors between the two devices. Here, first-principles quantum transport simulations are employed to investigate the symmetric transport behavior of single-layer (SL) HfN₂ in CMOS transistors. Results indicate that HfN₂ NMOS and PMOS still outperform the high-performance benchmarks of the ITRS at a 3 nm gate length (L_g) limit. Excellent symmetry between NMOS and PMOS devices is observed for L_g = 5–1 nm, where the ratio of ON-state current, subthreshold swing, delay time, and power-delay product is close to 1. These findings offer theoretical insights for the application of SL HfN₂ in symmetric CMOS ICs.