High ON/OFF ratio and near-thermal subthreshold swing in a p-type silicon channel field-effect transistor

Abstract

We performed a numerical simulation of a field-effect transistor (FET) employing a p-type silicon channel and a SiO₂ gate dielectric using Silvaco Atlas TCAD. The device structure shows remarkable switching performance with the subthreshold swing (SS) reaching near thermal limits at 86.5 mV dec⁻¹ (drain voltage −0.1 V) and 152 mV dec⁻¹ (drain voltage −3 V). The FET operates with ultra-high ON/OFF current ratios of ∼10¹¹ and peak field-effect mobilities of about 2 cm² V⁻¹ s⁻¹ under a low drain bias. The mobilities exhibits degradation due to enhanced scattering at higher biases. The simulation also emphasizes the interplay of the drain voltage affecting the transfer characteristics, highlighting the importance of electrostatic design for high-performance, low-power p-type silicon-based FETs.