A next-generation transistor with low supply voltage operation constructed based on 2D materials' metal–semiconductor phase transition

Abstract

Power dissipation, a fundamental limitation for realizing high-performance electronic devices, may be effectively reduced by an external supply voltage. However, a small supply voltage simultaneously brings another serious challenge, that is, a remarkable device inability in transistors. To deal with this issue, we propose a new transistor design based on the metal–semiconductor phase transition in a AsGeC₃ monolayer, which provides a switching mechanism of band-to-band tunneling at on- and off-states by gate-voltage modulation. Our first-principles calculations uncover that the monolayer AsGeC₃ field-effect transistors (FETs) with gate lengths of 5, 4, and 3 nm may meet well the requirements for on-state current (I_on), power dissipation (PDP), and delay period (τ) as outlined by the International Technology Roadmap for Semiconductors (ITRS) in 2013 to achieve higher performance by the year 2028. Importantly, high performances are achieved only under a very low supply voltage (V_DD = 0.05/0.10 V). Significantly, the AsGeC₃ FETs exhibit remarkably lower values of both PDP and τ than those of nearly all the transistors reported up to date. These novel 2D metal–semiconductor phase transition-based FETs open up a new door for designing next-generation low-power electronic devices.