The Role of Hybrid Dielectric Interface in Improving the Performance of Multilayer InSe Transistors
In graphene-like 2D layered semiconductors based field-effect transistors (FETs), device performance is strongly influenced by semiconductor-dielectric interface. In this study, it is demonstrated that hybrid dielectric interface combines the advantages of high dielectric constant and inert polymer dielectric layer, and their synergistic effect induce the improvement of InSe FETs performance. FETs with hybrid dielectric interface, composed of 200 nm PMMA and Hf0.5Zr0.5O2/Al2O3(HZO/AlO), displays a mobility of 863 cm2 V-1 s-1, a relatively low sub-threshold swing of 462 mV dec-1, a diminutive hysteresis loop, an ultrahigh Ion-off ratio of ~107, and low leakage current, superior to that using conventional single dielectric layer. Experimental and theoretical results proved that low density of charge trapping states and suppression of scattering effect at the semiconductor-dielectric interface synergistically result in enhanced device performance. Present study indicates that the smart combination of inert polymer buffer layer on high-κ constant oxides is effective to optimize the semiconductor-dielectric interface, and promising to fabricate high performance FETs for next-generation electronic devices.