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Issue 3, 2020
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Parallel weight update protocol for a carbon nanotube synaptic transistor array for accelerating neuromorphic computing

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Abstract

Brain-inspired neuromorphic computing has the potential to overcome the inherent inefficiency of the conventional von Neumann architecture by using the massively parallel processing power of artificial neural networks. Neuromorphic parallel processing can be implemented naturally using the crossbar geometry of synaptic device arrays with Ohm's and Kirchhoff's laws. However, selective and parallel weight updates of the synaptic crossbar array are still very challenging due to the unavoidable crosstalk between adjacent devices and sneak path currents. Here, we experimentally demonstrate a weight update protocol in a carbon nanotube synaptic transistor array, where selective and parallel weight updates can be executed by exploiting the individually controllable three terminals of the synaptic device via a localized carrier trapping mechanism. The trained 9 × 8 synaptic array solves four different convolution operations simultaneously for the feature extraction of an image. The massive parallelism and robustness of the weight update protocol are important features toward effective manipulation of big data through neuromorphic computing systems.

Graphical abstract: Parallel weight update protocol for a carbon nanotube synaptic transistor array for accelerating neuromorphic computing

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Article information


Submitted
21 Oct 2019
Accepted
20 Dec 2019
First published
23 Dec 2019

Nanoscale, 2020,12, 2040-2046
Article type
Paper

Parallel weight update protocol for a carbon nanotube synaptic transistor array for accelerating neuromorphic computing

S. Kim, Y. Lee, H. Kim and S. Choi, Nanoscale, 2020, 12, 2040
DOI: 10.1039/C9NR08979A

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