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Asymmetric Hot Carrier Tunneling van der Waals Heterostructure for Multi-bit Optoelectronic Memory

Abstract

Two-dimensional float gate van der Waals heterostructures exhibit appealing opportunity in combining optoelectronic sensing and memory functions in atomically thin layers, which as optoelectronic memories can find applications in high-throughput image sensors and artificial photonic neuromorphic hardware, etc. However, existing optoelectronic memory generally suffers overshoot characteristics after optical stimulation due to the inherent and persistent recombination loss of photogenerated electron-hole pairs. Here, we demonstrate a multibit float gate optoelectronic memory free from such transient dynamics based on a new van der Waals heterostructure of PtS2/h-BN/graphene. The large electron affinity of PtS2 renders highly asymmetric tunneling barriers for hot electrons and holes across h-BN, thereby enabling efficient separation of photogenerated electron-hole pairs during the optical program of memory. A laddering optical program of up to 74 discriminable states (>6 bits) is thus achieved with linear conductance update in memory using sequentially applied light pulses. The present two-dimensional heterostructure with asymmetric charge tunneling barriers may enlighten future exploration of practical multibit optoelectronic memories via attentive band engineering in two-dimensional van der Waals heterostructures.

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Supplementary files

Article information


Submitted
01 Dec 2019
Accepted
14 Jan 2020
First published
14 Jan 2020

Mater. Horiz., 2020, Accepted Manuscript
Article type
Communication

Asymmetric Hot Carrier Tunneling van der Waals Heterostructure for Multi-bit Optoelectronic Memory

Y. Chen, J. Yu, F. Zhuge, Y. He, Q. Zhang, S. Yu, K. Liu, L. Li, Y. Ma and T. Zhai, Mater. Horiz., 2020, Accepted Manuscript , DOI: 10.1039/C9MH01923E

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