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Poly-GeSn junctionless P-TFTs featuring a record high ION/IOFF ratio and hole mobility by defect engineering

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Abstract

2-Stage defect engineering of poly-GeSn (Sn: ∼5.1%) film for bottom-gate junctionless P-channel thin film transistors (JL P-TFTs), including gas annealing and plasma treatment, is investigated in this work. Stage I of the Ar gas annealing is effective in enhancing the grain size, which helps suppress the grain boundary density and bulk trap density of the surface part of the poly-GeSn film. With the subsequent stage II of the NH3 plasma treatment, both the defect density at the gate dielectric interface and in the bulk poly-GeSn film can be greatly reduced by terminating the intra- and inter-grain dangling bonds via radical diffusion along the grain boundaries. With the improved defect density of 9.2 × 1011 cm−2 by stage I and II, JL P-TFTs exhibit a record high peak field-effect hole mobility of 162.2 cm2 V−1 s−1 and an ION/IOFF ratio of 2.8 × 105 even with a planar structure. In addition, enhanced reliability performance in terms of reduced stress induced leakage current and improved bias induced instability is also achieved. Moreover, the low-thermal-budget process of 500 °C for 30 s paves a new avenue towards creating high-performance monolithic 3D ICs.

Graphical abstract: Poly-GeSn junctionless P-TFTs featuring a record high ION/IOFF ratio and hole mobility by defect engineering

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Publication details

The article was received on 01 Oct 2018, accepted on 01 Apr 2019 and first published on 02 Apr 2019


Article type: Paper
DOI: 10.1039/C8TC04972F
Citation: J. Mater. Chem. C, 2019, Advance Article

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    Poly-GeSn junctionless P-TFTs featuring a record high ION/IOFF ratio and hole mobility by defect engineering

    C. Chou, Y. Lin, K. Hsieh and Y. Wu, J. Mater. Chem. C, 2019, Advance Article , DOI: 10.1039/C8TC04972F

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