Silicon nanowires and nanotrees: elaboration and optimization of new 3D architectures for high performance on-chip supercapacitors

Abstract

Micro-supercapacitors are increasingly foreseen as future energy storage or power buffer solutions for small scale integration on-chip. However, widely used electrode materials or electrolytes often proved to be incompatible with microelectronics processes. Although being the material of choice for on-chip integration, nanostructured silicon electrodes only recently caught attention for potential applications, and they displayed promising results especially for bottom-up silicon nanostructures, where the design liberty and fine control of nanostructure morphologies allow considerable improvements. The present work deals with the optimization of highly doped silicon nanowires (Si-NWs) and nanotrees (Si-NTrs) pioneered in the laboratory using an innovative, fast and efficient electroless gold deposition method in order to explore a wide variety of 3D architectures and their physicochemical properties. Through a systematic study of branches and trunks morphologies, the nature inspired nanotrees have been drastically improved compared to previously published works, resulting in excellent electrode properties, showing high energy and power densities, respectively, up to 2.8 mJ cm⁻² and 235 mW cm⁻². In addition, a cyclability of over a million charge–discharge galvanostatic cycles was determined using an enlarged electrochemical window of 4 V in an ionic liquid electrolyte.