3C-SiC carbonization optimization and void reduction on misoriented Si substrates: from a research reactor to a production scale reactor
In this work, we studied how to optimize the carbonization process in order to deposit cubic SiC (3C-SiC) on misoriented Si substrates. The carbonization process is a key step to obtain device-quality layers and to partially release the strain due to the lattice mismatch between the substrate and the thin 3C-SiC film. One of the common problems in SiC/Si epitaxy is the presence of interfacial voids that can degrade the structural quality of the deposited film and the electrical properties in vertical devices. Carbonization optimization requires careful control of several parameters, in particular temperature, precursor flows, and heating ramps. Precise tailoring of this process on a production reactor with the understanding of all the involved variables would require huge effort in terms of time and money, so it is desirable to perform part of this work on a smaller scale research reactor, which is more versatile and economically viable. Starting from a baseline process for 3C-SiC power devices on 100 mm Si already developed on a production reactor, we used a small research reactor to investigate how the thermal heating profile during the carbonization ramp influences the void density on the Si substrate. We have also studied how the introduction of silane during the carbonization ramp can effectively suppress void formation. After having obtained a comprehensive understanding of the variables involved in the process, the key ideas were successfully implemented in the production reactor, resulting in a significant reduction of interfacial voids.