Competitive effects of oxygen vacancy formation and interfacial oxidation on an ultra-thin HfO2-based resistive switching memory: beyond filament and charge hopping models†
We studied the quantum transport mechanism of an ultra-thin HfO2-based resistive random access memory (ReRAM) cell with TiN electrodes and proposed the design of a sub-10 nm scale device. It is believed that formation and rupture of the conduction path in the local filament causes the switching between high and low resistive states. However, the validity of this simple filament model is not obvious in the sub-10 nm scale device because the redox processes occur mainly in a few nm range at the interface. Furthermore, the intrinsic transport mechanism of the device, in particular, quantum coherence, depends on device materials and length-scale. The relationship between the redox states and the transport mechanism like ballistic or hopping is still under debate when the device length scale is less than 10 nm. In the present study, we performed first-principles calculations of the non-equilibrium Green's function including electron–phonon interactions. We examined several characteristic structures of the HfOx wire (nano-scale conduction path) and the interfaces between the resistive switching layer and electrodes. We found that the metal buffer layer induced a change in the oxygen-reduction site from the interface of HfOx/TiN to the buffer layer. Even when the inserted buffer layer is a few atomic layers, this effect plays an important role in the enhancement of the performance of ON/OFF resistive switching and in the reduction of the inelastic electric current by electron–phonon scattering. The latter suppresses the hopping mechanism, which makes the ballistic conduction the dominant mechanism. We evaluated the activation energy in the high temperature limit by using the first-principles results of inelastic current. Our theoretical model explains the observed crossover of the temperature dependence of ReRAM cells and gives a new insight into the principle of operation on a sub-10 nm scale ReRAM device.