Solution-processed high-κ SrTiO3 with high breakdown field for gate dielectrics

Abstract

As MOSFET dimensions approach their physical limits, conventional gate dielectrics struggle at the nanoscale to simultaneously deliver high breakdown strength and low power consumption. To address this challenge, an ethylene-glycol-chelated sol–gel route was employed to deposit high-κ strontium titanate (SrTiO₃) films on p-type highly doped silicon. The resulting films exhibit a relatively high breakdown field of 11.04 MV cm⁻¹ at 2.5 nm. Using the optimized dielectric, back-gated MoS₂ field-effect transistors were fabricated, which show a low subthreshold swing of ∼0.23 V dec⁻¹, gate leakage on the order of ∼10⁻¹¹ A, and an on/off ratio of ∼10⁶, confirming the feasibility of sol–gel STO as a high-κ gate insulator for 2D devices. These results establish a solution-processed STO platform that is compatible with silicon and amenable to integration with both 2D and oxide electronics.