Hydrated lithium phosphate as a low-temperature processable solid electrolyte for high-performance printed electronics

Abstract

Ion-conducting oxide (ICO) electrolytes have contributed to the advancement of various electrochemical devices, from lithium-ion batteries to electrochemical sensors. Notably, the ICOs have also been used as solid electrolytes for printed thin film transistors (TFTs). However, the printed TFT technology typically aims for flexible electronic applications, where the high process temperature of ICOs creates a big hindrance. In this regard, in the present study, we propose and demonstrate an extremely low-temperature processable (∼120 °C) solid electrolyte in the form of hydrated lithium phosphate (Li₃PO₄). The fully inkjet-printed TFTs fabricated with amorphous indium gallium oxide (a-IGO) as the semiconductor material demonstrate excellent transistor performance parameters, such as high on–off ratio, high width-normalized on-current density (I_D,ON/W), and width-normalized transconductance (g_m/W) of 3.8 × 10⁸, 63.2 µA µm⁻¹, and 39.4 µS µm⁻¹, respectively, and a subthreshold slope close to the Boltzmann limit (61 mV decade⁻¹). The maximum and average linear field-effect mobility of the TFTs are estimated to be 42.8 and 28.9 cm² V⁻¹ s⁻¹, respectively. The unipolar, depletion-load-type pseudo-CMOS inverters demonstrate rail-to-rail switching for supply voltages from 0.5 to 2 V, with a signal gain up to 33.4 V/V. The present results demonstrate the emergence of a novel low-temperature processed ICO-based solid electrolyte for printed TFTs to be used in various printable, wearable, and portable electronic applications.

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Introduction

Ion-conducting oxides (ICOs) are a type of ceramic electrolyte that has uncovered extensive application possibilities in fuel cells, sensors, lithium-ion batteries, electrochromic devices, etc.^1–3 A thin film of such ICOs has a large areal capacitance due to its light and mobile ions, such as Li⁺ and Na⁺, that can freely move through the crystal structure. In fact, there are a number of ICOs that combine ionic and electronic conduction; they are commonly known as mixed ion–electron conductors (MIECs). MIECs possess low electrical resistivity; therefore, they are not suitable as an electrolyte material. In contrast, electrically insulating ICOs can have very low electronic conductivity and a high breakdown voltage, making them suitable candidates for electrolytic applications, including gate insulators in the case of electrolyte-gated TFTs.^4–6 The use of such ICO-based gate dielectrics for TFT applications has been demonstrated for the first time with Na-β alumina, alongside solution-processed zinc tin oxide (ZTO) as the semiconductor material. However, the processing temperature of Na-β alumina thin film is extremely high (∼830 °C).⁷ Later on, various ICO systems were proposed and developed, including Li₅AlO₄, LiAlO₂, and LiInSnO₄, which offer substantially lower fabrication temperatures.^5,8–12 Alongside, proton-conducting perhydropolysilazane has been used as a gate dielectric of metal oxide TFTs.¹³ However, all these materials still require >350 °C processing temperatures, which are not compatible with flexible polymer substrates. In fact, flexible printed electronics necessitate a gate dielectric with low processing temperature, preferably ≤120 °C. In this regard, it should be noted that even though there are numerous reports of room temperature processed composite solid polymer electrolyte (CSPE)-gated high performance TFTs,^14–23 examples of low temperature processed ICOs are not available. On the other hand, although high-κ dielectric materials, such as HfO₂ and Al₂O₃, enable the realization of low-operating-voltage TFTs, their deposition typically requires vacuum-based processing techniques (e.g., ALD or sputtering), which significantly increases the fabrication cost and limits large-area scalability. Alternatively, the solution-processed routes involve high process temperatures around 300 °C or above, which is far beyond what the inexpensive polymer substrates, such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), can sustain.^24–27 In contrast, polymer-based gate dielectrics, such as PVA and PVP, can be readily processed or printed from solution; however, they typically require a high operating voltage that is not suitable for battery-compatible portable electronics.^28–31 Therefore, an ideal strategy involves developing gate dielectric materials that would be easy to print, and would simultaneously be low-temperature solution processable, demonstrating high capacitance and low operation voltage, with high electrical bias-stress and environmental stability. While electrolytic insulators demonstrate all these performance combinations, extensive study has only been carried out for CSPE or iongel-type solid electrolytes, whereas this paper demonstrates that low temperature processed high performance ion conducting ceramic electrolytes may also be a serious contender for printed flexible electronic applications.

Among different ICO materials, Al₂O₃-based materials can offer excellent chemical stability, they demonstrate a high breakdown field, and due to their abundance, they are relatively inexpensive compared to other ICO materials. However, it is certainly difficult to achieve a <200 °C processing temperature to deposit Al₂O₃-based ICO thin films. In addition to the Al₂O₃-based ICOs, PO₄-based conducting oxides are also quite popular and widely used in solid-state Li-ion batteries, due to their high Li⁺ mobility. Among them, Li₃PO₄, LiFePO₄, and LiTiPO₄ are used in commercial products.^32–34 However, the low-temperature solution processing of PO₄-based ICOs and their possible use in TFTs and electronic devices have not been explored yet.

In contrast, in this work, a facile and environment-friendly method has been developed for low-temperature processed (∼120 °C) fabrication of a Li₃PO₄ thin film using deionized water as the solvent and subsequent addition of a small amount of acetic acid to complete the dissolution process of Li₃PO₄. A thin film of Li₃PO₄ deposited by this synthesis technique offers low electronic conductivity with a high breakdown voltage, which is required for its use as a gate dielectric. The ionic conduction of Li⁺ ions in the Li₃PO₄ provides a high areal capacitance of the dielectric thin film that has been utilized for fabricating high-performance low-voltage (≤2 V) TFTs, as well as depletion-load type unipolar pseudo-CMOS inverters. The printed Li₃PO₄ layer is nanocrystalline, and the inter-crystallite Li⁺ ion conduction is found to be slow, especially for high-frequency electronic applications, such as TFTs or logic electronics. However, a small moisture content in air as low as 15–20% relative humidity has been proven to be sufficient to lower the inter-crystallite ion transport barrier substantially so that excellent transistor performance can be achieved. Consequently, in this case, it is better to call the hydrated Li₃PO₄ a composite solid electrolyte. Of course, the situation can be completely different when large crystals or a single crystal of Li₃PO₄ can be grown and used as the gate dielectric.

Experimental methodology

Semiconductor ink preparation

Semiconductor precursor ink to obtain amorphous indium gallium oxide (a-IGO) was prepared by dissolving indium(III) nitrate hydrate ([In(NO₃)₃·xH₂O], 99.99%, trace metal basis, Sigma Aldrich Chemie GmbH) and gallium(III) nitrate hydrate ([Ga(NO₃)₃·xH₂O], crystalline, 99.9% trace metals basis, Sigma Aldrich Chemie GmbH) with an atomic ratio of 85 : 15 in a mixture of solvents of deionized water : ethanol : ethane-diol with V/V ratio of 45 : 40 : 15, for 1 h to obtain a homogeneous ink formulation with molarity of 50 mM. Deionized water was added to obtain better printability of the ink and easy hydrolysis of the semiconductor film. Ethane diol was added to obtain a suitable viscosity for inkjet printing, and to obtain a homogeneous film without the coffee ring effect. The prepared ink was filtered through a 0.2 µm polyimide filter before printing.

Preparation of the Li₃PO₄ solid electrolyte ink

An inkjet printable precursor solution of lithium phosphate (Li₃PO₄) of concentration 500 mM was prepared from Li₃PO₄ powder, procured from Sigma Aldrich Chemie GmbH. Li₃PO₄ was dissolved in deionized (DI) water under continuous stirring at 1000 rpm for a duration of 2 h, at room temperature and ambient conditions. In this process, a little milky-white solution was obtained. Subsequently, diluted acetic acid (1 : 10 glacial acetic acid in DI water) was added dropwise until a completely transparent solution was achieved with a pH value of ∼5.0. Under these conditions, the Li₃PO₄ crystals are completely dissolved in DI water, and a pH of ∼5.0 also meets the inkjet printing conditions. Furthermore, the ink was filtered through a 0.2 µm polyimide filter before the printing process.

Structural and morphological characterizations

The structural characterization of the a-IGO films was carried out using a Rigaku SmartLab X-ray diffractometer with a Cu-Kα source (40 kV, 30 mA), and with a constant grazing incidence angle of 0.5°. The morphological characterizations of every individual film and the energy dispersive X-ray spectroscopy (EDX) analysis of the electrolyte film were carried out using an Ultra55 (field-emission scanning electron microscopy) FE-SEM, Karl Zeiss, with a beam voltage of 15 keV. The transmission electron microscopy (TEM) sample of the semiconductor thin film was prepared by inkjet printing of the identical ink used for device fabrication, on 30 nm free-standing Si₃N₄ membrane TEM grids (Agar Scientific), and subsequent annealing at 350 °C, for 1 h; the transmission electron microscopy of the semiconductor thin film on the Si₃N₄ membrane was carried out using TITAN Themis, operated at an accelerating voltage of 300 kV. The Super-X quad EDX detector was used for elemental mapping. The cross-section TEM sample of the device was prepared by using a scanning electron microscopy-focused Ga-ion beam (SEM-FIB) with a FEI dual beam Scios system. The X-ray photoelectron spectroscopy (XPS) data were recorded in a Thermo Scientific K-Alpha Surface Analysis instrument with X-ray spot size of 400 µm, and a Flood gun of FG03 Argon, in an ultrahigh vacuum chamber with a base pressure of 2 × 10⁻⁹ mbar, and a monochromatic Al-Kα source (1486.6 eV), with a full width half maximum of around 0.4 eV. The broad spectrum was measured with a scan range of 10 eV to 1350 eV, a step size of 1 eV, a dwell time of 10 ms, and a pass energy of 200 eV. In contrast, the high-resolution elemental spectra were recorded with a pass-energy of 50 eV, dwell time of 50 ms, and a step size of 0.1 eV. Thermogravimetric analysis (TGA) of the printed Li₃PO₄ film was performed using a TGA Q500 machine from TA Instruments. 10–15 mg of the sample was collected from the as-printed and room-temperature-dried film and placed in a ceramic crucible for the experiment. The sample was heated from room temperature to 800 °C at a heating rate of 10 °C min⁻¹ under a nitrogen atmosphere.

Rheology measurements

The TA DHR 2 (TA instruments, New Castle, DE, USA) rheometer was used to conduct rheological investigations with a 40 mm steel plate geometry with a 1° cone angle and a 1 mm gap. Throughout the measurement, the temperature of the Peltier base plate containing the precursor ink of Li₃PO₄ was maintained at 23 °C.

Device fabrication

The drive electrodes of the TFT devices were fabricated using photolithography; sputtered tin-doped indium oxide (ITO) coated high-quality float glass (∼180 nm), having a sheet resistance value of <10 Ω sq.⁻¹, was patterned using a Heidelberg UPG 501 direct writer, using a laser of 390 nm and an exposure time of 80 seconds. The patterned substrates were then sequentially cleaned with bath sonication in acetone, isopropyl alcohol, and deionized water before printing the semiconductor layer. The semiconductor ink was printed using a Dimatix 2831 desktop inkjet printer with a drop spacing (ds) of 10 µm, and 2 passes of printing, on the patterned substrate having a W : L ratio of 50 µm : 20 µm, followed by a preheating of the film at 80 °C for 15 minutes. Subsequently, the semiconductor film was further annealed at 350 °C for 1 h. Next, the solid electrolyte ink was printed (10 passes) with a drop spacing of 15 µm to ensure a large thickness of the electrolyte layer and a low leakage current in effect. The devices were then annealed at 120 °C for 2 h to ensure nucleation and growth of Li₃PO₄ crystals subsequent to the solvent evaporation. Next, a highly conducting inkjet printable organic metallic ink of PEDOT : PSS (Sigma Aldrich Chemie GmbH) was printed on top of the electrolyte layer to comprise the top gate electrode and complete the device fabrication. The depletion-load type unipolar pseudo-CMOS devices were fabricated following the above-mentioned procedure, with a W : L ratio of 50 : 20 and 20 : 50 for the load and the drive TFTs, respectively.

Electrical characterizations

The electrical characterizations of the TFTs and inverters were carried out using a semiconductor parameter analyzer (KEYSIGHT B1500A) connected to a MicroXact SPS1000-15 DC probe station, with a constant voltage scan rate of 25 mV s⁻¹. The switching stability studies of the TFTs were carried out using a Tektronix AFG1022 arbitrary function generator.

Results and discussions

It is essential to characterize all the active materials of the TFTs before an attempt to print the transistors can be made. Consequently, at first, the semiconductor material has been characterized, followed by the characterization of the novel ion-conducting and electrically insulating solid electrolyte. The X-ray diffractogram shown in Fig. 1a reveals that the semiconductor film is predominantly amorphous; however, the frequent occurrence of phase-separated In₂O₃ nanocrystals can be expected. The two broad peaks at 2θ of 21.5° and 30.5° belong to the phase-separated In₂O₃, and its volume-averaged crystallite size may be around 3–4 nm. However, such nanocrystals may be embedded in an amorphous matrix, and the overall transport may still be through the amorphous region, and hence calling the semiconductor material as a-IGO is justified.²⁰ The featureless, homogeneous, and glassy morphology of a-IGO may further be confirmed by the scanning electron micrograph of the printed semiconductor film, as shown in Fig. 1b. Next, totally corroborating the observation obtained from the X-ray diffraction data, small phase-separated In₂O₃ nanocrystals are observed in the TEM images of the printed a-IGO film, on the free-standing Si₃N₄ membrane.

Fig. 1 (a) Grazing incident X-ray diffractogram, (b) scanning electron micrograph, (c) and (d) high resolution transmission electron micrograph, and (e) selective area electron diffraction (SAED) pattern of the amorphous semiconductor layer (a-IGO); (f) grazing incident X-ray diffractogram, (g) scanning electron micrograph, and (h) atomic force micrograph, showing the huge surface roughness of the solid electrolyte (hydrated Li₃PO₄) film; X-ray photoelectron spectroscopy of the (i) O 1s peak, (j) P 2p peak, and (k) Li 1s peak of the electrolyte (Li₃PO₄) film.

What can be noted from the TEM images is that mostly the nanocrystal size stays within 2–4 nm, whereas very rarely nanocrystals ≥5 nm have been observed (Fig. 1c and d). The unusually large nanocrystal shown in Fig. 1d clearly depicts the d-spacing of the crystal planes (222) and (200), which matches the indium oxide crystal lattice. The ring pattern in the selected area electron diffraction (SAED) image in Fig. 1e, also confirms the presence of the (222) plane of In₂O₃ within the a-IGO matrix.

The grazing incident X-ray diffractogram pattern of the lithium phosphate film shown in Fig. 1f confirms the formation of the β-Li₃PO₄ phase with (010), (110), (011), and (111) planes that match with the JCPDS file number 01-074-0358.³⁵ Before ink-jet printing of the Li₃PO₄ precursor film, the rheology measurement of the ink has been carried out and has been plotted as Fig. S2. The viscosity of the ink is ∼7 cP for a range of shear rates (10–1000 s⁻¹), which falls within the range of ink-jet printing. The thermographic analysis of the as-printed Li₃PO₄ film (in Fig. S3) reveals that at 110 °C, the solvent removal (water loss) is completed, and above this temperature, slowly, the formation of P–O–P bonds at the surface of the film begins, which validates the selection of the annealing temperature (120 °C). It may also be noted that 120 °C is below the glass transition temperature of polyethylene terephthalate (PET), one of the most inexpensive and abundant polymer materials that can be used as a substrate in printed/flexible electronics. Next, the scanning electron micrograph shown in Fig. 1g depicts the morphology of the film post-evaporation of the solvent and the annealing process. The Li₃PO₄ thin film after crystallization shows a particulate structure with high surface roughness. The atomic force micrograph in Fig. 1h confirms that the film is an inhomogeneous and particulate-type structure with a very high average (R_a) and root mean square (R_RMS) surface roughness value of 56.8 nm and 66.4 nm, respectively. In order to understand the bonding present in the Li₃PO₄ thin film, X-ray photoelectron spectroscopy has been carried out. In Fig. 1i, the oxygen 1s spectrum is deconvoluted to obtain three peaks at 531.5 eV, 532.4 eV, and 533.5 eV, which correspond to symmetric bridging oxygen with phosphorous (P–O–P), the oxygen vacancy , and the hydroxyl group (–OH), respectively. The peak observed at the binding energy of 531.5 eV corresponds to the PO₄³⁻ tetrahedra. In Fig. 1j, the deconvoluted peak at 133.4 eV represents the doublets 2p_1/2 and 2p_3/2.

In Fig. 2(a–c), optical micrographs are shown, which demonstrate the stepwise fabrication process of the printed TFTs. While Fig. 2a shows the ink-jet printing of the semiconductor ink on the channel region of the pre-patterned ITO/glass substrate, Fig. 2b illustrates printing of the electrolyte ink on the annealed semiconductor layer, and Fig. 2c shows the printed polymeric top gate (PEDOT : PSS) electrode on top of the annealed electrolytic insulator layer. It has been observed that the amount of electrolyte ink or the thickness of the printed electrolyte layer determines the electrolyte crystal dimension; this is evident from the scanning electron micrograph of a large crystal >100 µm in size, which resulted from a thick drop-cast film (50 µl cm⁻²), as shown in Fig. S1. However, in the case of a printed electrolyte layer as a gate insulator, a densely packed and homogeneous electrolyte layer with small nanocrystals of the electrolyte is preferred, and this has been achieved by optimizing the printing parameters. In the case of inkjet printing, the drop spacing (ds) plays an important role in determining the film morphology, hence an optimum drop-spacing of 15 µm and interlayer delay of 15 seconds with ink deposition volume of 250 nl cm⁻² have been maintained throughout the printing process to ensure a homogeneous printed layer; this is also essential to avoid any penetration of the printed liquid metal top gate, PEDOT : PSS, within the electrolyte layer, which may cause an increase in the leakage current of the TFTs. Fig. 2d presents a schematic of the cross-section of the device, illustrating the stacked layer of each component, which has been validated by the TEM image of the cross-section of a representative device. From Fig. 2e, the thickness of the electrolytic layer has been obtained to be in the range of 2.5–2.8 µm, whereas the thickness of the semiconductor layer (a-IGO) is ∼200 nm (Fig. 2), and that of the inkjet-printed gate layer of PEDOT : PSS is ∼200 nm. Next, Fig. 2f reveals that the interface between the semiconductor and the electrolyte is highly conformal. This conformality likely arises from the nature of the printed electrolyte ink, which is initially deposited in a liquid state. During the subsequent drying process, the removal of solvent (water) facilitates the nucleation of Li₃PO₄ and the formation of a uniform solid film that closely envelops the semiconductor surface. As a result, when an electric field is applied through the gate, the field is effectively transmitted across the conformal electrolyte layer to the underlying semiconductor. Fig. 2g–k shows the EDX mapping of different elements, which indicates the presence and thickness of the electrolyte layer, semiconductor layer, and indium tin oxide (ITO) drive electrode layer beneath the semiconductor layer in the stack. The phosphorous (Fig. 2h), gallium (Fig. 2i), and indium (Fig. 2j) footprints indicate the printed hydrated Li₃PO₄-based solid electrolyte layer on top of the semiconductor (a-IGO), whereas the strong indium signal is from the bottom ITO electrode. Lastly, the tin (Sn) signal confirms the location of the ITO electrode in Fig. 2k. Here, it may also be noted that although the Li₃PO₄-based solid electrolyte is not optically transparent, the glass substrate with an array of printed TFTs shows optical transparency >80% in the visible region, as shown in Fig. S5, which is sufficient for the technology to be used in transparent electronic applications.

Fig. 2 Optical micrograph of the stepwise fabrication process of the Li₃PO₄ electrolyte gated, a-IGO based TFTs; (a) printed semiconductor (a-IGO) layer; (b) printed Li₃PO₄ electrolyte layer over the semiconductor film; (c) printed PEDOT : PSS top gate electrode over the electrolyte layer; (d) schematic showing each layer of the printed TFT; (e) high-angle annular dark field (HAADF) image of the cross section of each stack of the printed device; (f) HAADF image of the interface area showing the conformal printed layer of Li₃PO₄ on top of the printed a-IGO layer; (g) elemental mapping of all the elements present in the cross-section; (h) elemental mapping of P (showing the printed Li₃PO₄ electrolyte layer); (i) elemental mapping of Ga (showing the printed a-IGO semiconductor layer); (j) elemental map of In (showing the a-IGO layer and the sputtered ITO layer on the glass substrate); and finally (k) elemental mapping of Sn (showing the location of the sputtered ITO layer on the glass substrate).

The bottom contact top gate geometry of the printed TFTs is shown in Fig. 3a. It is to be noted that the printed Li₃PO₄ electrolyte layer is nanocrystalline and granular (refer to the SEM and AFM micrographs); the inter-particle Li⁺ ion transfer is found to be quite slow, denoted by a large drop in capacitance at a certain scan speed when the moisture content is completely eliminated by placing it inside a glove box or under high vacuum. However, a small moisture content, as low as 15–20% RH, is found to be sufficient to restore the electrolyte performance. Consequently, here it is believed that the adsorbed moisture at the surface and interface of the inter-particulate structure allows the Li⁺ ions to move freely from one crystallite to another and maintains high ionic conductivity.

Fig. 3 (a) Schematic showing the printed hydrated Li₃PO₄ electrolyte-gated TFT device; (b) the transfer curve (darker shade-I_D,ON and lighter shade-I_G) of a representative TFT device at different V_DS values, 0.5 V, 1 V, 1.5 V and 2 V; (c) the output curve of a representative TFT device at different V_GS values 0 V, 0.5 V, 1 V, 1.5 V, and 2 V; transistor performance parameters extracted from a set of printed TFTs, (d) on–off (I_D,ON : I_D,OFF) ratio and width normalized on-current density (I_D,ON/W), (e) width normalized transconductance (g_m/W) and estimated subthreshold slope, and (f) calculated threshold voltage and estimated linear mobility.

In other words, it drastically reduces the transport barrier for Li⁺ ions from one crystallite to the next. Nevertheless, under ambient conditions, the hydrated Li₃PO₄ solid electrolyte is found to offer excellent transistor characteristics, which will be discussed next. The printed TFTs are fabricated with a channel width (W) to length (L) ratio of 50 µm to 20 µm, where amorphous a-IGO has been used as the semiconducting material. a-IGO has been chosen as the active material for the printed TFTs in order to obtain a high mobility and saturation current with 85 at% of indium, and at the same time a low off-state with 15 at% of carrier suppressor gallium. On the other hand, the typical composition of the amorphous semiconductor with a substantial amount of zinc (amorphous indium gallium zinc oxide, a-IGZO) has been avoided, as zinc usually degrades the environmental stability of the semiconductor material. The operating voltage of the TFTs has been limited to ≤2 V, considering the compatibility with portable electronics applications. Fig. 3b demonstrates the double loop transfer characteristics curve of a representative TFT, recorded in ambient conditions with the presence of nominal hysteresis. The hysteresis in forward and reverse sweep from −1 V to +2 V is observed to be gradually reducing with increment of the V_DS value from 0.5 V to 2 V. The current hysteresis of the transfer curves shows a minimal hysteresis width of only 0.3 V, 0.33 V, 0.25 V, and 0.05 V at V_DS of 0.5 V, 1.0 V, 1.5 V, and 2 V, respectively, which indicates that the printed transistors have very limited interfacial trap density. The maximum on-state current (I_D,ON) of the TFT can be noted as 3.1 mA, at V_GS of 2 V (Fig. 3c). In order to provide an idea about the variability in the electrical performance of these printed TFTs, the statistics of various device performance parameters have been provided in Fig. 3d–f. The estimated parameters include on–off current ratio (I_D,ON/I_D,OFF), channel width normalized on-current (I_D,ON/W), channel width normalized transconductance (g_m/W), subthreshold slope (S), threshold voltage (V_T), and linear mobility (μ_lin). It may be noted that the TFTs exhibit excellent I_D,ON/I_D,OFF ratio as high as 3.8 × 10⁸, and a large I_D,ON/W value of 63.2 (39.12 ± 15.1) µA µm⁻¹. The average width normalized transconductance of the TFTs extracted from the transfer curves (g_m = ∂I_D/∂V_GS) has been found to be as high as 39.4 (29.9 ± 7.1) µS µm⁻¹. Due to the presence of a large concentration of Ga in the a-IGO semiconductor, the printed TFTs are found to operate as normally-off (enhancement-mode) devices with high positive threshold voltage of ∼0.6 V, and confirming an excellent semiconductor–electrolyte interface and absence of trap states, a subthreshold slope of 61 mV decade⁻¹ has been recorded, which is quite close to Boltzmann's limit at room temperature. The linear mobility values of the TFTs have been estimated using the following equation:

where C_DL is the specific electric double layer capacitance estimated from the gate current observed (23 µF cm⁻²) and (∂I_D)/(∂V_GS) is the slope of the transfer curve in the linear region of operation (V_DS = 0.5 V). The linear mobility of the representative TFT has been estimated to be 42.8 (28.9 ± 9.5) cm² V⁻¹ s⁻¹, which is generally observed in the case of In-rich oxide semiconductor systems with electrolyte gating.^20,23 Summarizing, it may very well be stated that the TFTs exhibit outstanding performance parameters, owing to the conformal growth of the Li₃PO₄ electrolyte on the semiconductor surface, as well as a conformal interface between the solid electrolyte and the polymeric gate metal layer, printed on top of the printed solid electrolyte layer (as observed in Fig. S4).

To understand the stability of the devices under ambient conditions, the devices have been kept under ambient conditions without any encapsulation and remeasured after a month. The transfer curve of the devices (Fig. 4a) demonstrates an insignificant reduction in I_D,ON from 1.1 × 10⁻³ A to 0.8 × 10⁻³ A, after a month. The I_D,ON/I_D,OFF ratio of the representative device, estimated from the transfer curves, has changed from 1.9 × 10⁶ to 3.7 × 10⁶. Next, the operational stability of the ceramic-electrolyte-gated thin-film transistors (TFTs) has been systematically evaluated, as it represents a key figure of merit for their practical applicability. Initially, the on/off switching stability (AC bias stress) has been examined through continuous switching for 1000 cycles by providing a 0.1 Hz square wave signal of V_GS = 2 V to the gate of the TFTs. The drain current has been recorded as a function of time and has been plotted as shown in Fig. 4b–e. The devices exhibit a nominal decrease in on-current during this repeated on/off switching operation, which is a typical behavior observed in the case of electrolyte-gated TFTs. During this process, the I_D,ON/I_D,OFF ratio is observed to be nominally changing from 1.8 × 10⁵ to 2 × 10⁵. To further assess the device reliability, a positive DC bias stress (PBS) test has been carried out, wherein a constant gate bias of +2 V has been applied, as shown in Fig. 4f. The transfer curves have been continuously monitored with an interval of 5 minutes to estimate the on-current I_D,ON, threshold voltage shift (V_T), and linear mobility decay (μ_lin). After biasing for 90 minutes continuously, the on-current (I_D,ON) has been estimated to be reduced to only 8.2%, whereas the threshold voltage (V_T) has increased from 0.5 V to 0.97 V, and the linear mobility value (μ_lin) has been found to reduce from 34.1 cm² V⁻¹ s⁻¹ to 19.3 cm² V⁻¹ s⁻¹ (refer to Fig. 4g–i).

Fig. 4 (a) The environmental stability of the representative TFT after 1 month under ambient conditions, without any encapsulation; (b) schematic showing the AC bias stress experiment with the applied square wave input signal to V_GS varying the amplitude from 0 V to +2 V, at 0.1 Hz, with a constant DC V_DS = 1.5 V; (c) the TFT drive current switching for 1000 cycles under the AC bias stress test; (d) drain current switching during the first 5 cycles; and (e) the drain current switching during the last 5 cycles; (f) representative transfer characteristics variation with positive gate bias stress of +2 V (the maximum operating voltage of the TFTs) at a constant V_DS of +2 V for 90 minutes with transfer curves measured at an interval of 5 minutes; (g) variation in the on-state current as a function of biasing time; (h) variation of threshold voltage as a function of biasing time; and (i) variation of linear mobility as a function of biasing time.

To further demonstrate the usability of these printed solid electrolyte-gated TFTs, depletion-load type, unipolar pseudo-CMOS inverters have been fabricated with load and drive TFTs having W/L ratio of 50 µm/20 µm and 20 µm/50 µm (as shown in Fig. 5a), respectively. This device architecture has previously been optimized in our workgroup.³⁶ The voltage transfer characteristics (VTCs) of the inverters have been studied for various supply voltage (V_DD) values from 0.5 V to 2 V, with an interval of 0.5 V. Fig. 5b demonstrates the VTC curve of the inverters with rail-to-rail output voltage and with nominal hysteresis. This ascertains the excellent switching behavior of the inverters. The signal gain (η) has been estimated using the following equation,

where, the V_OUT and V_IN are the output and input voltage, respectively. The maximum signal gain has been estimated to be 33.4 V/V at V_DD of 2 V (Fig. 5c), which is sufficient for the inverters to be used in commercial circuit design and practical applications. Furthermore, the noise margin (Fig. 5d) of the inverter, which estimates the maximum allowable DC voltage amplitude of an inessential signal that can be added to the noise-free lowest input level (0 V), without distorting the output logic voltage level, has been estimated using the following equations:

Low noise margin, N_ML = V_IL – V_OL (3)

High noise margin, N_MH = V_OH – V_IH (4)

where, input low voltage (V_IL), input high voltage (V_IH), output low voltage (V_OL), and output high voltage (V_OH).

Fig. 5 (a) Schematic showing a depletion-load type, unipolar, pseudo-CMOS inverter design; (b) voltage transfer characteristics (VTC) curve of a representative inverter measured at various V_DD values of 0.5 V, 1 V, 1.5 V and 2 V; (c) corresponding voltage gain values of the representative inverter; (d) noise margin of the inverter at V_DD of 2 V; (e) current flow through the inverter circuit at different input voltage values with various V_DD values of 0.5 V, 1 V, 1.5 V and 2 V; (f) dynamic power dissipated during the operation of the inverter at various V_DD values of 0.5 V, 1 V, 1.5 V and 2 V.

The noise margin for each supply voltage (V_DD) value has been estimated and shown in Fig. S4 and summarized in Table S1. The noise margin of the inverter is promising for higher supply voltage (>1 V), which indicates that the inverter is suitable for >1 V supply voltage values. The drive current through the inverter (I_DD) and the transient power dissipation (P = V_OUT × I_DD) during switching have been presented in Fig. 5e and f, respectively, for all the supply voltages. It may be noted that other than the supply voltage V_DD of 2 V, the power dissipation is not more than 7 nW, which increases to 26.5 nW, in the case of a 2 V supply voltage. In the case of high supply voltage, the load transistor does not switch off properly and allows larger current to flow through the inverter circuit, and results in high static current dissipation.

Conclusion

In order to demonstrate a low-temperature processed ICO, a hydrated Li₃PO₄ ion conducting oxide-based solid electrolyte has been proposed, which is well suited to inkjet printing, and owing to its low process temperature of 120 °C, it may also be compatible with flexible substrates. Even though the inkjet-printable, electronically insulating, ion-conducting oxide-based solid electrolyte possesses a huge RMS surface roughness value of 66.4 nm, the TFTs fabricated using the same as the gate insulator, with a bottom contact top gate geometry, show excellent semiconductor–electrolyte and gate–electrolyte interface, which can be validated from the absence of interfacial trap states. The absence of trap states can be concluded from hysteresis-free transfer curves and subthreshold slope values close to the Boltzmann theoretical limit. The compliant interfaces may have been achieved because of the liquid Li₃PO₄ precursor that is printed on the semiconductor layer, or the liquid organic metal PEDOT : PSS ink printed on the crystalline Li₃PO₄ layer; in either case, the liquid inks wet the solid layer underneath and provide conformal interfaces. The TFTs thus produced with the novel hydrated Li₃PO₄ electrolyte and inkjet printing technology have demonstrated an excellent combination of device performance properties that include an on/off ratio of 3.8 × 10⁸, a high current density of 63.2 µA µm⁻¹, a transconductance of 39.4 µS µm⁻¹, a maximum linear mobility of 42.8 cm² V⁻¹ s⁻¹, a subthreshold slope of 61 mV decade⁻¹, and all of these at a low operating voltage of ≤2 V. Furthermore, utilizing the printed TFTs, depletion-load type unipolar pseudo-CMOS inverters have been fabricated with excellent rail-to-switching, a signal gain of 33.4 V/V, and nominal power dissipation of 7 nW up to a supply voltage of 1.5 V. The low process temperature of the solid electrolyte, excellent TFT performance, and high optical transparency of the printed devices are believed to pave the path for new avenues towards reliable all-printed electronics for wearable and consumer electronic applications.

Conflicts of interest

The authors declare no competing interests.

Data availability

Raw data of this manuscript are available upon reasonable request made to the corresponding author.

The data supporting this article have been included as part of the supplementary information (SI). Supplementary information: scanning electron micrograph of a particular Li₃PO₄ electrolyte crystal from a drop-cast film; rheology study of the inkjet-printable Li₃PO₄ precursor ink; thermogravimetric analysis of the Li₃PO₄ film; cross-section STEM image of the thicker electrolyte-gated thin film transistor with an a-IGO semiconductor; UV-visible transmission spectra of the printed devices and the spin-coated Li₃PO₄ electrolyte film; capacitance–voltage measurement of the inkjet-printed Li₃PO₄ gated TFT with an a-IGO channel; noise margin extraction from the VTC plot; estimation of the noise margin of the inverter at various supply voltages; comparison of the performance parameter of the Li₃PO₄ gated TFTs having an a-IGO channel with existing literature. See DOI: https://doi.org/10.1039/d5tc02795k.

Acknowledgements

The authors would like to acknowledge the financial support from the Anusandhan National Research Foundation (ANRF), under the grant number CRG/2023/003983. The Centre for Nano Science and Engineering (CeNSE) at the Indian Institute of Science (IISc), Bangalore, is acknowledged for allowing access to its structural and morphological characterization facilities.

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