Recent progress in HfO₂-based ferroelectric devices with oxide semiconductor channels: a comprehensive review

Abstract

With conventional silicon-based devices approaching their physical scaling limits and traditional perovskite ferroelectrics facing complementary metal–oxide-semiconductor (CMOS) compatibility challenges, the development of alternative material integrations is essential for next-generation semiconductor systems. Among these, the synergistic integration of oxide semiconductors (OSs) with HfO₂-based ferroelectrics has emerged as a particularly promising approach, leveraging the superior interfacial properties, excellent uniformity, and compatibility with low-temperature fabrication processes inherent to OS channels. However, realizing the full potential of this technology requires a comprehensive understanding of its synergistic benefits across diverse applications and overcoming the challenges of scaling from individual devices to complex and large-scale arrays. In this review, we provide a comprehensive overview of recent progress in OS-based ferroelectric field-effect transistors (FeFETs) across five key application domains: flash memory, dynamic random-access memory (DRAM), neuromorphic computing, logic, and displays. We examine how the unique advantages of this integration address the fundamental limitations of conventional technologies in each area and conclude by discussing the remaining technical barriers and future research directions for practical implementation of the technology.

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He Young Kang

He Young Kang received the B.S. and M.S. degrees in electrical engineering from Soongsil University in South Korea, in 2013 and 2015, respectively. She is currently pursuing a PhD degree with the Department of Electronic Engineering at Hanyang University in South Korea. Her research interests include both oxide semiconductor based ferroelectric devices and the functional materials prepared by atomic layer deposition, alongside emerging thin-film transistor technologies and their applications.

Yun Ho Shin

Yun Ho Shin received a B.S. degree from Hanyang University, Seoul, South Korea, in 2023. He is currently pursuing an integrated M.S.-PhD. degree at the Department of AI Semiconductor Engineering, Hanyang University, Seoul. His current research interests include ferroelectric devices, hardware-based neuromorphic devices, and TCAD simulation for advanced logic device development.

Da Eun Kim

Da Eun Kim received a B.S. degree from the Department of Electronic Engineering at Hanyang University in South Korea. She is currently pursuing an M.S. degree in Artificial Semiconductor Engineering at Hanyang University. Her research primarily focuses on oxide semiconductor-based ferroelectric devices and thin-film engineering via atomic layer deposition and physical vapor deposition, aimed at memory semiconductor technologies and their applications.

Dae Woong Kwon

Dae Woong Kwon received a PhD degree in electrical engineering from Seoul National University (SNU), Seoul, South Korea, in 2017. From 2005 to 2014, he was a Senior Engineer with Samsung Electronics. In 2017, he was a Postdoctoral Fellow at the University of California at Berkeley, Berkeley, USA. In 2019, he was with Intel, Santa Clara, CA, USA. He is currently an Associate Professor at the Department of Electronic Engineering, Hanyang University, Seoul.

Jae Kyeong Jeong

Jae Kyeong Jeong is a professor affiliated with the Department of Electronic Engineering at Hanyang University in South Korea. He received his PhD. degree in materials science and engineering from Seoul National University, Seoul, Korea, in 2002. His research has been focused on novel devices including oxide TFTs, flexible electronics, CMOS TFTs, and NAND. He has more than 222 authored Science Citation Index (SCI) journal papers and 120 international patents. He is a member of the National Academy of Engineering of Korea and is an editorial board member for both Scientific Reports and the Journal of Information Display.

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1 Introduction

The semiconductor industry has reached a pivotal inflection point as the scaling trajectory defined by Moore's law encounters fundamental physical limits. As device dimensions approach the atomic scale, silicon-based architectures face severe bottlenecks in scalability and performance, necessitating a paradigm shift toward alternative materials and non-conventional device geometries.^1–3

These limitations are pervasive across the memory and logic landscapes: NAND flash is hampered by structural scaling and thermal budget constraints;^4–7 DRAM faces capacitor scaling hurdles that compromise retention characteristics; and logic devices are increasingly plagued by leakage currents (I_L) and stochastic variability.^8–10 Furthermore, the rise of edge computing and AI necessitates ultra-low power consumption and massive integration density-requirements that incumbent technologies struggle to satisfy.^3,11

A transformative milestone occurred in 2011, when Böscke et al. reported robust ferroelectricity in Si-doped HfO₂.¹² This discovery was particularly significant as it demonstrated that ferroelectric behaviour could be elicited in a simple binary oxide through stabilization of the non-centrosymmetric orthorhombic phase (Pca2₁),^13,14 rather than requiring complex perovskite structures. Unlike conventional perovskite ferroelectrics such as PbZr_xTi_1−xO₃ (PZT) and BaTiO₃ (BTO)-which suffer from CMOS incompatibility, lead toxicity, and critical thickness limitation (>100 nm)^12,15–19 -HfO₂-based materials offer seamless integration into existing fabrication lines. Notably, HfO₂ maintains stable ferroelectric polarizations at ultrathin scales (2.9–4.5 nm), significantly undercutting the physical limits of the perovskite system.^12,20–26 The stabilization of this metastable o-phase is governed by a sophisticated interplay of factors, including dopant selection (e.g., Zr, Al, Y, Si, and Gd),^13,27–30 electrode-induced mechanical strain (e.g., TiN, W, or Mo capping)^31,32 and the precise modulation of oxygen vacancies (V_O).³³ Rigorous thermal processing is essential to navigate crystallization kinetics, bypassing the thermodynamically stable monoclinic phase in favor of the non-centrosymmetric structure.³⁴ Despite challenges such as “wake-up” effects and polarization fatigue,^35,36 the high coercive field (0.8–2.0 MV cm⁻¹) of HfO₂-based ferroelectrics enables a wide memory window (MW) even in scaled layers.^24–26,37 These attributes position HfO₂-based ferroelectrics as the leading candidates for next-generation non-volatile memory and logic applications.

Silicon-based ferroelectric transistors have faced fundamental material constraints that would limit their practical implementation. Despite extensive optimization efforts with HfO₂-based ferroelectrics, these inherent limitations have persisted, prompting the exploration of OS channels, which could offer a potential solution to circumvent these silicon-specific constraints through fundamentally different material properties and superior interfacial characteristics.

To address these silicon channel limitations, OSs such as InGaO (IGO), InGaZnO (IGZO), and InGaSnO (IGTO), among various others, offer fundamentally different material properties that address silicon-specific constraints (Fig. 1a and b). Silicon's sp³ orbitals exhibit strong directional bonding, making carrier transport highly sensitive to bond angle variations. Grain boundaries (GBs) and structural disorder create localized trap states, limiting poly-Si to <100 cm² V⁻¹ s⁻¹ through GB scattering and charge trapping,³⁸ and a-Si to ∼1 cm² V⁻¹ s⁻¹ via hopping-dominated transport.^39,40 In contrast, OSs employ spatially spread metal ns-orbitals with an isotropic shape that enable direct orbital overlap insensitive to bond distortions—a characteristic generic to multi-cation oxides with heavy post-transition metals (n ≥ 5). This enables amorphous OSs to achieve 10–50 cm² V⁻¹ s⁻¹ mobility through band conduction without requiring crystallization.^39–44

Fig. 1 Electronic structure and device characteristic comparison between Si and OS ferroelectric channels. (a) Orbital structures in Si channels. (upper) Crystalline Si showing highly directional sp³ bonding. (lower) Amorphous-Si showing disrupted sp³ bonds sensitive to structural disorder, causing mobility degradation and increased charge trapping. (b) Orbital structures in OS-based channels. (upper) Crystalline OSs. (lower) Amorphous OSs showing spatially extended metal ns-orbitals with isotropic symmetry, enabling high carrier mobility even in the amorphous state. (c) Schematic comparison between poly-Si channel and IGZO channel FeFETs. (d) Cross-sectional TEM images of the IGZO-based FeFET with no IL between IGZO and HZO.¹³ Reproduced with permission from Mo et al., IEEE J. Electron Devices Soc. 8, 717 (2020). Copyright 2020 IEEE.

Regarding interfacial characteristics, silicon channels form SiO_x interfacial layers (ILs) during HfO₂ integration, causing voltage loss and retention degradation.⁴⁵ OSs, by contrast, exhibit negligible low-k IL formation with HfO₂-based ferroelectrics, minimizing voltage loss and preserving ferroelectric properties.⁴⁶ Furthermore, OS channels—particularly in the amorphous state—demonstrate superior large-area uniformity without poly-Si GB variability, while their low-temperature processing (200–400 °C) enables back-end-of-line (BEOL)-compatible monolithic 3D (M3D) integration compared to poly-Si (>600 °C).^47–50 OSs can be deposited through various methods including sputtering and atomic layer deposition (ALD), with tunable electrical properties achieved through composition control.^51,52

These characteristics—including extremely low off-current (I_OFF) (<10⁻¹² A µm⁻¹), large-area uniformity, and low-temperature compatibility—make OSs particularly suitable for HfO₂-based ferroelectric devices where CMOS compatibility, 3D integration, and scalability are critical requirements.^47–50 The inherent composition tunability of OSs also offers potential for application-specific optimization, as the diverse requirements across NAND, DRAM, logic, neuromorphic, and display applications may benefit from different material properties.

The combination of OSs and HfO₂-based ferroelectrics offers pathways to address fundamental limitations of Si-based channels and conventional ferroelectric integration. While silicon channels suffer from IL formation and processing constraints that compromise device performance, OSs exhibit negligible IL formation with HfO₂-based ferroelectrics, leading to improved retention properties (Fig. 1c and d).^46,53 This integration enables low-power operation through the extremely low I_OFF of OS channels and negligible ILs that minimize voltage losses, as well as non-volatile characteristics that eliminate standby power consumption.

OS based FeFETs have been explored for diverse applications, with their potential for high-density 3D integration attracting significant attention. The emergence of advanced architectures, such as those for 3D vertical NAND (V-NAND) (Fig. 2a), stacked DRAM (Fig. 2b), and neuromorphic systems (Fig. 2c), underscores the critical need to understand the unique advantages of this integrated technology. Despite a wealth of literature dedicated to HfO₂-based ferroelectrics and OSs independently,^{14,41,43,44,54–60} a significant knowledge gap persists regarding their combined implementation in FeFET technology. Given the rapid advancements in OSs as silicon channel alternatives,^61–65 a comprehensive review of OS-HfO₂ FeFET integration is timely and essential.⁶⁶ This work addresses this gap through systematic analysis across five key applications: NAND flash memory (Section 2.1), DRAM (Section 2.2), neuromorphic computing (Section 2.3), logic and computing applications (Section 2.4), and display technologies (Section 2.5). For each application, we provide quantitative performance comparison highlighting OS advantages over silicon-based devices, evaluate current progress against system-level integration requirements, and identify critical challenges for practical realization. Finally, in Section 3 (Perspectives and Future Directions), we discuss interface reliability mechanisms, channel engineering approaches, and material optimization directions for advancing of OS-FeFET technology.

Fig. 2 Device schematics of (a) 3D Fe VNAND, (b) 3D Fe DRAM, and (c) FeFET-based neuromorphic computing architecture.

2 Key applications of OS-FeFETs

2.1 NAND flash memory

Conventional floating-gate-based NAND technology has faced cell-to-cell interference due to increased parasitic capacitance^4,67,68 and increased I_L that resulted from reduced tunnel oxide thickness in sub-20 nm scaling.⁵ Moreover, the polysilicon channels in 3D NAND have exhibited limitations including electrical characteristic non-uniformity due to grain boundaries⁷ and requirements for high processing temperatures exceeding 900 °C.^6,69 Additionally, currently commercialized Quad-Level Cell (QLC) NAND requires four distinguishable threshold voltage states for 4-bit-per-cell storage, which necessitates sufficient MW and precise programming control.⁷⁰

OS-based FeFETs have gained considerable attention as promising next-generation memory technologies that can provide pathways to overcome these bottlenecks. OS channels offer critical advantages for NAND application. While Si channels suffer from IL formation that would compromise retention characteristics, negligible IL formation with HfO₂-based ferroelectrics in OS channels improves retention characteristics.⁴⁶ Furthermore, the IL-free structure, combined with the inherent uniformity of OS channels-arising from the isotropic nature of metal ns-orbitals-contribute to uniform device performance across large arrays.^41,71 While poly-Si FeFETs have demonstrated gate all around (GAA) configurations in 3D ferroelectric NAND (FeNAND) structures, they suffer from high operating voltages and severely limited endurance (>10² cycles).⁷² In contrast, OS-based FeFETs achieve significantly lower operating voltages with endurance exceeding 10⁴–10⁸ cycles (Table 1). Consequently, OS-FeFETs have demonstrated not only low-voltage and high-speed operation but also endurance exceeding 10⁸ cycles and scalability down to sub-10 nm nodes.

Table 1 Summary of device performance for OS-based ferroelectric NAND reported in the literature

Key feature	OS (deposition method)	Structure	MW (V)	P/E voltage (V)	Endurance	Retention	Ref.
a Linear extrapolation.b Current constant method.
Back gate control	IGZO (sputter)	MFS	0.5	2.5/−3	>10^8 (capacitor)	1 year (capacitor)	13
Vertical structure	IZO (ALD)	MFS	2.5^a	5/−5	>10^8	N/A	79
Double gate structure	IGZO (sputter)	MIFSIM	5^b	8/−8	>10^4	N/A	75
SCM and CDE	IZO (ALD)	MINFIS(IM)	14.3	20/−18	>10^4	10 years (ext.)	76
O-deficient and GIL	IGZO (sputter)	MIFS	17.8	11/−15	>10^4	>10^3 s	77
Separated write/read	Al:IZTO (sputter)	MFS	10	8	>10^8	>10^5 s	78
Gate stack engineering	Poly Si	GAA-MIFIS	13.2	19/−14	>10^2	10 years (ext.)	72

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Despite their potential, early demonstrations of OS-FETs were hampered by a limited MW of ∼0.5 V, uncovering fundamental challenges intrinsic to their operation.⁴⁶ Because OSs are predominantly n-type with a negligible concentration of minority holes,⁴³ erase operations-which typically necessitate polarization switching via hole accumulation-are fundamentally constrained. This scarcity of holes, exacerbated by the floating body effect, results in incomplete polarization erasure, thereby capping the overall device performance. While floating body phenomena limit the MW, substrate potential control using back gates was proposed to enable proper operation (Fig. 3a).⁴⁶ To address the erase operation limitations originating from insufficient hole carriers in n-type OSs, the insertion of a p-type CuO_x layer between the n-type channel and ferroelectric HZO was demonstrated to supply hole carriers, achieving a 4 V MW through enhanced polarization switching.⁷³ In addition, various structural approaches have been proposed to address these fundamental issues. Technology computer-aided design (TCAD) simulations comparing single-gate and double-gate configurations in both 2D and 3D structures demonstrated that the double-gate structure could effectively mitigate floating body effects and enable improved MW (Fig. 3b).⁷⁴ Subsequently, experimental demonstrations of the dual-gate structure confirmed enhanced performance through separated read/write operations (Fig. 3c).⁷⁵

Fig. 3 (a) Simulated I_d–V_g and I_g–V_g characteristics of the IGZO FeFET with and without a top gate. Measured I_d–V_g and I_g–V_g characteristics of the IGZO FeFET with a top gate. Polarization switching in the IGZO channel is confirmed by the displacement current peaks in I_g.⁴⁶ Reproduced with permission from Mo et al., IEEE J. Electron Devices Soc. 8, 717 (2020). Copyright 2020 IEEE. (b) Comparison of TCAD simulated ferroelectric polarization charge and electrostatic potential for double gate planar and single gate planar FeFETs.⁷⁴ Reproduced with permission from Mo et al., Jpn. J. Appl. Phys. 61, SC1013 (2022). Copyright 2022 The Japan Society of Applied Physics. (c) I_d–V_g characteristic comparison between bottom-gate and top-gate operation and an extracted MW of 2.5 V (BG) and 5 V (TG).⁷⁵ Reproduced with permission from Jeong et al., IEEE Electron Device Lett. 44, 749 (2023). Copyright 2023 IEEE. (d) Gate stack schematic of the proposed FeNAND cell with an SCM structure. I_d–V_g characteristics for different SCM overlap margins (0, 50, and 100%).⁷⁶ Reproduced with permission from Joh et al., 2024 IEEE Int. Electron Devices Meet. (IEDM), 1 (2024). Copyright 2024 IEEE. (e) Schematic illustration of full-loop switching enabled by the intermediate oxygen-deficient IGZO layer. I_d–V_g characteristics of the device with a 3 nm GIL⁷⁷ Reproduced with permission from Yoo et al., IEEE Symp. VLSI Technol. Circuits, 1 (2024). (f) Schematic of a nanoscale vertical FeTFT array and I_BL–V_WL transfer characteristics showing ferroelectric hysteresis. V_WL was swept on the selected WL electrode while V_PASS = 2 V was applied to unselected WL electrodes.⁸⁰ Reproduced with permission from Kim et al., Appl. Phys. Lett. 121, 042901 (2022). Copyright 2022 AIP Publishing.

A device combining Source-tied Covering Metal (SCM) with Control Dielectric (CDE) achieved a 14.3 V MW (Fig. 3d).⁷⁶ Notably, the grounded SCM promotes hole accumulation during erase operations, whereas CDE extended the MW through voltage distribution during read operations, with retention remaining 11.5 V after 10 years. Furthermore, Samsung's research demonstrated a 17.8 V MW through gate stack and channel engineering (Fig. 3e).⁷⁷ This advancement incorporated an oxygen-deficient intermediate channel that enabled full-loop polarization switching and a gate interlayer (GIL) that enhanced the MW. With a sub-12 nm gate stack thickness and an operation voltage below 15 V, the device enabled high-density, low-power NAND applications. Moreover, a dual-port FeFET with Al-doped IZTO channels and separated write/read gates achieved a 10 V MW through a double-gate switching operation.⁷⁸ As a result, this approach enabled stable QLC programming and achieved negligible disturbance, which satisfied the core requirements for commercial NAND applications.

Beyond individual device optimization, ensuring reliable operation in large-scale 3D arrays represented a critical challenge for practical implementation. The feasibility of 3D FeNAND was investigated by demonstrating vertical FeFETs at the string level, with TCAD simulations confirming the viability of the 3D architecture (Fig. 3f).⁷⁹ Further progress was achieved by scaling the vertical FeFET gate length to 10 nm and demonstrating its string-level characteristics, with simulations confirming the viability of a 200-stack FeNAND structure.⁸⁰ Subsequently, recent systematic analysis demonstrated that disturb-free program operation can be achieved through optimized pass voltage below 2 V in both 2D and 3D arrays, with a SiO₂ interlayer thickness above 40 nm enabling interference-free operation in 3D configurations.⁸¹

A MW of up to 17.8 V has been achieved through various structural approaches, including dual-gate structures, SCM designs, dual-port configurations, and channel engineering (Table 1). These advances successfully addressed the fundamental challenges of the erase operation and enabled QLC programming with a disturb-free operation. However, the critical challenge lies in transitioning from optimized individual devices to reliable high-density 3D array architectures that can compete with commercial NAND requirements exceeding 200 layers. Poly-Si FeFETs have already achieved GAA configurations in 3D FeNAND structures but suffer from high operating voltages and severely limited endurance (>10² cycles). OS-based FeFETs have addressed voltage and endurance limitations through low-voltage operation with 10⁴–10⁸ cycle endurance, while inherent wide bandgap properties provide ultra-low I_L (<10⁻¹² A µm⁻¹). However, substantial challenges remain in experimental demonstration of vertical GAA architectures, validation of disturb-free operation in high-density multi-string arrays, and systematic characterization of device-to-device variability across large-area substrates for practical implementation.

2.2 DRAM

Conventional one-transistor-one-capacitor (1T1C) DRAM has faced two critical challenges: capacitor scaling limitations and refresh power consumption. As the capacitor thickness approached ∼5 nm, the capacitance reduction from 20 fF to 8 fF degraded the retention and sensing margins.^{8–10,82–84} Additionally, the 64 ms retention time required frequent refresh operations that dominated power consumption.^82,84 Two-transistor capacitor-less (2T0C) DRAM, which eliminated the capacitor and stores charge directly in the channel region, emerged to address capacitor scaling. This architecture achieved 4F² area efficiency and dramatically extended retention (400–1000 s) compared to 64 ms.^85–87 In 2T0C, the write transistor (Wtr) needs ultra-low I_OFF to suppress I_L during retention, while the read transistor (Rtr) needs high I_ON for adequate sensing margin. Table 2 summarizes how OSs provide ultra-low I_OFF and Si provides high on current (I_ON) for these respective roles. Heterogeneous approaches (Si–MoS₂⁸⁸ and IGZO-Si⁸⁹) extended retention to 4800–6000 s. Ferroelectric integration with OSs can employ permanent polarization states to overcome retention limitations, demonstrating refresh-free DRAM.

Table 2 Summary of device performance for OS-based DRAM and FeDRAM reported in the literature

Device architecture	OS (deposition method)		Area per transistor	MW (V)	Rtr ION (µA µm^−1)	Retention	Ref.
	Wtr	Rtr
a Non-FeFET device
Planar 2T0C DRAM	IGZO (sputter)		Planar	^a	∼10 (VDS = 0.8 V)	∼1000 s	85 and 86
Vertical 2T0C DRAM	IGZO (ALD)		4F^2	^a	30 (VDS = 1 V)	300 s	87
2T0C FeDRAM (simulation)	IGZO		4F^2	1.76	∼1 (−)	N/A	90
2T0C FeDRAM (experimental)	a-ITZO (sputter)	a-ITZO/a-IGZO (sputter)	Planar	1.5	∼1 (VDS = 0.1 V)	>2000 s	91
2T-eDRAM	Si	MoS2 (CVD)	Planar	^a	165.97 (VDS = 3 V)	∼6000 s	88
2T0C DRAM	a-IGZO (sputter)	Si	Vertical (3D)	^a	∼1.19 (VDS = 1 V)	∼4800 s	89

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Ferroelectric integration, which transformed 2T0C into non-volatile 2T0C ferroelectric DRAM (FeDRAM), directly addressed this remaining limitation. The ferroelectric layer enabled permanent polarization states that removed the need for refresh operation. Furthermore, OS-based channels, which provided extremely low I_L and superior HfO₂ interfacial properties, were particularly suited for this integration, enabling stable non-volatile switching. Consequently, this integration approach addressed both original challenges: where capacitor scaling was addressed through structural elimination, and refresh power was removed through non-volatile operation.

Stackable vertical channel-all-around (CAA) structure IGZO FeFETs were investigated through TCAD simulations, which addressed array-level operation challenges.⁹⁰ The study demonstrated a 10⁷ on/off ratio (I_ON/OFF), and the proposed methodology resolved current-sharing issues (Fig. 4a). Moreover, the optimized operation achieved current ratios exceeding 10⁵ between the data states while preventing readout interference (Fig. 4b).

Fig. 4 (a) Schematic of stacked 2T0C memory with CAA-IGZO FeFETs and cross sectional view of the Rtr with ferroelectric HfO₂ (b) Simulated I_d–V_g characteristics comparing IGZO-based FeFETs (red) and conventional IGZO FET (black dashed). Selective readout of RWL1 with an ultra-high current ratio (>10⁵) between data “1” and data “0”. Unselected cells (RWL2) remain locked, preventing readout interference.⁹⁰ Reproduced with permission from Liang et al., Jpn. J. Appl. Phys. 63, 06SP05 (2024). Copyright 2024 The Japan Society of Applied Physics. (c) Schematic comparison of read/write operations in conventional 2T0C DRAM and proposed 2T0C FeDRAM, highlighting programmable V_TH (V_SN = 0 V operation), non-overlapping I_RBL for multi-bit storage, and enhanced stress stability. (d) I_d–V_g characteristics of the Rtr showing >10⁶ current MW at V_read = 0 V. Retention characteristics demonstrate stable 19-level memory states over 2000 s.⁹¹ Reproduced with permission from Noh et al., Nanoscale 16, 16576 (2024). Copyright 2024 Royal Society of Chemistry.

Subsequently, the first operational 2T0C FeDRAM using a-ITZO FET and a-ITZO/a-IGZO FeFET was demonstrated.⁹¹ The device achieved a 1.5 V MW with 10⁴ s retention (Fig. 4c). Notably, the Rtr exhibited >10⁶ I_ON/OFF with a stable 19-level multi-bit operation (Fig. 4d), with a 11.5 V MW retention extrapolated after 10 years.

The evolution from 1T1C DRAM to 2T0C addressed capacitor scaling through structural elimination, achieving a 4F² area efficiency and extended retention (400–1000 s). Ferroelectric integration further removes the refresh power requirements through non-volatile operation. The demonstrated 2T0C-FeDRAM achieved a 1.5 V MW with 10⁴ s retention, >10⁶ I_ON/OFF, and 19-level multi-bit operation with 11.5 V retention extrapolated after 10 years (Table 2). The 2T0C architecture requires ultra-low I_OFF for the Wtr to minimize I_L and high I_ON for the Rtr to ensure the sensing margin—properties naturally provided by OSs and Si, respectively (Table 2). Heterogeneous approaches (Si–MoS₂ and IGZO-Si) combined these complementary characteristics, utilizing OSs for low-leakage retention and Si for high-current sensing, achieving 4800–6000 s retention. Ferroelectric integration with OS channels addressed volatility through permanent polarization, demonstrating a 1.5 V MW with 10⁴ s retention, >10⁶ I_ON/OFF, and 19-level multi-bit operation. However, demonstrations remain at the discrete device level. Progression to array-level feasibility faces critical challenges: current-sharing issues degrade read margins, cross-talk affects multi-cell operations, and the fundamental retention-write speed trade-off—where extended retention requires slower polarization switching—complicates optimization. Validating extrapolated 10-year retention in integrated arrays under realistic conditions remains essential, with cell area versus leakage management becoming increasingly critical at scaled dimensions.

2.3 Neuromorphic computing systems

FeFETs exploit HfO₂ polarization to modulate channel conductance, yet poly-Si FeFETs suffer from interface-related instabilities that compromise synaptic precision. In contrast, OS-based FeTFTs provide stable interfaces that enable reliable analog weight updates crucial for neuromorphic learning.⁴⁶ As summarized in Table 3, poly-Si FeFETs exhibit a limited conductance dynamic range (G_max/G_min ≈ 10) and restricted weight resolution (5-bit), indicating a fundamental trade-off between programming speed and analog controllability.⁹²

Table 3 Summary of device performance for OS-based FeFETs for neuromorphic computing reported in the literature

OS (deposition method)	Structure	Gmax/Gmin	Conductance levels	Accuracy	Pulse width	Read bias	Ref.
IZTO (sputter)	MFS	11	64	93.1% (MNIST)	100 µs	VDS = 0.1 V	96
IGZO (sputter)	MFS	>10	64	91.1% (MNIST)	50 ms	VDS = 0.1 V	98
IGZO (sputter)	MFMIS	∼53.2	>70	∼97% (MNIST)	100 µs	VDS = 1.0 V	100
IGZO (T-ALD)	MFMIS	∼183	N/A	> 90% (CIFAR-10)	10 µs	VDS = 0.1 V	101
IGZO (sputter)	MFMIS	∼1400	256 (8-bit)	96.6% (MNIST)	100 µs	VDS = 0.1 V	97
Poly-Si (LPCVD)	MFS	9.96	32 (5-bit)	N/A	150 ns	VDS = 0.1 V	92

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For neuromorphic applications, critical synaptic functionalities are enabled by OS-based FeFETs: analog weight modulation through partial polarization switching and stable multi-level conductance states essential for neural network operations.^93–96 In contrast, OS-based FeTFTs demonstrate significantly expanded conductance windows (G_max/G_min: ∼50–1400) and enhanced conductance levels exceeding 70 states with up to 8-bit precision.⁹⁷ Partial polarization switching generates multiple intermediate states, enabling multi-level conductance modulation (Fig. 5a).⁹⁸ This property extends beyond binary memory operation, establishing itself as an analog synaptic device capable of continuous weight modulation, a fundamental requirement for neuromorphic computing. The metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure introduces an insulating layer and floating metal between the ferroelectric and channel, suppressing interfacial reactions and enabling optimized capacitance matching.^59,99 The MFMIS structure enabled enhanced performance in synaptic applications. The device stack consisting of an IGZO channel, ZrO₂ insulating layer, Mo electrode, and HZO ferroelectric layer ensures efficient coupling of ferroelectric polarization while minimizing interface trap effects (Fig. 5b).^100,101 Low nonlinearity (α ≈ 0.21), wide G_max/G_min (≈53.2), and highly stable updates with a cycle-to-cycle variation of only ∼0.47% were achieved.¹⁰¹ Crucially, precise analog weight modulation enabled by the MFMIS structure realized a robust analog reservoir computing system, achieving high performance in tasks such as temporal data prediction.¹⁰⁰ This capability is further supported by retention measurements, which demonstrate that multiple programmed states remain stable for over 10³ s (Fig. 5c),¹⁰⁰ confirming that the MFMIS FeTFT is well-suited for long-term analog weight storage in neuromorphic systems.

Fig. 5 (a) Schematic of ferroelectric polarization states (erased, programmed, and intermediate states) and corresponding transfer curves demonstrating multiple intermediate conductance levels.⁹⁸ Reproduced with permission from Kim and Lee, Nano Lett. 19, 2044 (2019). Copyright 2019 American Chemical Society. (b) Three-dimensional device structure and cross-sectional schematic of the MFMIS FeTFT showing the IGZO channel, ZrO₂ interlayer oxide, TiN inner metal, HZO ferroelectric layer, and Mo gate electrode.¹⁰¹ Reproduced with permission from Kwon et al., Adv. Intell. Syst. 5, 2300125 (2023). Copyright 2023 Wiley-VCH GmbH. (c) LTP and LTD characteristics, conductance modulation stability over 20 cycles, and retention measurements showing multi-level state stability over >10³ s.¹⁰⁰ Reproduced with permission from Kim et al., Nat. Commun. 15, 9147 (2024). Copyright 2024 Springer Nature. (d) Biasing schemes for selective weight update and read operations with inhibit voltage control, and schematic of VMM operation demonstrating programmed and erased cell states for neuromorphic computing. (e) Optical microscope image of the fabricated 3D FeTFT array, three-dimensional schematic of vertically stacked layers, and equivalent circuit diagram showing WL, BL, and SL interconnections.¹⁰³ Reproduced with permission from Kim et al., Nat. Commun. 14, 504 (2023). Copyright 2023 Springer Nature.

FeTFT synaptic arrays enable vector-matrix multiplication (VMM) operations, which are fundamental computations for neural networks.¹⁰² By applying input voltages to the word lines and bit lines and summing the output currents along the source lines, parallel in-memory computation can be achieved (Fig. 5d). Inhibit voltages were applied to unselected cells to suppress unwanted polarization switching, thereby enabling precise cell-level control. The biasing scheme demonstrated that the targeted cells exhibited conductance modulation, whereas the non-selected cells remained unchanged.

3D stacked FeTFT arrays, which address area limitations and sneak-path current issues, have emerged as an essential approach for overcoming the constraints of conventional 2D planar architecture.¹⁰³ The structural configurations are composed of TiN, HZO, InZnO (IZO), and Mo layers forming vertically stacked FeTFT cells with independent access (Fig. 5e). A six-layer stacked array has been reported to reach ∼93.1% accuracy on Modified National Institute of Standards and Technology (MNIST) digit classification, closely approaching software-level performance.¹⁰³ Moreover, hafnia-based FeFET arrays have demonstrated >90% accuracy on CIFAR-10 image classification,¹⁰⁴ evidencing that 3D stacking not only enhances integration density but also provides practical feasibility for deep-learning inference. An endurance exceeding 10⁶ cycles and retention over 10⁴ s have been confirmed, underscoring the reliability required for large-scale neuromorphic hardware.

Table 3 compares the reported performance. Poly-Si FeFETs exhibit limited G_max/G_min (≈10) and restricted weight resolution (5-bit), indicating a fundamental trade-off between programming speed and analog controllability. In contrast, OS-based FeTFTs demonstrate significantly expanded G_max/G_min (∼50–1400) and enhanced conductance levels exceeding 70 states with up to 8-bit precision. OS-FeFET synaptic devices achieved precise analog weight modulation (nonlinearity α ≈ 0.21, G_max/G_min (≈53.2) and demonstrated functionality in 3D stacked arrays with vector-matrix multiplication operations, achieving >90% accuracy on MNIST and CIFAR-10 benchmarks. Six-layer stacked arrays have achieved ∼93.1% MNIST accuracy approaching software performance.

However, scaling to large-scale systems faces critical challenges. Device-to-device and cycle-to-cycle variation impact weight accuracy in arrays, while the fundamental trade-off between analog weight precision and programming endurance—where higher-resolution multi-level states exhibit reduced cycling stability—complicates optimization. Further scaling beyond current 6-layer demonstrations would encounter wire resistance and cross-talk challenges, while endurance limitations (10⁴–10⁶ cycles) constrain on-chip learning operations that require frequent weight updates. Long-term retention validation beyond 10³ s and balancing weight retention versus update speed for learning remain essential. As neuromorphic hardware remains pre-commercial, system-level development including peripheral circuits, power management, and manufacturing scalability is required for practical deployment.

2.4 Logic and in-memory computing applications

2.4.1 Content-addressable memory (CAM). Traditional static random-access memory (SRAM)-based CAM has fundamental limitations in area and power efficiency with a 16-transistor structure and standby power consumption.¹⁰⁵ Si-based TCAM implementations exhibit restricted I_ON/OFF (∼10⁴) due to a narrow bandgap (1.12 eV); furthermore, poly-Si variants are hindered by high-temperature processing requirements and poor uniformity (Table 4).^106–108 In contrast, FeFET-based approaches offer significant area reduction and lower operation power compared to SRAM.^{105,106,109,110} Combined with OS channels, which enable precise content matching through consistent switching behaviour, ferroelectric non-volatility allows architectural simplification from 16T SRAM to 1FeTFT-1T structures while achieving extremely low standby power.¹¹¹

Table 4 Summary of device performance for OS-based FeFETs for logic applications reported in the literature

Application	OS (deposition method)	Structure	MW (V)	Endurance (cycles)	Retention	ION/IOFF	Ref.
TCAM	Al:IZTO (sputter)	MFMIS	3.2	10^6	10^5 s	∼10^5	106
TCAM	IGZO (sputter)	MFMIS	2.9	>10^8	10 years (ext.)	∼10^8	107
CECAM	IGZO (ALD)	MFMIS	2.2	10^4	10^4 s	∼10^6	113
TCAM	Si	MFIS	1.1	N/A	N/A	∼10^4	108
M3D	IGZO (sputter)	MFS	1.7	>10^6	10^4 s	>10^5	116
M3D	ITO-IGZO (sputter)	MFS	2	>10^7	10 years (ext.)	∼10^6	117 and 118
M3D	In2O3 (ALD)	Vertical MFS	1.88	>10^12	10 years (ext.)	∼10^7	120
M3D	Poly-Si	MFMIS	2.5	∼10^6	10^5 s	∼10^4	114

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BEOL-compatible TCAM using the MFMIS structure achieved a 2.9 V MW with a 40 nm channel length, 10⁸ cycle endurance and 8 orders I_ON/OFF, enabling a larger sensing margin than conventional designs, with 90.4% handwritten digit recognition accuracy in artificial intelligence (AI) applications (Fig. 6a).^107,112 Focused microwave annealing (FMA) based processing at 250 °C enabled BEOL-compatible M3D integration with 2P_r 22.5 µC cm⁻² and 10⁸ cycle endurance, achieving high density using single transistor area compared to 12T silicon TCAM (Fig. 6b).¹⁰⁶ Combinatorial encoding CAM (CECAM), which addressed limitations of bit-by-bit storage through combinatorial encoding, achieved 0.75 bit/switch content density with 65% power reduction using the 12-IGZO based FeFET structure storing 9-bit words (Fig. 6c).¹¹³

Fig. 6 (a) Schematic comparison of conventional 16-transistor CMOS-based TCAM and two-FeFET TCAM, with sensing margin comparison showing superior performance at reduced word length.¹⁰⁷ Reproduced with permission from Sun et al., IEEE Trans. Electron Devices 69, 5262 (2022). Copyright 2022 IEEE. (b) SEM images of FMA-processed multilayer FeTFT integration (1st, 2nd, and 3rd layer FeTFTs) and 3D schematic with cross-sectional TEM images showing vertical M3D integration.¹⁰⁶ Reproduced with permission from Joh et al., ACS Appl. Mater. Interfaces 15, 51339 (2023). Copyright 2023 American Chemical Society. (c) CECAM access method schematic demonstrating input/output operations and matching current versus search content for 6-FeFET CECAM.¹¹³ Reproduced with permission from Nguyen et al., ACS Appl. Electron. Mater. 7, 2404 (2025). Copyright 2025 American Chemical Society. (d) Schematic of heat distribution in multi-layer devices through laser annealing.¹¹⁶ Reproduced with permission from Kim et al., Adv. Sci. 11, 2401250 (2024). Copyright 2024 Wiley-VCH GmbH. (e) Schematic of the double-gated FeFET structure with memory and logic switching capability, and I_d–V_g characteristics for comparing top-gated ITO-IGZO and IGZO FeFETs.¹¹⁸ Reproduced with permission from Chen et al., IEEE Trans. Electron Devices 70, 2098 (2023). Copyright 2023 IEEE. (f) 3D schematic of the vertical all-oxide FeFET showing a detailed layer structure including link regions with varying electrostatic control, and bi-directional I_d–V_g characteristics demonstrating a 1.85 V MW at V_DS = 0.2 V.¹¹⁹ Reproduced with permission from Lin et al., IEEE Trans. Electron Devices 71, 7984 (2024). Copyright 2024 IEEE.

2.4.2 Monolithic 3D integration. Poly-Si requires high-temperature processing (600–1000 °C) for dopant activation and defect annealing, exceeding BEOL thermal limits (<400 °C). Laser annealing enables sub-500 °C processing but yields limited I_ON/OFF (∼10⁴) with increasing multi-layer complexity (Table 4).¹¹⁴ In contrast, OS channels enable BEOL-compatible M3D through low-temperature processing (<400 °C) while maintaining performance.¹¹⁵ Nanosecond pulsed laser annealing enabled selective crystallization of HZO-IGZO while maintaining the bottom layer temperature below 250 °C, achieving >10⁶ cycles of endurance, a retention over 10⁶ s, and a >10⁵ I_ON/OFF ratio (Fig. 6d).¹¹⁶ ITO-IGZO heterojunction FeFETs utilizing channel defect self-compensation, which passivated interface/bulk defects, achieved enhanced performance through low thermal budget processing at 380 °C (Fig. 6e).^117,118 The top-gated and double-gated structures were enabled with 68 mV dec⁻¹ subthreshold swing, endurance exceeding 10⁷ cycles, retention longer than 10 years, and an I_ON/OFF ratio of ∼10⁷, demonstrating BEOL compatibility for non-volatile logic integration in M3D architectures. Vertical all-oxide FeTFTs using degenerated In₂O₃ for both gate and source/drain electrodes demonstrated metallization-free processing over 400 °C at 1.88 V with 10¹² cycle endurance, 10-year retention, and I_ON/OFF above 10⁷ (Fig. 6f).¹¹⁹ The M3D-FACT architecture with a three-layer structure comprising Si CMOS control logic, analog resistive RAM (RRAM)-based compute-in-memory (CIM) units, and a IGZO FeTFT-based reconfigurable datapath achieved a 15F² cell area, representing a 40× area reduction compared to the 7 nm SRAM.¹²⁰ CNN benchmarks demonstrated an energy efficiency improvement of 6.9× for VGG-8, 19.2× for DenseNet-121, and 9.9× for ResNet-18 compared to conventional structures.

Si-based TCAM shows low I_ON/OFF (∼10⁴) from a narrow bandgap, while poly-Si additionally requires high-temperature processing (600–1000 °C) exceeding BEOL limits, with laser annealing achieving sub-500 °C but maintaining limited I_ON/OFF (∼10⁴). In contrast, OS-FeFETs have demonstrated architectural simplification in CAM applications, achieving an area reduction from 16T SRAM to 1FeTFT-1T structures with 0.75 bit/switch content density. OS-based devices achieve high I_ON/OFF (10⁵–10⁸) compared to Si devices (∼10⁴) with a demonstrated endurance up to 10⁸ cycles (Table 4). For M3D integration, various approaches, including low-temperature processing (250–380 °C), heterojunction channel engineering, and vertical all-oxide structures, have enabled BEOL compatibility, with system-level demonstrations achieving 6.9–19.2× energy efficiency improvement in CNN benchmarks. However, scaling from laboratory demonstrations to practical implementation faces critical challenges. The primary trade-off in M3D integration involves the number of stacked tiers versus cumulative thermal budget, where repeated thermal cycles can degrade bottom layer performance even within nominal BEOL limits. CAM operation in large arrays requires validation of content matching reliability, search power consumption, and false match rates beyond current small-scale demonstrations. Key challenges include balancing search speed versus power consumption in CAM operations and achieving device uniformity across multiple functional layers in manufacturable heterogeneous stacking processes. System-level integration of peripheral circuits remains essential for practical implementation.

2.5 Display backplane applications

Display applications uniquely benefit from OS channels being the industry-standard backplane material, with IGZO widely adopted for superior uniformity and low-temperature processing. Display thin film transistors (TFTs) require compensation circuits to address pixel-to-pixel variations and degradation. OS-FeTFTs offer circuit simplification opportunities through ferroelectric non-volatility and programmable threshold voltage control.

A programmable ferroelectric approach to compensate for the positive threshold voltage (V_TH) shift in display driver TFTs was developed by integrating ferroelectric films in the gate stack.¹²¹ Display-compatible heat treatment at 350 °C for 1 h simultaneously crystallized the HZO film and annealed IGZO defects and contacts, with intermediate states showing a 20% polarization loss extrapolated for 10 years (Fig. 7a). This approach was advanced to reduce the V_TH variation from 0.21 to 0.01 V (Fig. 7b).¹²² The programmable compensation enabled the recalibration of degradation-induced V_TH shifts during operation, with organic light-emitting diode (OLED) integration demonstrated. Additionally, programmable light intensity control for micro-LEDs has been demonstrated using a-ITZO FeTFTs, achieving 3 V MW and multi-level lighting through partial polarization switching.¹²³ This approach enables Mura-free operation by compensating for light output variations, with the retention exceeding 100 s and an endurance of 10⁸ cycles (Fig. 7c). The FeTFT-based active-matrix circuit simplifies conventional designs by removing the need for compensation capacitors while enabling dynamic V_TH adjustment. Low-temperature IGZO FeTFT processing on polyimide/polydimethylsiloxane (PI/PDMS) substrates has been demonstrated.¹²⁴ The non-volatile characteristics of FeTFTs enabled a 3T0C capacitor-free pixel circuit for pulse-width modulation (PWM) micro-LED operation, which simplified the conventional pixel structures (Fig. 7d). Stable operation was maintained under mechanical stress, including a 1 mm bending radius and 30% biaxial strain for 100 h.

Fig. 7 (a) Transfer characteristics of FeTFTs demonstrating partial switching with voltage pulses of varying amplitude (constant 200 ns width) and varying width (constant 5.5 V amplitude).¹²¹ Reproduced with permission from Lehninger et al., Adv. Electron. Mater. 7, 2100082 (2021). Copyright 2021 Wiley-VCH GmbH. (b) V_TH distribution before and after compensation programming for 10 TFTs, and transfer characteristics showing V_TH compensation through ferroelectric programming.¹²² Reproduced with permission from Joch et al., SID Symp. Dig. Tech. Pap. 55, 100 (2024). Copyright 2024 Wiley. (c) Conventional and FeTFT-based active-matrix circuits for displays. Light output power of an AlGaInP micro-LED with four programmed levels vs. retention time, and top-view images during operation.¹²³ Reproduced with permission from Lee et al., J. Soc. Inf. Disp. 33, 533 (2024). Copyright 2024 Wiley. (d) Hysteresis curves for stretched FeTFT on PDMS under 30% biaxial strain for 100 h. A 3T0C capacitor-free pixel circuit with the FeTFT, PWM timing diagram, and measured current at V_DS = 5.0 V.¹²⁴ Reproduced with permission from Jin et al., Nanoscale Adv. 5, 1316 (2023). Copyright 2023 Royal Society of Chemistry.

The display industry has already adopted OSs as the mainstream backplane technology due to their superior large-area uniformity and low-temperature processing compatibility. Ferroelectric integration explores additional functionalities through non-volatile operation beyond conventional oxide TFT capabilities. OS-FeTFTs display demonstrated programmable V_TH control achieving a 21-fold reduction in V_TH variation with degradation compensation. The non-volatile characteristics further enabled capacitor-free three-transistor zero-capacitor (3T0C) pixel architectures for PWM micro-LED applications, with mechanical flexibility at a 1 mm bending radius and 30% strain (Table 5). While ferroelectric layer integration adds process steps, the structural simplification offers potential value. However, OS-FeFET display applications remain exploratory with diverse approaches (V_TH compensation, capacitor-free pixels, and flexible implementations) yet to establish dominance. Critical trade-offs include circuit simplification benefits versus programming overhead, and refresh/recalibration requirements versus long-term V_TH stability. Key challenges include V_TH compensation validation over display lifetimes (>50 000 hours) under continuous operation, array-level uniformity across large panels (>10 inch) beyond current small-scale demonstrations, and flexible display reliability under realistic usage conditions. Commercialization requires demonstrating competitive manufacturing economics and clear advantages over mature LTPS and oxide TFT backplanes that already provide adequate performance for most display applications.

Table 5 Summary of device performance for OS-based FeFETs for display applications reported in the literature

Role	OS (deposition method)	Structure	MW (V)	Endurance	Retention	ION/IOFF	Ref.
VTH compensation	IGZO (sputter)	MFIS	0.7	N/A	∼10^4 s	∼10^6	121
VTH compensation	IGZO (sputter)	MFIS	0.6	N/A	N/A	∼10^6	122
VTH compensation	ITZO (sputter)	MFIS	3 (VD = 1 V)	∼10^8 (capacitor)	10^6 s	10^6	123
Constant current generation	IGO (sputter)	MISF	9.1 (VDS = 0.1 V)	∼10^4	2400 s	∼10^7	124

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3 Perspectives and future directions

While individual application domains have achieved significant device-level breakthroughs, the maturity levels vary considerably across applications. NAND and neuromorphic systems have progressed to array-level demonstrations, while DRAM and display applications remain at early device-level proof-of-concept stages. Nevertheless, several common challenges have emerged across multiple applications, such as array-level operation, manufacturing integration, and reliability validation. Array implementation requires solutions for device uniformity and array-specific issues, including disturb immunity, interlayer interference, and addressing schemes that would extend beyond individual device optimization. Moreover, manufacturing integration must maintain the advantages of low-temperature processing while meeting commercial fabrication requirements to ensure scalability.

Addressing system-level challenges requires deeper understanding of the OS–ferroelectric interface. Unlike silicon channels that form low-k IL limiting EOT scaling and increasing voltage, OS channels enable direct HfO₂ integration. However, long-term reliability requires systematic investigation. In Si-channel FeFETs, the IL causes wake-up behaviour, limits endurance to ∼10⁶ cycles, and necessitates long read-after-write delays (>10 ms).¹²⁵ OS-based FeFETs avoid these IL-related issues, achieving >10⁸ cycle endurance with immediate readout.¹²⁶ However, distinct challenges remain: asymmetric imprint causing read disturb,^127,128 polarization-state-dependent retention,^126,128 longer erase pulses from donor state ionization,¹²⁹ and hydrogen-related V_TH shifts.¹²⁹ Interface engineering, such as oxygen-controlling interlayers, can mitigate these mechanisms.¹²⁷ Furthermore, OSs enable low-temperature processing (<400 °C) versus poly-Si (>900 °C) critical for multi-tier integration. Deeper understanding of interface dynamics—V_O migration, hydrogen diffusion, and donor state kinetics—remains essential.

Channel engineering represents a relatively recent and limited research area for OS-FeFET development. While structural optimization has been extensively pursued, systematic channel material engineering offers pathways to address application-specific performance requirements. Initial studies explored ITO-IGZO heterojunctions that passivate deep-level defects through self-compensation,¹¹⁸ and oxygen-deficient intermediate channels providing sufficient depletion charge for full-loop polarization switching.⁷⁷ Recent work has expanded these concepts through IGZO composition tuning to balance mobility and bias stress stability,¹³⁰ and functional heterostructures (e.g., In₂O₃–ZnO) where oxygen-deficient layers enable efficient switching while high-mobility layers reduce inter-cell resistance.¹³¹ However, these demonstrations remain primarily at the discrete device level. Co-optimization of OS composition with ferroelectric switching dynamics, V_O kinetics, and array-level variability control remains in its early stages,^130,132,133 with validation in 3D architectures such as vertical GAA or multi-tier M3D structures yet to be explored. Further development of channel engineering approaches addressing these aspects holds potential to enhance the MW, cycling endurance, retention stability, and device uniformity in scaled systems.

The diverse requirements across applications highlight the need for systematic material optimization beyond IGZO. NAND and DRAM prioritize cycling endurance and retention stability, logic demands maximum mobility and drive current, neuromorphic systems require precise analog conductance control and displays need low I_OFF and a stable threshold voltage. Meeting these varying demands may require exploring binary (IGO, IZO, AZO, and ZTO), ternary (IGZO, IGTO, and IZTO), and quaternary (IGZTO) oxide systems with varying composition ratios, multiple channel stack design, and controlled crystallization. Building on the demonstrated channel engineering approaches, such systematic optimization could enable matching of channel properties to specific applications, advancing OS-FeFET technology through coordinated progress in architecture, interface engineering, and material design.

4 Conclusion

We have discussed the synergistic integration of OSs with HfO₂-based ferroelectrics across five key application domains, revealing how this combination addresses the fundamental limitations of conventional silicon-based technologies. The examination demonstrated that the negligible IL formation and low temperature processability enabled unique advantages across diverse applications. In NAND flash memory, diverse structural approaches and oxygen deficiency control in OS channels achieved substantial MW enhancement in FeNAND. Refresh-free DRAM architectures eliminated standby power through non-volatile 2T0C configurations, while neuromorphic computing demonstrated precise analog weight modulation through the MFMIS structure achieving competitive accuracy on standard benchmarks. Logic applications showcased enhanced functionality in CAM memory and significant energy efficiency improvement in monolithic 3D integration. Display technologies enabled substantial reduction in V_TH variation and capacitor-free pixel architectures through non-volatile characteristics.

While each application domain has achieved substantial device-level performance, the transition to practical implementation requires addressing common challenges, including array-level operation, manufacturing integration, and long-term reliability validation. Notably, channel engineering remains less extensively investigated, yet optimization of OS composition, interfacial properties, and heterostructure designs offers promising pathways to address the diverse performance requirements across all applications.

The diverse achievements across memory, computing, and display technologies demonstrate the versatility of OS-FeFET integration and establish a strong foundation for next-generation semiconductor systems. However, realizing commercial potential requires continued research in several critical areas. Fundamental understanding of defect mechanisms-particularly V_O dynamics and their impact on retention, endurance, and reliability phenomena-is essential for predictable operation. Further development in structural optimization, channel engineering through controlled crystallization and V_O control, and interface management represent promising pathways toward enhanced performance and reliability. Additionally, comprehensive array-level validation under realistic operating conditions remains necessary to bridge the gap between discrete device demonstration and practical implementations.

Conflicts of interest

There are no conflicts to declare.

Data availability

No new data were created or analyzed in this study. Data sharing is not applicable to this article.

Acknowledgements

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (NRF-2022M3H4A1A04068923), Ministry of Trade, Industry & Energy (MOTIE) grant funded by the Korean government (RS-2023-00235609, Proposal of 3D DRAM development direction from the process development of vertical stacked cell transistors), Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korean government(MSIT) (RS-2024-00399394, Development of PDK and a process integration platform for a new memory-CMOS co-integrated PIM system) and Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-(2025)-RS-2023-00253914) grant funded by the Korean government(MSIT).

Notes and references

1. S.-H. Lee, in 2016 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2016, pp. 111–118.
2. N. Chandrasekaran, N. Ramaswamy and C. Mouli, in 2020 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2020, pp. 1011–1018.
3. R. Clark, K. Tapily, K.-H. Yu, T. Hakamata, S. Consiglio, D. O'Meara, C. Wajda, J. Smith and G. Leusink, APL Mater., 2018, 6, 058203.
4. B. Wang, B. Gao, H. Wu and H. Qian, Microelectron. Eng., 2018, 192, 66–69.
5. N. Ramaswamy, T. Graettinger, G. Puzzilli, H. Liu, K. Prall, S. Gowda, A. Furnemont, C. Kim and K. Parat, in 2013 5th IEEE International Memory Workshop, IEEE, Monterey, CA, USA, 2013, pp. 5–8.
6. A. Torsi, Y. Zhao, H. Liu, T. Tanzawa, A. Goda, P. Kalavad and K. Parat, IEEE Trans. Electron Devices, 2011, 58, 11–16.
7. D. Resnati, A. Mannara, G. Nicosia, G. M. Paolucci, P. Tessariol, A. S. Spinelli, A. L. Lacaita and C. Monzio Compagnoni, IEEE Trans. Electron Devices, 2018, 65, 3199–3206.
8. K. Itoh, Y. Nakagome, S. Kimura and T. Watanabe, IEEE J. Solid-State Circuits, 1997, 32, 624–634.
9. J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li and C. J. Radens, IBM J. Res. Dev., 2002, 46, 187–212.
10. A. Spessot and H. Oh, IEEE Trans. Electron Devices, 2020, 67, 1382–1393.
11. W. Sun, J. Liu and Y. Yue, IEEE Netw., 2019, 33, 68–74.
12. T. S. Böscke, J. Muller, D. Brauhaus, U. Schroder and U. Bottger, in 2011 International Electron Devices Meeting, IEEE, Washington, DC, USA, 2011, pp. 2451–2454.
13. T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder and U. Böttger, Appl. Phys. Lett., 2011, 99, 102903.
14. U. Schroeder, M. H. Park, T. Mikolajick and C. S. Hwang, Nat. Rev. Mater., 2022, 7, 653–669.
15. J. Muller, T. S. Boscke, S. Muller, E. Yurchuk, P. Polakowski, J. Paul, D. Martin, T. Schenk, K. Khullar, A. Kersch, W. Weinreich, S. Riedel, K. Seidel, A. Kumar, T. M. Arruda, S. V. Kalinin, T. Schlosser, R. Boschke, R. Van Bentum, U. Schroder and T. Mikolajick, in 2013 IEEE International Electron Devices Meeting, IEEE, Washington, DC, USA, 2013, pp. 1081–1084.
16. L. Mazet, S. M. Yang, S. V. Kalinin, S. Schamm-Chardon and C. Dubourdieu, Sci. Technol. Adv. Mater., 2015, 16, 036005.
17. T. Mikolajick, S. Slesazeck, H. Mulaosmanovic, M. H. Park, S. Fichtner, P. D. Lomenzo, M. Hoffmann and U. Schroeder, J. Appl. Phys., 2021, 129, 100901.
18. J. Muller, E. Yurchuk, T. Schlosser, J. Paul, R. Hoffmann, S. Muller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kucher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schroder and T. Mikolajick, in 2012 Symposium on VLSI Technology (VLSIT), IEEE, Honolulu, HI, USA, 2012, pp. 25–26.
19. J. Müller, T. S. Böscke, U. Schröder, S. Mueller, D. Bräuhaus, U. Böttger, L. Frey and T. Mikolajick, Nano Lett., 2012, 12, 4318–4323.
20. Y. Kim, J. Hwang, C. Kim, G. Kang and S. Jeon, Phys. Status Solidi, 2025, e202500590.
21. N. L. Trinh, B. Gu, K. Yang, C. T. Nguyen, B. Lee, H.-M. Kim, H. Kim, Y. Kang, M. H. Park and H.-B.-R. Lee, ACS Nano, 2025, 19, 3562–3578.
22. M. Lee, J.-H. Kim, D. N. Le, S. Lee, S.-U. Song, R. Choi, Y. Ahn, S. W. Ryu, P.-R. Cha, C.-Y. Nam, S. Park, J. Kang, S. J. Kim and J. Kim, in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2024, pp. 1–2.
23. K. Toprasertpong, K. Tahara, Y. Hikosaka, K. Nakamura, H. Saito, M. Takenaka and S. Takagi, ACS Appl. Mater. Interfaces, 2022, 14, 51137–51148.
24. M. Si, X. Lyu, P. R. Shrestha, X. Sun, H. Wang, K. P. Cheung and P. D. Ye, Appl. Phys. Lett., 2019, 115, 072107.
25. S. S. Cheema, D. Kwon, N. Shanker, R. Dos Reis, S.-L. Hsu, J. Xiao, H. Zhang, R. Wagner, A. Datar, M. R. McCarter, C. R. Serrao, A. K. Yadav, G. Karbasian, C.-H. Hsu, A. J. Tan, L.-C. Wang, V. Thakare, X. Zhang, A. Mehta, E. Karapetrova, R. V. Chopdekar, P. Shafer, E. Arenholz, C. Hu, R. Proksch, R. Ramesh, J. Ciston and S. Salahuddin, Nature, 2020, 580, 478–482.
26. S. J. Kim, J. Mohan, S. R. Summerfelt and J. Kim, JOM, 2019, 71, 246–255.
27. J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick and L. Frey, Appl. Phys. Lett., 2011, 99, 112901.
28. S. Mueller, J. Mueller, A. Singh, S. Riedel, J. Sundqvist, U. Schroeder and T. Mikolajick, Adv. Funct. Mater., 2012, 22, 2412–2417.
29. J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger, J. Sundqvist, P. Kücher, T. Mikolajick and L. Frey, Appl. Phys. Lett., 2011, 99, 112901.
30. S. Mueller, J. Mueller, A. Singh, S. Riedel, J. Sundqvist, U. Schroeder and T. Mikolajick, Adv. Funct. Mater., 2012, 22, 2412–2417.
31. J. Müller, U. Schröder, T. S. Böscke, I. Müller, U. Böttger, L. Wilde, J. Sundqvist, M. Lemberger, P. Kücher, T. Mikolajick and L. Frey, J. Appl. Phys., 2011, 110, 114113.
32. S. Mueller, C. Adelmann, A. Singh, S. Van Elshocht, U. Schroeder and T. Mikolajick, ECS J. Solid State Sci. Technol., 2012, 1, N123–N126.
33. R. Cao, Y. Wang, S. Zhao, Y. Yang, X. Zhao, W. Wang, X. Zhang, H. Lv, Q. Liu and M. Liu, IEEE Electron Device Lett., 2018, 39, 1207–1210.
34. M. H. Park, Y. H. Lee, T. Mikolajick, U. Schroeder and C. S. Hwang, Adv. Electron. Mater., 2019, 5, 1800522.
35. T. Shiraishi, K. Katayama, T. Yokouchi, T. Shimizu, T. Oikawa, O. Sakata, H. Uchida, Y. Imai, T. Kiguchi, T. J. Konno and H. Funakubo, Appl. Phys. Lett., 2016, 108, 262904.
36. Y. Goh, S. H. Cho, S.-H. K. Park and S. Jeon, Nanoscale, 2020, 12, 9024–9031.
37. K. Yang, G.-Y. Kim, J. J. Ryu, D. H. Lee, J. Y. Park, S. H. Kim, G. H. Park, G. T. Yu, G. H. Kim, S. Y. Choi and M. H. Park, Mater. Sci. Semicond. Process., 2023, 164, 107565.
38. M. Pešić, F. P. G. Fengler, L. Larcher, A. Padovani, T. Schenk, E. D. Grimley, X. Sang, J. M. LeBeau, S. Slesazeck, U. Schroeder and T. Mikolajick, Adv. Funct. Mater., 2016, 26, 4601–4612.
39. T. Mikolajick, S. Slesazeck, M. H. Park and U. Schroeder, MRS Bull., 2018, 43, 340–346.
40. C. R. M. Grovenor, J. Phys. C: Solid State Phys., 1985, 18, 4079.
41. E. Fortunato, P. Barquinha and R. Martins, Adv. Mater., 2012, 24, 2945–2986.
42. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano and H. Hosono, Nature, 2004, 432, 488–492.
43. H. Hosono and H. Kumomi, Amorphous Oxide Semiconductors: IGZO and Related Materials for Display and Memory, Wiley, 2022.
44. J. F. Wager, Inf. Disp., 2014, 30, 26–29.
45. T. Kim, C. H. Choi, J. S. Hur, D. Ha, B. J. Kuh, Y. Kim, M. H. Cho, S. Kim and J. K. Jeong, Adv. Mater., 2023, 35, 2204663.
46. T. Kamiya and H. Hosono, NPG Asia Mater., 2010, 2, 15–22.
47. A. J. Tan, A. K. Yadav, K. Chatterjee, D. Kwon, S. Kim, C. Hu and S. Salahuddin, IEEE Electron Device Lett., 2018, 39, 95–98.
48. J. S. Hur, S. Lee, J. Moon, H.-G. Jung, J. Jeon, S. H. Yoon, J.-H. Park and J. K. Jeong, Nanoscale Horiz., 2024, 9, 934–945.
49. T. Schenk, M. Hoffmann, J. Ocker, M. Pešić, T. Mikolajick and U. Schroeder, ACS Appl. Mater. Interfaces, 2015, 7, 20224–20233.
50. K. Dhananjay, P. Shukla, V. F. Pavlidis, A. Coskun and E. Salman, IEEE Trans. Circuits Syst., II Express Briefs, 2021, 68, 837–843.
51. M. M. Shulaker, T. F. Wu, M. M. Sabry, H. Wei, H.-S. Philip Wong and S. Mitra, in Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE Conference Publications, Grenoble, France, 2015, pp. 1197–1202.
52. M. H. Cho, H. Seol, A. Song, S. Choi, Y. Song, P. S. Yun, K.-B. Chung, J. U. Bae, K.-S. Park and J. K. Jeong, IEEE Trans. Electron Devices, 2019, 66, 1783–1788.
53. H. J. Yang, H. J. Seul, M. J. Kim, Y. Kim, H. C. Cho, M. H. Cho, Y. H. Song, H. Yang and J. K. Jeong, ACS Appl. Mater. Interfaces, 2020, 12, 52937–52951.
54. T. Kamiya, K. Nomura and H. Hosono, Sci. Technol. Adv. Mater., 2010, 11, 044305.
55. K. Yang, S. H. Kim, H. W. Jeong, D. H. Lee, G. H. Park, Y. Lee and M. H. Park, Chem. Mater., 2023, 35, 2219–2237.
56. M. H. Park, D. H. Lee, K. Yang, J.-Y. Park, G. T. Yu, H. W. Park, M. Materano, T. Mittmann, P. D. Lomenzo, T. Mikolajick, U. Schroeder and C. S. Hwang, J. Mater. Chem. C, 2020, 8, 10526–10550.
57. M. H. Park, Y. H. Lee, T. Mikolajick, U. Schroeder and C. S. Hwang, MRS Commun., 2018, 8, 795–808.
58. J. Y. Kim, M.-J. Choi and H. W. Jang, APL Mater., 2021, 9, 021102.
59. I. Kim and J. Lee, Adv. Mater., 2023, 35, 2206864.
60. J. Hwang, Y. Goh and S. Jeon, Small, 2024, 20, 2305271.
61. T. Song and A. I. Khan, Nat. Electron., 2025, 8, 1132–1133.
62. S. Fujii, T. F. Lu, K. Ikeda, S. Y. Chang, K. Sakamoto, L. W. Chung, M. Okajima, J.-Y. Tsai, T. Kuroda, C. P. Hao, S. Miyano, M. C. Peng, K. Okano, M. Sillero, A. Kajita, C. L. Huang, T. Fujimaki and C.-L. Shih, in 2024 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2024, pp. 1–4.
63. S. Choi, B. Kim, J. K. Jeong and Y. H. Song, IEEE Trans. Electron Devices, 2019, 66, 4739–4744.
64. D. Ha, Y. Lee, S. Yoo, W. Lee, M. H. Cho, K. Yoo, S. M. Lee, S. Lee, M. Terai, T. H. Lee, J. H. Bae, K. J. Moon, C. Sung, M. Hong, D. G. Cho, K. Lee, S. W. Park, K. Park, B. J. Kuh, S. Hyun, S. J. Ahn and J. H. Song, in 2024 IEEE International Memory Workshop (IMW), IEEE, Seoul, Republic of Korea, 2024, pp. 1–4.
65. F. F. Athena, E. Ambrosi, K. Jana, C. H. Wu, J. Hartanto, Y. M. Lee, C. C. Kuo, S. Liu, B. Saini, C. C. Wang, C. F. Hsu, G. Zeevi, X. Wang, J. Kang, E. Pop, T. Y. Lee, P. C. McIntyre, H.-S. P. Wong and X. Y. Bao, in 2024 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2024, pp. 1–4.
66. J. Kim, J. Kim, H. S. Choi, D. H. Han, H. W. Jeong, Y. Lee and M. H. Park, Electron. Mater. Lett., 2025 DOI:10.1007/s13391-025-00621-4.
67. K. Parat and A. Goda, in 2018 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, 2018, pp. 211–214.
68. J. Hwang, J. Seo, Y. Lee, S. Park, J. Leem, J. Kim, T. Hong, S. Jeong, K. Lee, H. Heo, H. Lee, P. Jang, K. Park, M. Lee, S. Baik, J. Kim, H. Kang, M. Jang, J. Lee, G. Cho, J. Lee, B. Lee, H. Jang, S. Park, J. Kim, S. Lee, S. Aritome, S. Hong and S. Park, in 2011 International Electron Devices Meeting (IEDM), IEEE, Washington, DC, USA, 2011, pp. 911–914.
69. A. Goda, IEEE Trans. Electron Devices, 2020, 67, 1373–1381.
70. S. Aritome, in Nand Flash Memory Technologies, Wiley, 1st edn, 2015, pp. 129–193.
71. T. Arai, N. Morosawa, K. Tokunaga, Y. Terai, E. Fukumoto, T. Fujimori, T. Nakayama, T. Yamaguchi and T. Sasaoka, Symp. Dig. Tech. Pap., 2010, 41, 1033–1036.
72. P. Sharma, K. Florent, D. Resnati, A. Mauri, J. Yue, J. Ahn, A. Fayrushin, E. Camerlenghi, P. Fantini, A. Goda, T. Kim and R. Hill, in 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2025, pp. 1–3.
73. I.-J. Kim, M.-K. Kim and J.-S. Lee, IEEE Electron Device Lett., 2023, 44, 249–252.
74. F. Mo, X. Mei, T. Saraya, T. Hiramoto and M. Kobayashi, Jpn. J. Appl. Phys., 2022, 61, SC1013.
75. S. Jeong, C. Han, J. Yim, J. Kim, K. R. Kwon, S. Kim, E. C. Park, J. W. You, R. Choi and D. Kwon, IEEE Electron Device Lett., 2023, 44, 749–752.
76. H. Joh, G. Kim, J. Ock, S. Kim, S. Lee, S. Lee, K. Kim, S. Lim, J. Woo, W. Kim, D. Ha, J. Ahn and S. Jeon, in 2024 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2024, pp. 1–4.
77. S. Yoo, D. Kim, D.-H. Choe, H. J. Lee, Y. Lee, S. Jo, Y. Park, K. H. Kim, K. Jung, M. Jung, K.-H. Lee, J.-E. Yang, S. Kim and S.-G. Nam, in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Honolulu, HI, USA, 2024, pp. 1–2.
78. H. Joh, S. Lee, J. Ahn and S. Jeon, J. Mater. Chem. C, 2024, 12, 15435–15443.
79. M.-K. Kim, I.-J. Kim and J.-S. Lee, Sci. Adv., 2021, 7, eabe1341.
80. I.-J. Kim, M.-K. Kim and J.-S. Lee, Appl. Phys. Lett., 2022, 121, 042901.
81. I.-J. Kim, J. Choi and J.-S. Lee, ACS Appl. Mater. Interfaces, 2024, 16, 33763–33770.
82. S. Y. Cha, in 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, Kyoto, Japan, 2025, pp. 1–4.
83. K. Kim and J. Lee, IEEE Electron Device Lett., 2009, 30, 846–848.
84. R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous and A. R. LeBlanc, IEEE J. Solid State Circ., 1974, 9, 256–268.
85. A. Belmonte, H. Oh, N. Rassoul, G. L. Donadio, J. Mitard, H. Dekkers, R. Delhougne, S. Subhechha, A. Chasin, M. J. Van Setten, L. Kljucar, M. Mao, H. Puliyalil, M. Pak, L. Teugels, D. Tsvetanova, K. Banerjee, L. Souriau, Z. Tokei, L. Goux and G. S. Kar, in 2020 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2020, pp. 2821–2824.
86. A. Belmonte, H. Oh, S. Subhechha, N. Rassoul, H. Hody, H. Dekkers, R. Delhougne, L. Ricotti, K. Banerjee, A. Chasin, M. J. Van Setten, H. Puliyalil, M. Pak, L. Teugels, D. Tsvetanova, K. Vandersmissen, S. Kundu, J. Heijlen, D. Batuk, J. Geypen, L. Goux and G. S. Kar, in 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2021, pp. 1061–1064.
87. X. Duan, K. Huang, J. Feng, J. Niu, H. Qin, S. Yin, G. Jiao, D. Leonelli, X. Zhao, Z. Wang, W. Jing, Z. Wang, Y. Wu, J. Xu, Q. Chen, X. Chuai, C. Lu, W. Wang, G. Yang, D. Geng, L. Li and M. Liu, IEEE Trans. Electron Devices, 2022, 69, 2196–2202.
88. K. Xiao, J. Wan, H. Xie, Y. Zhu, T. Tian, W. Zhang, Y. Chen, J. Zhang, L. Zhou, S. Dai, Z. Xu, W. Bao and P. Zhou, Nat. Commun., 2024, 15, 9782.
89. Y. Lee, S. Lee, J. Choi, N. Ghenzi, J. Han and C. S. Hwang, Phys. Status Solidi RRL, 2025, 19, 2500131.
90. J. Liang, P. Yuan, Y. Yu, J. Xiang, Z. Zhu, M. Zhou, F. Shao, Y. Lu, J. Dai, S. Yi, G. Wang, J. Zhang, B. Kang and C. Zhao, Jpn. J. Appl. Phys., 2024, 63, 06SP05.
91. T. H. Noh, S. Chen, H.-B. Kim, T. Jin, S. M. Park, S. U. An, X. Sun, J. Kim, J.-H. Han, J.-H. Ahn, D.-H. Ahn and Y. Kim, Nanoscale, 2024, 16, 16467–16476.
92. W. C.-Y. Ma, C.-J. Su, Y.-J. Lee, K.-H. Kao, T.-H. Chang, J.-C. Chang, P.-H. Wu, C.-L. Yen and J.-H. Lin, Semicond. Sci. Technol., 2022, 37, 045003.
93. S. Yu, Proc. IEEE, 2018, 106, 260–285.
94. S. Oh, T. Kim, M. Kwak, J. Song, J. Woo, S. Jeon, I. K. Yoo and H. Hwang, IEEE Electron Device Lett., 2017, 38, 732–735.
95. B.-E. Park, H. Ishiwara, M. Okuyama, S. Sakai and S.-M. Yoon, Ferroelectric-Gate Field Effect Transistor Memories: Device Physics and Applications, Springer Singapore, Singapore, 2020, vol. 131.
96. M.-K. Kim, I.-J. Kim and J.-S. Lee, Appl. Phys. Lett., 2021, 118, 032902.
97. P. Yang, P. Tong, H. Xu, S. Liu, C. Chen, Y. Zhang, S. Yu, W. Wang, R. Cao, H. Liu, L. Liao and Q. Li, J. Mater. Sci. Technol., 2025, 231, 20–29.
98. M.-K. Kim and J.-S. Lee, Nano Lett., 2019, 19, 2044–2050.
99. S.-N. Choi, S.-E. Moon and S.-M. Yoon, Nanotechnology, 2021, 32, 085709.
100. J. Kim, E. C. Park, W. Shin, R.-H. Koo, C.-H. Han, H. Y. Kang, T. G. Yang, Y. Goh, K. Lee, D. Ha, S. S. Cheema, J. K. Jeong and D. Kwon, Nat. Commun., 2024, 15, 9147.
101. D. Kwon, E. C. Park, W. Shin, R.-H. Koo, J. Hwang, J.-H. Bae, D. Kwon and J.-H. Lee, Adv. Intell. Syst., 2023, 5, 2300125.
102. Y. Van De Burgt, A. Melianas, S. T. Keene, G. Malliaras and A. Salleo, Nat. Electron., 2018, 1, 386–397.
103. I.-J. Kim, M.-K. Kim and J.-S. Lee, Nat. Commun., 2023, 14, 504.
104. E. C. Park, J. Kim, J. Ko, W. Shin, M.-C. Nguyen, M. Song, K.-R. Kwon, R.-H. Koo and D. Kwon, Nano Energy, 2025, 139, 110877.
105. X. Yin, M. Niemier and X. S. Hu, in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, IEEE, Lausanne, Switzerland, 2017, pp. 1444–1449.
106. H. Joh, S. Nam, M. Jung, H. Shin, S. H. Cho and S. Jeon, ACS Appl. Mater. Interfaces, 2023, 15, 51339–51349.
107. C. Sun, K. Han, S. Samanta, Q. Kong, J. Zhang, H. Xu, X. Wang, A. Kumar, C. Wang, Z. Zheng, X. Yin, K. Ni and X. Gong, IEEE Trans. Electron Devices, 2022, 69, 5262–5269.
108. K. Ni, X. Yin, A. F. Laguna, S. Joshi, S. Dünkel, M. Trentzsch, J. Müller, S. Beyer, M. Niemier, X. S. Hu and S. Datta, Nat. Electron., 2019, 2, 521–529.
109. C. Li, F. Muller, T. Ali, R. Olivo, M. Imani, S. Deng, C. Zhuo, T. Kampfe, X. Yin and K. Ni, in 2020 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2020, pp. 2931–2934.
110. A. J. Tan, K. Chatterjee, J. Zhou, D. Kwon, Y.-H. Liao, S. Cheema, C. Hu and S. Salahuddin, IEEE Electron Device Lett., 2020, 41, 240–243.
111. M. R. Sk, S. Thunder, D. Lehninger, S. Sanctis, Y. Raffel, M. Lederer, M. P. M. Jank, T. Kämpfe, S. De and B. Chakrabarti, ACS Appl. Electron. Mater., 2023, 5, 812–820.
112. C. Sun, K. Han, S. Samanta, Q. Kong, J. Zhang, H. Xu, X. Wang, A. Kumar, C. Wang, Z. Zheng, X. Yin, K. Ni and X. Gong, Symposium on VLSI Technology, 2021, pp. 1–2.
113. M.-C. Nguyen, E. C. Park, R. Choi, D. S. Jeong and D. Kwon, ACS Appl. Electron. Mater., 2025, 7, 2404–2412.
114. S. W. Kim, W. Shin, R. Koo, J. Kim, J. Im, D. Koh, J. Lee, S. S. Cheema and D. Kwon, Small, 2025, 21, 2406376.
115. A. Thean, S.-H. Tsai, C.-K. Chen, M. Sivan, B. Tang, S. Hooda, Z. Fang, J. Pan, J. Leong, H. Veluri and E. Zamburg, in 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022, pp. 1221–1224.
116. D. Kim, H. Jeong, G. Pyo, S. J. Heo, S. Baik, S. Kim, H. S. Choi, H. Kwon and J. E. Jang, Adv. Sci., 2024, 11, 2401250.
117. C.-K. Chen, Z. Fang, S. Hooda, M. Lal, U. Chand, Z. Xu, J. Pan, S.-H. Tsai, E. Zamburg and A. V.-Y. Thean, in 2022 International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2022, pp. 611–614.
118. C.-K. Chen, S. Hooda, Z. Fang, M. Lal, Z. Xu, J. Pan, S.-H. Tsai, E. Zamburg and A. V.-Y. Thean, IEEE Trans. Electron Devices, 2023, 70, 2098–2105.
119. Z. Lin, Z. Zhang, C. Niu, H. Dou, K. Xu, M. Md Fahimul Islam, J.-Y. Lin, C. Sung, M. Hong, D. Ha, H. Wang, M. Ashraful Alam and P. D. Ye, IEEE Trans. Electron Devices, 2024, 71, 7984–7991.
120. S. Dutta, H. Ye, W. Chakraborty, Y.-C. Luo, M. S. Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu and S. Datta, in 2020 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2020, pp. 3641–3644.
121. D. Lehninger, M. Ellinger, T. Ali, S. Li, K. Mertens, M. Lederer, R. Olivio, T. Kämpfe, N. Hanisch, K. Biedermann, M. Rudolph, V. Brackmann, S. Sanctis, M. P. M. Jank and K. Seidel, Adv. Electrode Mater., 2021, 7, 2100082.
122. D. Joch, D. Lehninger, A. Sunil, S. Sanctis, T. Lang, J. Zeltner, P. Wartenberg, K. Seidel and M. P. M. Jank, Symp. Dig. Tech. Pap., 2024, 55, 100–103.
123. T. Jin, S. Kim, J.-H. Han, D.-H. Ahn, S. U. An, T. H. Noh, X. Sun, C. J. Kim, J. Park and Y. Kim, Nanoscale Adv., 2023, 5, 1316–1322.
124. H. Lee, J. Lee, J. Noh, S. Roy, J. Kim and J. Jang, J. Soc. Inf. Disp., 2025, 33, 533–542.
125. A. Agarwal, A. M. Walke, N. Ronchi, K.-H. Kao and J. Van Houdt, IEEE Trans. Electron Devices, 2024, 71, 4619–4625.
126. F. Mo, T. Saraya, T. Hiramoto and M. Kobayashi, Appl. Phys. Express, 2020, 13, 074005.
127. Z. Chen, N. Ronchi, A. Walke, K. Banerjee, M. I. Popovici, K. Katcko, G. Van Den Bosch, M. Rosmeulen, V. Afanas’Ev and J. Van Houdt, in 2023 IEEE International Memory Workshop (IMW), IEEE, Monterey, CA, USA, 2023, pp. 1–4.
128. Z. Chen, N. Ronchi, K. Banerjee, R. Izmailov, A. M. Walke, M. I. Popovici, H. Dekkers, A. Pavel, G. Van Den Bosch, M. Rosmeulen, V. Afanas’Ev and J. Van Houdt, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), IEEE, Bruges, Belgium, 2024, pp. 661–664.
129. Z. Chen, N. Ronchi, R. Izmailov, H. Tang, M. I. Popovici, H. Dekkers, A. Pavel, G. V. D. Bosch, M. Rosmeulen, V. V. Afanas’Ev and J. Van Houdt, IEEE J. Electron Devices Soc., 2025, 13, 245–251.
130. Z. Chen, H.-C. Kim, W. Zheng, R. Izmailov, B. Truijen, S. Subhechha, A. M. Walke, A. Chasin, M. I. Popovici, J. Li, A. Kruv, H. Tang, F. Xi, G. Van Den Bosch, M. Rosmeulen, N. Ronchi, V. Afanas’ev and J. Van Houdt, in 2024 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2024, pp. 1–4.
131. C. Sun, X. Li, D. Zhang, W. Shi, Y. Chen, G. Liu, R. Shao, Q. Kong, Y. Wang, L. Jiao, Z. Zhou, Y. Feng, X. Wang, K. Ni and X. Gong, in 2025 IEEE International Electron Devices Meeting (IEDM), IEEE, San Francisco, CA, USA, 2025, pp. 1–4.
132. J. Hwang, C. Kim, J. Ahn and S. Jeon, J. Mater. Chem. C, 2025, 13, 23819–23830.
133. M. M. Hasan, M. M. Islam, R. N. Bukke, E. Tokumitsu, H.-Y. Chu, S. C. Kim and J. Jang, IEEE Electron Device Lett., 2022, 43, 725–728.

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